Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The low power has been the main concern for the VLSI industry with the technology scaling in CMOS process from 130 nm to 22nm. The presentation here gives a brief idea about the several low power VLSI techniques being used in VLSI circuits to reduce the power and delay. for any query feel free to visit us at: http://www.siliconmentor.com/
Power Gating Based Ground Bounce Noise ReductionIJERA Editor
As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The low power has been the main concern for the VLSI industry with the technology scaling in CMOS process from 130 nm to 22nm. The presentation here gives a brief idea about the several low power VLSI techniques being used in VLSI circuits to reduce the power and delay. for any query feel free to visit us at: http://www.siliconmentor.com/
Power Gating Based Ground Bounce Noise ReductionIJERA Editor
As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of vco using current mode logic with low supply sensitivityeSAT Journals
Abstract The function of an oscillator is to convert dc energy into RF. Voltage Controlled Oscillator (VCO) is a type of oscillator whose output frequency can be varied by a control voltage. Here the VCO is designed using 0.18μm CMOS-RF technology using current mode logic. The Current mode logic is the fastest logic and is mainly used in Clock and Data Recovery applications. Current mode logic (CML) is a differential logic and provides noise immunity. Using the proposed design the current mode logic VCO operates with a supply voltage of 1.8 V and frequency varies from 2 MHz to 2.5 MHz. Its normalized supply sensitivity is 0.976 and optimum sensitivity is 0.966. Keywords: VCO, Supply sensitivity, CML, Ring oscillator.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
These slides presents an introduction to distributed generators integration in distribution system. Later its modelling, control, protection aspects will be presented.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Power gating is the main power reduction techniques for the static power. As long as technology scaling is taking place, static power becomes paramount important factor to the VLSI designs.Therefore Power gating is the recent power reduction technique that is actively in research areas.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
Matlab/simulink simulation of unified power quality conditioner-battery energ...IJECEIAES
This paper presents performance analysis of Unified Power Quality Conditioner-Battery Energy Storage (UPQC-BES) system supplied by Photovoltaic (PV)-Wind Hybrid connected to three phase three wire (3P3W) of 380 volt (L-L) and 50 hertz distribution system. The performance of supply system is compared with two renewable energy (RE) sources i.e. PV and Wind, respectively. Fuzzy Logic Controller (FLC) is implemented to maintain DC voltage across the capacitor under disturbance scenarios of source and load as well as to compare the results with Proportional Intergral (PI) controller. There are six scenarios of disturbance i.e. (1) non-linear load (NL), (2) unbalance and nonlinear load (Unba-NL), (3) distortion supply and non-linear load (Dis-NL), (4) sag and non-linear load (Sag-NL), (5) swell and non-linear load (Swell-NL), and (6) interruption and non-linear load (Inter-NL). In disturbance scenario 1 to 5, implementation of FLC on UPQC-BES system supplied by three RE sources is able to obtain average THD of load voltage/source current slightly better than PI. Furthermore under scenario 6, FLC applied on UPQC-BES system supplied by three RE sources gives significantly better result of average THD of load voltage/source current than PI. This research is simulated using Matlab/Simulink.
Implementation of pull up pull-down network for energy optimization in full a...IJARIIT
Nowadays the requirements of energy optimized low power circuits in higher-end applications such as
communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power
circuits but the static power dissipation need to improve such kind of circuits. The conventional topology has been
implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an
unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the
static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC
180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to
reduce the static power dissipation in full adder is used to improve the operating speed of each individual.
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER ...VLSICS Design
The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a
rapidly growing research area driven by a wide range of emerging energy constrained applications such
as wireless sensor network, portable medical devices and brain implants. The asynchronous design
techniques allow the construction of systems which are samples driven, which means they only dissipate
dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous
design over conventional synchronous circuits allows them to be energy efficient. However the
implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandard
synchronous design tools and modelling languages. This paper devises a novel asynchronous
design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is
synthesizable and suitable for implementation using conventional synchronous systems design flow and
tools. The proposed design is based on a modified version of the micropipline architecture and it is
constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been
developed on an FPGA, and systematically verified. The results prove correct functionality of the novel
design and a superior performance compared to a synchronous FIR implementation. The findings of this
work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and
performance benefits.
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design of vco using current mode logic with low supply sensitivityeSAT Journals
Abstract The function of an oscillator is to convert dc energy into RF. Voltage Controlled Oscillator (VCO) is a type of oscillator whose output frequency can be varied by a control voltage. Here the VCO is designed using 0.18μm CMOS-RF technology using current mode logic. The Current mode logic is the fastest logic and is mainly used in Clock and Data Recovery applications. Current mode logic (CML) is a differential logic and provides noise immunity. Using the proposed design the current mode logic VCO operates with a supply voltage of 1.8 V and frequency varies from 2 MHz to 2.5 MHz. Its normalized supply sensitivity is 0.976 and optimum sensitivity is 0.966. Keywords: VCO, Supply sensitivity, CML, Ring oscillator.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
These slides presents an introduction to distributed generators integration in distribution system. Later its modelling, control, protection aspects will be presented.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Power gating is the main power reduction techniques for the static power. As long as technology scaling is taking place, static power becomes paramount important factor to the VLSI designs.Therefore Power gating is the recent power reduction technique that is actively in research areas.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
The Approach on Influence of Biasing Circuit in Wideband Low Noise Amplifier ...IJEACS
This proposed work investigates the effects of biasing
circuit in the ultra-wideband microwave low noise amplifier
which operates between 3GHz to 10GHz. The complete circuit is
visualized the importance of every component in the design with
respect to linear measurements like Gain, Noise Figure, Return
loss under unconditionally stable condition. The design and
realization are made by using Hybrid Microwave integrated
circuit in AWR microwave office. The thing that is absolutely
necessary and frequently the difficult step in the design of an
LNA is 'biasing circuit design'. The difficulty situation arises
because traditional methods LNA by using S-parameters data
files in EDA tools provides almost all linear measurements.
Hence a number of time consuming iterations of different biasing
circuits with optimization methods may be required to reach
targeted specifications with the fixed operating point at the
desired points in the load line. Considering this behavior, various
alternate biasing circuit schemes are prepared and founded the
results associated with it. Furthermore, this paper unmistakably
clarifies the impacts of the biasing circuit by utilizing
intermodulation and harmonics distortion technique for
portrayal characterization. Different cases and sorts of the
biasing circuits with various biasing focuses have been tested and given clear perspective of the biasing ideas.
Matlab/simulink simulation of unified power quality conditioner-battery energ...IJECEIAES
This paper presents performance analysis of Unified Power Quality Conditioner-Battery Energy Storage (UPQC-BES) system supplied by Photovoltaic (PV)-Wind Hybrid connected to three phase three wire (3P3W) of 380 volt (L-L) and 50 hertz distribution system. The performance of supply system is compared with two renewable energy (RE) sources i.e. PV and Wind, respectively. Fuzzy Logic Controller (FLC) is implemented to maintain DC voltage across the capacitor under disturbance scenarios of source and load as well as to compare the results with Proportional Intergral (PI) controller. There are six scenarios of disturbance i.e. (1) non-linear load (NL), (2) unbalance and nonlinear load (Unba-NL), (3) distortion supply and non-linear load (Dis-NL), (4) sag and non-linear load (Sag-NL), (5) swell and non-linear load (Swell-NL), and (6) interruption and non-linear load (Inter-NL). In disturbance scenario 1 to 5, implementation of FLC on UPQC-BES system supplied by three RE sources is able to obtain average THD of load voltage/source current slightly better than PI. Furthermore under scenario 6, FLC applied on UPQC-BES system supplied by three RE sources gives significantly better result of average THD of load voltage/source current than PI. This research is simulated using Matlab/Simulink.
Implementation of pull up pull-down network for energy optimization in full a...IJARIIT
Nowadays the requirements of energy optimized low power circuits in higher-end applications such as
communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power
circuits but the static power dissipation need to improve such kind of circuits. The conventional topology has been
implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an
unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the
static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC
180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to
reduce the static power dissipation in full adder is used to improve the operating speed of each individual.
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER ...VLSICS Design
The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a
rapidly growing research area driven by a wide range of emerging energy constrained applications such
as wireless sensor network, portable medical devices and brain implants. The asynchronous design
techniques allow the construction of systems which are samples driven, which means they only dissipate
dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous
design over conventional synchronous circuits allows them to be energy efficient. However the
implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandard
synchronous design tools and modelling languages. This paper devises a novel asynchronous
design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is
synthesizable and suitable for implementation using conventional synchronous systems design flow and
tools. The proposed design is based on a modified version of the micropipline architecture and it is
constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been
developed on an FPGA, and systematically verified. The results prove correct functionality of the novel
design and a superior performance compared to a synchronous FIR implementation. The findings of this
work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and
performance benefits.
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
This paper presents a novel Handover mechanism to minimize target Femto Access Points (FAPs) list
during macro-to-femto and femto-to-femto handover in LTE based Macro-Femto Heterogeneous Networks.
HandOver is the procedure that transfers an ongoing call from one cell to another as the users move
through the coverage area of cellular system. The femtocell has a limited coverage area (15 meters to 30
meters), and subsequently, HandOver is decided based on mobile User Equipment (UE) speed for handover
between macrocell-to-femtocell and femtocell-to-femtocell. In the existing networks, for handover
procedure, serving Base Station will decide the cell selection based on mostly the signal strength of the
neighbouring femtocells. This information is provided by the Measurement Reports sent by the
corresponding UE. In this paper, we present a novel handover management scheme which considers both
the Received Signal Strength and Cell Load of the target Femtocells for making the Handover decision.
This proposed scheme for macro-femto heterogeneous network reduces the number of target FAPs to avoid
handover to overloaded femtocells and also reduce the number of handovers.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
An integrated approach for designing and testing specific processorsVLSICS Design
This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
A new design for fault tolerant and fault recoverable ALU System has been proposed in this paper. Reliability is one of the most critical factors that have to be considered during the designing phase of any IC. In critical applications like Medical equipment & Military applications this reliability factor plays a
very critical role in determining the acceptance of product. Insertion of special modules in the main design for reliability enhancement will give considerable amount of area & power penalty. So, a novel approach to this problem is to find ways for reusing the already available components in digital system in efficient way to implement recoverable methodologies. Triple Modular Redundancy (TMR) has traditionally used
for protecting digital logic from the SEUs (single event upset) by triplicating the critical components of the system to give fault tolerance to system. ScTMR- Scan chain-based error recovery TMR technique provides recovery for all internal faults. ScTMR uses a roll-forward approach and employs the scan chain implemented in the circuits for testability purposes to recover the system to fault-free state. The proposed
design will incorporate a ScTMR controller over TMR system of ALU and will make the system fault tolerant and fault recoverable. Hence, proposed design will be more efficient & reliable to use in critical applications, than any other design present till today.
DUALISTIC THRESHOLD BASED MIN-MAX METHOD FOR VOICE SIGNAL ENHANCEMENTVLSICS Design
In this article, unwanted transitory assessment is specified by averaging previous phantom power
standards and through a levelling stricture that is in step by the symbol existence likelihood in sub-bands.
A two threshold based min-max method is proposed that we compare with the recursive averaging (RA)
approach for unwanted transient assessment with SAL (spectral amplitude with logarithm assessment) in
voice signal enrichment .The SAL procedure includes a transient assessment and the unwanted transient
PSDs in virtual stationary form, and enrichment of voice signal. It is proficient of tracing the incoming
signal rapid variations in spectra and supports to assessment of PSD for transients effectively. The
unwanted transient assessment is much efficient by proposed method as compared to SAL method and RA
in terms of the voice signal power to noise ratio (SNR). And finally by simulation modelling we show the
results.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
IMPLEMENTATION OF SDC - SDF ARCHITECTURE FOR RADIX-4 FFT VLSICS Design
Very large scale integration and Digital signal processing are the very crucial technologies from the last
few decades. DSP applications require high performance, low area and low power VLSI circuits. This
paper is discussing about FFT which is one of the vital component in the digital signal processing. In this
Paper, we propose a single path delay commutator–feedback (SDC-SDF) Architecture for Radix-4 FFT
and presented its simulation and synthesis results. The Radix-4 FFT architecture consists of log4 N-1 SDC
Stages and 1 SDF stage. Previously, the radix-2 SDC-SDF (Single path delay commutator-feedback) FFT
architecture was includes log2 N-1 SDC Stages and 1 SDF stage. The proposed Radix-4 SDC-SDF
architecture reduces the number of multiplications and additions as well as number of stages which
achieves reduced area and low power. The resultant architecture is simulated using Modelsim, design
verification and synthesis results are done using Xilinx ISE. The proposed architecture is compared with
Radix-2 SDC-SDF FFT and it can achieve less area as well as low power
DESIGN AND IMPLEMENTATION OF 10 BIT, 2MS/s SPLIT SAR ADC USING 0.18um CMOS TE...VLSICS Design
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is
designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample
and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC
using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using
Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio (SDR) with high degree of flexibility and low power consumption has been a major challenge to the
scientific community ever since its conception. The basic philosophy of SDR is to implement different modulation or demodulation schemes on the same underlying hardware. Currently available high performance DSP processors, optimized with ‘Very Large Instruction Word (VLIW)’ architecture and multiply and accumulate (MAC) units, are unable to meet the near real time speed requirements of
Software Defined Radios (SDR) due to their inherent sequential execution of compute intensive signal
processing algorithms. Moreover, their power dissipation is considerably high. Even though, Application Specific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of their lack of flexibility. Various references on FPGA based implementations of reconfigurable architectures for SDRs are also available. However, the Look-up Table (LUT) based implementations of FPGAs are not
optimum and therefore, cannot offer highest performance at low silicon cost. Keeping this view, this paper presents the design of a configurable communication processor for Software Defined Radio. The proposed
scheme features the performance of an ASIC based design combined with the flexibility of software. Experimental results reveal that the proposed architecture has minimum hardware requirement, improved silicon area utilization and low power dissipation.
In this paper, we propose and investigate a schottky tunneling source impact ionization MOSFET (STSIMOS)
with enhanced device performance. STS-IMOS has silicide (NiSi) source to lower the breakdown
voltage of conventional impact ionization MOS (IMOS). There is cumulative effect of both impact
ionization and source induced tunneling for the current gating mechanism of the device. The silicide source
offers immensely low parasitic resistance subsequently there is an increment in voltage drop across
intrinsic region. This leads to appreciable lowering of breakdown and threshold voltage for STS-IMOS.
Hence, it demonstrates enhanced device performance over conventional IMOS. Besides this for STS-IMOS
the location of maximum electric field has shifted towards the source and now it is quite away from gateoxide. Hence, it shows high immunity against Vth fluctuations due to hot electron damage. Consequently, itis found that device reliability is also improved significantly.
In this paper, a novel architecture of RNS based 1D Lifting Integer Wavelet Transform (IWT) has been introduced. Advantage of Residue Number System (RNS) based Lifting Scheme over RNS based Filter Bank and non-binary IWT has been discussed. The performance of traditional predicts and updates stage of binary Lifting Scheme (LS) for Discrete Wavelet Transform (DWT) generates huge carry propagation
delay, power and complexity. As a result non binary number system is becoming popular in the field of Digital Signal Processing (DSP) due to its efficient performance. In this paper also a new fixed number ROM based RNS division circuit has been proposed. The proposed architecture has been validated on Xilinx Vertex5 FPGA platform and the corresponding result and reports are shown in here.
A new efficient fpga design of residue to-binary converterVLSICS Design
In this paper, we introduce a new 6n bit Dynamic Range Moduli set { 22n, 22n + 1, 22n – 1} and then present
its associated novel reverse converters. First, we simplify the Chinese Remainder Theorem in order to
obtain an efficient reverse converter which is completely memory less and adder based. Next, we present a
low complexity implementation that does not require the explicit use of modulo operation in the conversion
process and we demonstrate that theoretically speaking it outperforms state of the art equivalent reverse
converters. We also implemented the proposed converter and the best equivalent state of the art reverse
converters on Xilinx Spartan 6 FPGA. The experimental results confirmed the theoretical evaluation. The
FPGA synthesis results indicate that, on the average, our proposal is about 52.35% and 43.94% better in
terms of conversion time and hardware resources respectively.
LOW POWER, LOW NOISE AMPLIFIERS DESIGN AND ANALYSIS FOR RF RECEIVER FRONT END...VLSICS Design
This work is mainly to ensure the reliability of low power low noise amplifier design and analysis which is
useful for 4G receiver front ends in particularly WIMAX applications. The low noise amplifiers
implemented by using different topologies namely (a) Cascoded Common source amplifier technique(b)
Folded Cascode amplifier technique (c) Shunt feedback amplifier technique (d) Current reuse Common
gate amplifier with gm boosted technique with 90 nm TSMC CMOS technology, which is used for WIMAX
applications with 1V supply. In order to simulate and measurement the parameters such as Scattering
parameters(S21, S12 S11. S22 ),noise-figure, input matching, output matching ,stability, linearity the
Cadence ,Agilent technologies ADS and lab view graphical software have been used and Compare the
performance of the various parameters .
Transistor level implementation of digital reversible circuitsVLSICS Design
Now a days each and every electronic gadget is designing smartly and provides number of applications, so
these designs dissipate high amount of power. Reversible logic is becoming one of the best emerging design
technologies having its applications in low power CMOS, Quantum computing and Nanotechnology.
Reversible logic plays an important role in the design of energy efficient circuits. Adders and subtractors
are the essential blocks of the computing systems. In this paper, reversible gates and circuits are designed
and implemented in CMOS and pass transistor logic using Mentor graphics backend tools. A four-bit ripple
carry adder/subtractor and an eight-bit reversible Carry Skip Adder are implemented and compared with
the conventional circuits.
EVALUATION OF ATM FUNCTIONING USING VHDL AND FPGA VLSICS Design
It has been almost four decades that banks and other financial organizations have been gradually computerised, in order to improve service and efficiency and to reduce cost. The birth of Electronic Fund Transfer and Automated Teller Machines has given rise to 24-hour banking and a greater variety of services for the customer. This method uses a computer to transfer debits and credits, with the help of electronic pulses, which are carried through wires either to a magnetic disk or tape. ATM (Automated
Teller Machine) has become an important part in our daily lives. People use ATM for various purposes such as money withdrawal, checking balance, changing password etc. Since it mainly deals with people's
money, it has to be a secure system on which we can rely. We have taken a step towards increasing this
security and integrity by trying to implement the functioning of an ATM using VLSI-based programming, HDL(Hardware Description Language).The conventional coding languages such as C,C++ are replaced by VHDL(Very High Speed Integrated Circuit Hardware Description Language) so that the code cannot be easily hacked or changed. This article consists of an insight into the various functions that can be
performed using an ATM, a brief description of the Coding and the obtained simulation results. It alsoconsists of the implementation of the code using FPGA Kit (Spartan3; Model no.-XC 3S50).
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Minimization of Overall Losses of a Distribution System under Contingency Con...paperpublications3
Abstract: In this paper, a methodology has been proposed to minimize the losses of distribution systems (technical and non-technical losses) that is an absolutely necessary objective in the sound management of any electrical utility. The transmission & distribution losses in Indian power system are high. Most of the efforts of power planners concentrate on augmenting supply by building new power plants. But saving is possible by improving operating conditions for the distribution network. Due to inadequate planning and methods adopted for load shifting, some networks are under loaded while others are overloaded. Thus there is some scope for improvement in operating strategies. Network reconfiguration in distribution system is realized by changing the status of the sectionalizing switches and is usually done for loss reduction and avoids overloading. In primary distribution system (11KV), the need for reconfiguration occurs in emergency condition following the fault to isolate faulted section and in normal condition to reduce system losses or to avoid overloading of network. The main objective of the paper is to outline a methodology for management of distribution system for loss reduction by network reconfiguration. The possible techniques used for power loss reduction, which are network reconfiguration and capacitor addition. Case studies were simulated on an interconnected ring main distribution network.
Minimization of Overall Losses of a Distribution System under Contingency Con...paperpublications3
Abstract: In this paper, a methodology has been proposed to minimize the losses of distribution systems (technical and non-technical losses) that is an absolutely necessary objective in the sound management of any electrical utility. The transmission & distribution losses in Indian power system are high. Most of the efforts of power planners concentrate on augmenting supply by building new power plants. But saving is possible by improving operating conditions for the distribution network. Due to inadequate planning and methods adopted for load shifting, some networks are under loaded while others are overloaded. Thus there is some scope for improvement in operating strategies. Network reconfiguration in distribution system is realized by changing the status of the sectionalizing switches and is usually done for loss reduction and avoids overloading. In primary distribution system (11KV), the need for reconfiguration occurs in emergency condition following the fault to isolate faulted section and in normal condition to reduce system losses or to avoid overloading of network. The main objective of the paper is to outline a methodology for management of distribution system for loss reduction by network reconfiguration. The possible techniques used for power loss reduction, which are network reconfiguration and capacitor addition. Case studies were simulated on an interconnected ring main distribution network.
Study and Review on Various Current Comparatorsijsrd.com
This paper presents study and review on various current comparators. It also describes low voltage current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit has short propagation delay and occupies a small chip area as compare to other current comparators. The results of this circuit has obtained using PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Sources of Power Dissipation
Dynamic Power Dissipation
Static Power Dissipation
Power Reduction Techniques
Algorithmic Power Minimization
Architectural Power Minimization
Logic and Circuit Level Power Minimization
Control Logic Power Minimization
System Level Power Management.
In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.
In our project, we propose a novel architecture which generates the test patterns with reduced switching activities. LP-TPG (Test pattern Generator) structure consists of modified low power linear feedback shift register (LP-LFSR), m-bit counter; gray counter, NOR-gate structure and XOR-array. The m-bit counter is initialized with Zeros and which generates 2m test patterns in sequence. The m-bit counter and gray code generator are controlled by common clock signal [CLK]. The output of m-bit counter is applied as input to gray code generator and NOR-gate structure. When all the bits of counter output are Zero, the NOR-gate output is one. Only when the NOR-gate output is one, the clock signal is applied to activate the LP-LFSR which generates the next seed. The seed generated from LP-LFSR is Exclusive–OR ed with the data generated from gray code generator. The patterns generated from the Exclusive–OR array are the final output patterns. The proposed architecture is simulated using Modelsim and synthesized using Xilinx ISE 13.2 and it will be implemented on XC3S500e Spartan 3E FPGA board for hardware implementation and testing. The Xilinx Chip scope tool will be used to test the FPGA inside results while the logic running on FPGA.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
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Static power optimization using dual sub threshold supply voltages in digital cmos vlsi circuits
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
STATIC POWER OPTIMIZATION USING DUAL
SUB-THRESHOLD SUPPLY VOLTAGES IN
DIGITAL CMOS VLSI CIRCUITS
Mrs. K. Srilakshmi1, Mrs. Y. Syamala2 and A. Suvir Vikram3
1
Department of Electronics and Communication Engineering, Gudlavalleru Engineering
College, Gudlavalleru, A.P. India
2
Department of Electronics and Communication Engineering, Gudlavalleru Engineering
College, Gudlavalleru, A.P. India
3
Department of Electronics and Communication Engineering, Gudlavalleru Engineering
College, Gudlavalleru, A.P. India
Abstract
Power dissipation in high performance systems requires more expensive packaging. In this situation, low
power VLSI design has assumed great importance as an active and rapidly developing field. As the density
and operating speed of CMOS VLSI chip increases, static power dissipation becomes more significant. This
is due to the leakage current when the transistor is off this is threshold voltage dependent. This can be
observed in the combinational and sequential circuits. Static power reduction techniques are achieved by
means of operating the transistor either in Cut-off or in Saturation region completely and avoiding the
clock in unnecessary circuits. In this work, “Dual sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in on state by applying some voltage at the gate of the MOS
transistor. This static power reduction technique is to digital circuits, so that the power dissipation is
reduced and the performance of the circuit is increased. The designed circuits can be simulated by using
Mentor Graphics Backend Tool.
Keywords
Dual sub-threshold, reliability, power dissipation, leakage current.
1. INTRODUCTION
Low power design is the upcoming design technology due to its high performance batteryportable digital systems. Presently there are many portable devices that run on batteries, laptop,
tablet PC, mobile phone, ipod, etc. The power dissipation in these devices is high. This is due to
the supply of high voltage to the low power components in the device. If the supply power is low
then the circuits operating with that power should be capable of holding the loads. For example,
if an amplifier circuit is working with low input power then the output should be capable of
driving a loud speaker. The circuits which requires low power is better to use battery, so that the
device will be portable. If the power is reduced then the circuits that require low power to be used
and thus the number of circuit’s increases but the power supply remains the same. As the circuits
are operated in parallel the output of one circuit will depend on other circuit or may be
DOI : 10.5121/vlsic.2013.4506
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2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
independent and the usage of clock circuit is mandatory. Therefore the complexity of circuits
increases and the power (energy) supply remains same.
If the speed is increased then the circuits must be operated with high frequency clock pulse, at the
same time, if some circuits needs low frequency thus there is a need of a frequency divider and
some extra hardware is required to connect the circuits. Thus, the complexity is increased for the
high speed devices. Thermal problems arise due to more hardware in a dense packing. For this
there is a need for the cooling process. So, there is a need for heat sinks and cooling fans for heat
exhaust. By the use of low power circuits, there is no need of heavy weighted devices like
transformers. Due to these considerations the weight, size and cost are reduced. The dual subthreshold supply voltage technique would help to operate where complex devices need to
consume less power. Thereby, the complex circuits will dissipate less amount of power.
At the same time, due to the use of battery power there is no fluctuations in the supply power and
the noise produced by the circuits is very low. The need for low power is to reduce the power
dissipation, to increase the battery life time, reducing heat sinks, cooling fans and finally the cost
of the device also reduces. In this work, the circuits are designed and simulated in mentor
graphics back-end tool through Linux operating system. This provides the better way to design
the circuits from physical design and the circuits can be simulated easily as in the real time. The
remaining sections of the paper as follows: section 2 is about different low power design
techniques, design principles, power dissipation are given in section 3 and 4, implementation of
the circuits are given in section 5 and finally results and conclusion are discussed.
2. DIFFERENT LOW POWER DESIGN TECHNIQUES
There are certain low power techniques that provide low power dissipation by using the low
power design techniques. Techniques used in low power design includes
2.1 Clock gating technique
In this technique, the circuit consumes more power when the clock is on and the clock pulse must
be provided to every circuit which leads to complexity. The clock signal generator also consumes
power every time when the supply is on. The disadvantage of this technique is increase of leakage
power [1] [2] in the circuit when there is no input.
2.2 Multi-threshold CMOS (MTCMOS)
In multi threshold technique [3] different supply voltages are given to different circuit
components depending on the circuit path length. If the path length is long then high threshold
supply voltage must be given, if not low threshold supply voltage must be given so that low
voltage drop takes place. In this technique, the disadvantage is different threshold supply voltages
are provided in the circuit, this leads to the degradation of the compatibility.
2.3 Stacked Transistors
In this technique, more number of transistors can be incorporated on a single wafer. So the
transistor stacking will allow them to increase circuit density. They appear to be building silicon
wafers and stacking them together. Advantage of this technique is reducing IC size. Low power is
sufficient to drive an IC due to reduced wire length and power dissipation can also be reduced.
The disadvantage of the circuit is operated at high voltage, but the power dissipation due to
resistance is reduced due to reduced wire length.
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3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
2.4 Dynamic Threshold MOS (DTMOS)
In this technique, the threshold supply voltage can be varied between some fixed range of voltage.
As the circuit will be designed with a predefined technology and once if the IC is manufactured it
cannot be modified internally for a designed technology. The disadvantage of this technique is
that the components do not have certain limit of threshold supply voltage.
2.5 Dynamic/voltage/frequency scaling [4-7]
In this technique, the supply voltage can be reduced without change in the technology of the
circuit that is designed and the frequency of the input can be scaled down these are dynamic
changes done externally. The disadvantage in this technique is the supply voltage is technology
dependent, if high voltage is given to the components then the component is damaged.
2.6 Near sub-threshold supply [4-7]
In this technique, the supply voltage is scaled down such that the devices are also scaled down. So
the devices can be operated at sub-threshold voltage. The disadvantage in this technique is when
the component is used just above the threshold voltage then there can be an electron migration in
the transistors used in the circuit.
3. DESIGN PRINCIPLES
Transistors are designed in such a way that the width of the gate should be more when compared
with the length of the channel this is made such that the for applied gate voltage the channel must
be formed for logic high in NMOS and logic low in PMOS transistors. If the insulator used at the
gate of the MOS transistor is of very less width than the channel length, hence if the transistor is
off even though certain current flows due to charge induced due to capacitance effect. To reduce
the leakage current the length and width of MOS transistor is made suitably for low voltage
applications that to near sub-threshold voltages.
In this paper, by using multi threshold supply voltages that are provided with near sub-threshold
voltage and the voltage can also be varied around below sub-threshold and near sub-threshold
voltages. Transistors are designed to operate at weak inversion, so that sub threshold supply
voltage is sufficient to operate these transistors with negligible leakage current. Static power
consumed by these transistors is very less. The dynamic power consumed by the transistors
depends on the switching frequency of the signal that is applied at the gate of the transistor, full
supply voltage and the load capacitance used.
Supply voltage scaling was developed for switching power reduction. It is an efficient method for
reducing switching power. It also helps to reduce leakage power because the sub-threshold
leakage is due to Gate Induced Drain Leakage (GIDL) and Drain Induced Barrier Leakage
(DIBL), these are also reduced as well as the gate leakage component when the supply voltage is
scaled down. Static supply voltage scaling is a multiple supply voltage where as different supply
voltages are provided. The speed of the non-critical paths are not deterministic where as the speed
of the critical paths are lowered when compared with the non-critical paths. In order to satisfy the
speed performance the critical and non-critical paths are made to operate with same speed without
disturbing the system performance. By using multiple supply voltage technique the interconnect
delays are made negligible depending upon the lengths of the interconnects.
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4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
4. POWER DISSIPATION
Static power is reduced by reducing the length of the channel and width of the gate of transistors
[3], this is the easy way to reduce the static power consumption of a transistor without disturbing
its operation. The low voltage operation is that the conduction is due to diffusion of charge
carriers. Transistors connected to low threshold supply voltage conduct as the channel will be
formed for very low voltage. So that, even for a high threshold supply voltage the power
dissipation by the transistors is less. The near sub-threshold supply voltage is sufficient for the
transistors to conduct. Static power essentially consists of the power used when the transistor is
not in the process of switching.
Pstatic = Istatic*Vdd
(1)
The near threshold supply voltage is also provided in order to make the transistors to conduct if
there are equal paths that there are no critical and non-critical paths. Hence all the transistors need
equal voltages. Thereby, the static power dissipation is reduced. Dynamic power is the sum of
transient power consumption (Ptransient) and capacitive load power (Pcap) consumption. Ptransient
represents the amount of power consumed when the device changes logic states. Capacitive load
power consumption is the power used to charge the load capacitance.
Pdynamic = Pcap + Ptransient = (CL + C) *Vdd2 *f*N3
(2)
Where ‘N’ is the number of logic values that are switching, ‘f’ is the switching frequency. The
short circuit power depends upon the frequency of the transition. Hence the total power dissipated
is the sum of all the power dissipations in the circuit.
Ptotal =Pststic+Psc+Pdynamic
(3)
The power dissipation can also be further reduced by placing a transmission gate between the
circuit and the power supply. The inputs are connected to the transmission gate also. Depending
upon the inputs the transmission gate conducts that means there is some input to the circuit. When
there is no input the transmission gate will be in off state. If the transistors are not designed as per
our requirement the leakage power dissipation will be high as the leakage power is inversely
proportional to the threshold voltage. A way to reduce leakage power consumption is to raise the
Vth of some gates. A higher Vth reduces the sub-threshold leakage. Hence, the transistors are
designed in order to reduce the power dissipation to maximum level. The use of two power
supplies makes some devices to allow the leakage current hence by providing a third power
supply that is greater than the threshold supply voltage. The delay increases as the supply voltage
is scaled down. This technique can be applied to any circuit either combinational or sequential
circuit.
5. IMPLEMENTATION
Any CMOS circuits can be designed by implementing the dual sub-threshold supply voltages
along with Vdd. The designed combinational circuits are decoder, 4x1 multiplexer and sequential
circuits are Moore and Mealey machine, ring counter. The logic gates are designed with CMOS
transistors, the gates are designed as shown below. The inverter with VDD as supply voltage is
given in Figure 1.
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5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 1. Inverter with VDD as supply voltage
In this circuit the input is applied to both transistors depending on the applied input logic the
transistors conduct and the output is obtained. The inverter circuit uses very less number of
transistors connected through the supply voltage to the ground. Hence very low voltage is
sufficient to operate the inverter with very less power dissipation. The power dissipation for
different supply voltages is tabulated.
Figure 2. NAND gate with VDD as supply voltage
The NAND gate with VDD as supply voltage is given in Figure 2. The circuit inputs are i1 and i2,
depending on the input voltage applied transistors conduct and the output at O is obtained. The
designed NAND gate uses supply voltage either VDD or Low Vth or High Vth. Depending upon
the voltage applied the NAND gate is operated with low leakage current and very low power
dissipation.
Figure 3. 4-input OR gate with VDD as supply voltage
Figure 3 gives the functionality of 4-input OR gate with VDD as supply voltage. In this circuit,
the inputs are i1, i2, i3, i4 and the output is O. The input is applied to the transistors as the input
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6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
voltage is very low the transistors conduct. Depending upon the number of transistors used in the
circuit the supply voltage is also varied, if there are a number of transistors connected in series the
supply voltage is to be increased in order to obtain the required output for the given input.
Figure 4. 2-input AND gate with Vdd as supply voltage.
The 2-input AND gate with VDD as supply voltage is given in Figure 4. In this circuit the inputs
are in1 and in2. The output is O. Depending upon the applied logic the transistors conduct and the
output is obtained. The AND gate designed with an inverter and the NAND gate, hence inverter
requires very low power supply, NAND gate uses some high voltage than the inverter. Hence
High Vth supply voltage is sufficient to drive the AND gate.
Figure 5. D-Flip Flop
The D-Flip flop is given in Figure 5. In this circuit, the inputs are Data in and Clk. The outputs
are Q and Qbar. The NOT gate applied between the two NAND gates to provide the inverted
operation for the given input so that output at Qbar is obtained. For the given input the required
output at Q is obtained. The D-Flip flop requires (high threshold supply voltage) High Vth supply
voltage, hence in order to dissipate low power the transistors are designed with required
parameters such as channel length and gate width of the transistor. Further, the designed circuits
are discussed below. The 4x1 Multiplexer with dual sub-threshold supply voltage is given in
Figure 6.
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7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 6. 4x1 Multiplexer with dual sub-threshold supply voltage
The simulation waveform of 4x1 Multiplexer with dual sub-threshold supply voltage is given in
Figure 7. In this waveform, the inputs are i1, i2, i3, i4, s0 and s1 and output is Out. In this s0, s1
are selection lines. Depending on the inputs applied to the AND gates, by means of selection lines
the outputs from each gate is connected to the OR gate and the output Out is obtained. In the
above designed circuit the NOT gate can also be provided with low threshold supply voltage as
the voltage drop in the NOT gate is very low, the AND gat uses more number of transistors so
high Vth supply voltage can be provided and the OR gate that drives all the outputs from the
AND gates require Vdd as power supply and also there are more number of transistors required
for4-input OR gate.
Figure 7. Simulation waveform of 4x1 Multiplexer with dual sub-threshold supply voltage
The Differential cascode voltage switched (DCVS) level converter for NOT gate is shown in
Figure 8 and its simulation waveform is given in Figure 9. In this circuit, the input is IN, output is
OUT The DCVS circuit designed with NOT gates and few transistors so low threshold supply
voltage is provided to the inner NOT gate and high threshold supply voltage is provided to the
overall circuit and the output driven NOT gate.
Figure 8. Differential cascode voltage switched (DCVS) level converter for NOT gate
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8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 9. Simulation waveform of DCVS level converter for NOT gate
The 2 × 4 Decoder with dual sub-threshold supply voltage and its simulation waveforms are given
in Figures 10 and 11 respectively.
Figure 10. 2 × 4 Decoder with dual sub-threshold supply voltage
Figure 11. Simulation waveform of 2 × 4 Decoder with dual sub-threshold supply voltage
Later, the same technique was applied for sequential circuits and its functionality was verified.
The Mealey and Moore machine with dual sub-threshold supply voltage are shown in Figures
12 and 13. The simulation waveforms of the designed circuits are given in Figure 14 and 15
respectively. In this circuit, inputs are A, D1 and Clk. Outputs are D2 and Z. Depending on the
inputs applied to the AND gate the D-flip flop output is obtained, this is connected to the NOR
gate the output Z is obtained. Similarly the output is at D2. The mealey machine is designed
with D-Flip flops, AND, OR, NOR gates depending upon the path lengths connected in the
circuit the supply voltage to the different blocks in the circuit is also varied. In this inputs are
Vin and Clk. Output is Y. Depending on the inputs applied to the D-flip flops through the logic
gates output is obtained, this is connected to the OR gate and the output Y is obtained.
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9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 12. Mealey Machine with dual sub-threshold supply voltage
Figure 13. Moore Machine with dual sub-threshold supply voltage
The Moore machine is designed with D-flip flop, OR, AND gates depending upon the path
lengths the power is supplied in order not to waste the supply power in the form of power
dissipated as heat. Longest paths require high threshold supply, shortest paths require low
threshold supply voltage, and circuit blocks with more number of transistors require Vdd as
supply voltage that is greater than the high threshold supply voltage.
Figure 14. Simulation waveform of Mealey Machine with dual sub-threshold supply voltage
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10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 15. Simulation waveform of Moore Machine with dual sub-threshold supply voltage
The ring counter with dual sub-threshold supply voltage is given in Figure 16. In this inputs are
reset and Clk. Outputs are R0, R1, R2, R3 and R4. Depending on the inputs applied to the D-flip
flops output R1, R2, R3, R4 are obtained this is due to the delay by each flip-flop, this is
connected to the NOR gate and the output R0 is obtained. The output can be clearly obtained for
clock pulse with less with. Ring counter uses only two power supplies that are high threshold
supply voltage and Vdd supply, for 4-input NOR gate as there are more number of transistors
required hence Vdd supply is provided. D-flip flop uses few gates than the NOR gate in this
circuit so high threshold supply voltage is provided. This dual supply voltage also provides an
advantage depending upon the path length in the circuit.
Figure 16. Ring Counter with dual sub-threshold supply voltage
Some circuit designs allow only low threshold, some other high threshold, some circuits uses both
low and high threshold supply voltages. Power consumption is different in different circuits, as it
depends upon the supply voltage, load applied, type of components used to design the circuit, the
technique and technology used to design the circuit. The 1.25µm technology is used to implement
these designed circuits. The power dissipation of circuits with sub-threshold supply voltages
along with Vdd is given in Table 1. The results of power dissipation of circuits with dual subthreshold supply voltages are given in Table 2.
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11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Table 1. Power dissipation of circuits with sub-threshold supply voltages along with Vdd
Supply voltages(volts)
Designed circuit
Power
dissipation
(watts)
Vdd
Vddhigh
Vddlow
DCVS for NOT gate
0.7
0.35
0.15
2.279µ
Nand
Inverter
2 to 4 Decoder
--------0.7
------------0.35
0.15
0.15
0.15
39.9354n
25.9438f
1.7851µ
Moore
Ring counter
Up-down counter
0.7
1.5
0.7
0.25
----0.25
0.15
0.15
0.15v
18.6552µ
690.1097n
4.6425µ
Table 2. Power dissipation of circuits with dual sub-threshold supply voltages
Designed circuit
DCVS for NOT gate
Inverter
Nand
2 to 4Decoder
Up-down counter
Supply voltages(volts)
Vddlow Vddhigh
0.24
0.24
0.24
0.24
0.24
Power dissipation
(watts)
0.15
0.15
0.15
0.15
0.15
6.385 µ
34.680n
244.0433n
5.417 µ
35.9634u
6. POWER DISSIPATION COMPARISON
The power dissipation by using the dual sub-threshold supply voltage is more this is because of
the more leakage power and the output results are not accurate, when compared with the power
dissipation using the dual sub-threshold supply voltage along with Vdd and the output is accurate.
The Table 3 describes the percentage of power dissipation between dual sub-threshold supply
voltage along with Vdd and dual sub-threshold supply voltage.
Table 3. Percentage reduction of power dissipation for dual sub-threshold supply voltage with and without
supply voltage
S.No.
Designed circuits
Power dissipation (watts)
without VDD
Power reduction
(%)
withVDD
1
2.
3.
DCVS
Decoder
Nand
6.385µ
5.417 µ
244.0433n
2.279 µ
1.7851 µ
39.9354n
73.69
75.21
85.93
4.
Up-Down counter
35.9634 µ
4.6425 µ
88.56
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12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
7. CONCLUSION
The power dissipation by using dual sub-threshold supply voltage along with VDD is less when
compared to the dual sub-threshold supply voltage without VDD. The power dissipation increases
while increasing the VDD supply voltage. The leakage power dissipation is high for very low
supply voltages due to the leakage current through the ground. This technique can be applied for
any CMOS digital circuits depending on number of components used. High supply voltages can
not be applied for these designed circuits. Hence this technique provides a better solution for the
low power devices.
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Authors
Srilakshmi born at Karnataka. She completed her B.Tech degree from
JNTUK,
Kakinada, India in 2009, and M.Tech in 2011 from the JNTUK University in VLSI
System Design as specialization. She is currently working as a assistant professor in
Department of ECE in Gudlavalleru Engineering college, India. Her research interest
includes Low power design, VLSI design, and embedded design. She has been
published several papers in different various conferences.
Syamala born on Sept 14th 1980 in kavali, India. Obtained B.E degree from Bharatiyar
University, India in 2001. M.E degree in applied electronics from Anna University in
2005. In 2005, she joined as an assistant professor in Gudlavalleru Engineering College.
In 2011, she promoted as an Associate Professor in department of ECE, GEC, India.
She has been a member of IEEE, FIETE, ISTE, and MISTE. She has published several
papers in the area of VLSI. Her research interest includes VLSI design, digital design
and testing.
Suvir Vikram.A born in Vuyyuru, India. He has obtained his Bachelor degree in
Electronics and Communication from Newtons Institute of Engineering, Macherla in
2011. Presently he is pursuing his Masters degree in Embedded Systems of Electronics
and Communication in Gudlavalleru Engineering College, Gudlavalleru from 2011 to
2013 .He is interested in Low power VLSI design. He is currently working on a project
titled “Static Power Optmization using dual sub-threshold supply voltage in Digital
CMOS VLSI Circuits”as a partial fulfilment of his M.Tech degree.
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