This paper proposes a validation method for the des
ign of a CPU on which, in parallel with the
development of the CPU, it is also manually describ
ed a testbench that performs automated testing on t
he
instructions that are being described. The testbenc
h consists of the original program memory of the CP
U
and it is also coupled to the internal registers, P
ORTS, stack and other components related to the pro
ject.
The program memory sends the instructions requested
by the processor and checks the results of its
instructions, progressing or not with the tests. Th
e proposed method resulted in a CPU compatible with
the
instruction set and the CPU registers present into
the PIC16F628 microcontroller. In order to shows th
e
usability and success of the depuration method empl
oyed, this work shows that the CPU developed is
capable of running real programs generated by compi
lers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthe
sized on silicon.
Microcontroller Based Testing of Digital IP-CoreVLSICS Design
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.
Agilent flash programming agilent utility card versus deep serial memory-ca...AgilentT&M EMEA
This case study compares the flash programming performances of the Agilent Medalist i3070 Series (http://bit.ly/16hd1as) 5 in-circuit tester (ICT) with utility card flash programming solution against the Teradyne in-circuit tester with deep serial memory programming solution
This tutorial is intended for verification engineers that must validate algorithmic designs. It presents the detailed steps for implementing a SystemVerilog verification environment that interfaces with a GNU Octave mathematical model. It describes the SystemVerilog – C++ communication layer with its challenges, like proper creation and activation or piped algorithm synchronization handling. The implementation is illustrated for Ncsim, VCS and Questa.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
Microcontroller Based Testing of Digital IP-CoreVLSICS Design
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.
Agilent flash programming agilent utility card versus deep serial memory-ca...AgilentT&M EMEA
This case study compares the flash programming performances of the Agilent Medalist i3070 Series (http://bit.ly/16hd1as) 5 in-circuit tester (ICT) with utility card flash programming solution against the Teradyne in-circuit tester with deep serial memory programming solution
This tutorial is intended for verification engineers that must validate algorithmic designs. It presents the detailed steps for implementing a SystemVerilog verification environment that interfaces with a GNU Octave mathematical model. It describes the SystemVerilog – C++ communication layer with its challenges, like proper creation and activation or piped algorithm synchronization handling. The implementation is illustrated for Ncsim, VCS and Questa.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
Abstract
Now a day’s many VLSI designers are implementing different applications on real time with the use of FPGAs. Although they are
working efficiently, they are not achieving their expected goals. This is only because of the faults which are occurring in the
FPGA at the runtime of the application. Those faults are remaining in the circuitry as there is no provision for removal of those
faults at application level. So there is a great need of detection & removal of faults. Mainly Interconnect faults, Logical Faults
and Delay are the faults which reduces the performance of FPGA. Although the manufacturers are trying to decrease the fault
present in the FPGA, it is very necessary to remove those faults at run time of the particular application. This paper includes the
brief discussion about the occurrence of different faults and various methods to remove those faults.
Key Words: Fault diagnosis, field-programmable gate array (FPGA), testing.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Slides fra InfInIT arrangement i interessegruppen for Embedded Systems Engineering
http://www.infinit.dk/dk/arrangementer/tidligere_arrangementer/sweet---a-tool-for-wcet-flow-analysis.htm
High Speed Fault Injection Tool (FITO) Implemented With VHDL on FPGA For Test...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
The development of embedded applications (such as Wireless Sensor Network protocols) often
requires a shift to formal specifications. To insure the reliability and the performance of the
WSNs, such protocols must be designed following some methods reducing error rate. Formal
methods (as Automata, Petri nets, algebra, logics, etc.) were largely used in the specification of
these protocols, their analysis and their verification. After that, their implementation is an
important phase to deploy, test and use those protocols in real environments. The main
objective of the current paper is to formalize the transformation from high-level specification (in
Timed Automata) to low-level implementation (in NesC language and TinyOs system) and to
automate such transformation. The proposed transformation approach defines a set of rules that
allow the passage between these two levels. We implemented our solution and we illustrated the
proposed approach on a protocol case study for the "humidity" and "temperature" sensing in
WSNs applications.
LOW POWER, LOW NOISE AMPLIFIERS DESIGN AND ANALYSIS FOR RF RECEIVER FRONT END...VLSICS Design
This work is mainly to ensure the reliability of low power low noise amplifier design and analysis which is
useful for 4G receiver front ends in particularly WIMAX applications. The low noise amplifiers
implemented by using different topologies namely (a) Cascoded Common source amplifier technique(b)
Folded Cascode amplifier technique (c) Shunt feedback amplifier technique (d) Current reuse Common
gate amplifier with gm boosted technique with 90 nm TSMC CMOS technology, which is used for WIMAX
applications with 1V supply. In order to simulate and measurement the parameters such as Scattering
parameters(S21, S12 S11. S22 ),noise-figure, input matching, output matching ,stability, linearity the
Cadence ,Agilent technologies ADS and lab view graphical software have been used and Compare the
performance of the various parameters .
Transistor level implementation of digital reversible circuitsVLSICS Design
Now a days each and every electronic gadget is designing smartly and provides number of applications, so
these designs dissipate high amount of power. Reversible logic is becoming one of the best emerging design
technologies having its applications in low power CMOS, Quantum computing and Nanotechnology.
Reversible logic plays an important role in the design of energy efficient circuits. Adders and subtractors
are the essential blocks of the computing systems. In this paper, reversible gates and circuits are designed
and implemented in CMOS and pass transistor logic using Mentor graphics backend tools. A four-bit ripple
carry adder/subtractor and an eight-bit reversible Carry Skip Adder are implemented and compared with
the conventional circuits.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
Abstract
Now a day’s many VLSI designers are implementing different applications on real time with the use of FPGAs. Although they are
working efficiently, they are not achieving their expected goals. This is only because of the faults which are occurring in the
FPGA at the runtime of the application. Those faults are remaining in the circuitry as there is no provision for removal of those
faults at application level. So there is a great need of detection & removal of faults. Mainly Interconnect faults, Logical Faults
and Delay are the faults which reduces the performance of FPGA. Although the manufacturers are trying to decrease the fault
present in the FPGA, it is very necessary to remove those faults at run time of the particular application. This paper includes the
brief discussion about the occurrence of different faults and various methods to remove those faults.
Key Words: Fault diagnosis, field-programmable gate array (FPGA), testing.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Slides fra InfInIT arrangement i interessegruppen for Embedded Systems Engineering
http://www.infinit.dk/dk/arrangementer/tidligere_arrangementer/sweet---a-tool-for-wcet-flow-analysis.htm
High Speed Fault Injection Tool (FITO) Implemented With VHDL on FPGA For Test...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
The development of embedded applications (such as Wireless Sensor Network protocols) often
requires a shift to formal specifications. To insure the reliability and the performance of the
WSNs, such protocols must be designed following some methods reducing error rate. Formal
methods (as Automata, Petri nets, algebra, logics, etc.) were largely used in the specification of
these protocols, their analysis and their verification. After that, their implementation is an
important phase to deploy, test and use those protocols in real environments. The main
objective of the current paper is to formalize the transformation from high-level specification (in
Timed Automata) to low-level implementation (in NesC language and TinyOs system) and to
automate such transformation. The proposed transformation approach defines a set of rules that
allow the passage between these two levels. We implemented our solution and we illustrated the
proposed approach on a protocol case study for the "humidity" and "temperature" sensing in
WSNs applications.
LOW POWER, LOW NOISE AMPLIFIERS DESIGN AND ANALYSIS FOR RF RECEIVER FRONT END...VLSICS Design
This work is mainly to ensure the reliability of low power low noise amplifier design and analysis which is
useful for 4G receiver front ends in particularly WIMAX applications. The low noise amplifiers
implemented by using different topologies namely (a) Cascoded Common source amplifier technique(b)
Folded Cascode amplifier technique (c) Shunt feedback amplifier technique (d) Current reuse Common
gate amplifier with gm boosted technique with 90 nm TSMC CMOS technology, which is used for WIMAX
applications with 1V supply. In order to simulate and measurement the parameters such as Scattering
parameters(S21, S12 S11. S22 ),noise-figure, input matching, output matching ,stability, linearity the
Cadence ,Agilent technologies ADS and lab view graphical software have been used and Compare the
performance of the various parameters .
Transistor level implementation of digital reversible circuitsVLSICS Design
Now a days each and every electronic gadget is designing smartly and provides number of applications, so
these designs dissipate high amount of power. Reversible logic is becoming one of the best emerging design
technologies having its applications in low power CMOS, Quantum computing and Nanotechnology.
Reversible logic plays an important role in the design of energy efficient circuits. Adders and subtractors
are the essential blocks of the computing systems. In this paper, reversible gates and circuits are designed
and implemented in CMOS and pass transistor logic using Mentor graphics backend tools. A four-bit ripple
carry adder/subtractor and an eight-bit reversible Carry Skip Adder are implemented and compared with
the conventional circuits.
DESIGN AND IMPLEMENTATION OF 10 BIT, 2MS/s SPLIT SAR ADC USING 0.18um CMOS TE...VLSICS Design
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is
designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample
and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter(DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimizedarchitecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy ofthe components, which improves the performance of SAR ADC. Comparator constructed from resistances,capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC
using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using
Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
IMPLEMENTATION OF SDC - SDF ARCHITECTURE FOR RADIX-4 FFT VLSICS Design
Very large scale integration and Digital signal processing are the very crucial technologies from the last
few decades. DSP applications require high performance, low area and low power VLSI circuits. This
paper is discussing about FFT which is one of the vital component in the digital signal processing. In this
Paper, we propose a single path delay commutator–feedback (SDC-SDF) Architecture for Radix-4 FFT
and presented its simulation and synthesis results. The Radix-4 FFT architecture consists of log4 N-1 SDC
Stages and 1 SDF stage. Previously, the radix-2 SDC-SDF (Single path delay commutator-feedback) FFT
architecture was includes log2 N-1 SDC Stages and 1 SDF stage. The proposed Radix-4 SDC-SDF
architecture reduces the number of multiplications and additions as well as number of stages which
achieves reduced area and low power. The resultant architecture is simulated using Modelsim, design
verification and synthesis results are done using Xilinx ISE. The proposed architecture is compared with
Radix-2 SDC-SDF FFT and it can achieve less area as well as low power
In this paper, a novel architecture of RNS based 1D Lifting Integer Wavelet Transform (IWT) has been introduced. Advantage of Residue Number System (RNS) based Lifting Scheme over RNS based Filter Bank and non-binary IWT has been discussed. The performance of traditional predicts and updates stage of binary Lifting Scheme (LS) for Discrete Wavelet Transform (DWT) generates huge carry propagation
delay, power and complexity. As a result non binary number system is becoming popular in the field of Digital Signal Processing (DSP) due to its efficient performance. In this paper also a new fixed number ROM based RNS division circuit has been proposed. The proposed architecture has been validated on Xilinx Vertex5 FPGA platform and the corresponding result and reports are shown in here.
A new design for fault tolerant and fault recoverable ALU System has been proposed in this paper. Reliability is one of the most critical factors that have to be considered during the designing phase of any IC. In critical applications like Medical equipment & Military applications this reliability factor plays a
very critical role in determining the acceptance of product. Insertion of special modules in the main design for reliability enhancement will give considerable amount of area & power penalty. So, a novel approach to this problem is to find ways for reusing the already available components in digital system in efficient way to implement recoverable methodologies. Triple Modular Redundancy (TMR) has traditionally used
for protecting digital logic from the SEUs (single event upset) by triplicating the critical components of the system to give fault tolerance to system. ScTMR- Scan chain-based error recovery TMR technique provides recovery for all internal faults. ScTMR uses a roll-forward approach and employs the scan chain implemented in the circuits for testability purposes to recover the system to fault-free state. The proposed
design will incorporate a ScTMR controller over TMR system of ALU and will make the system fault tolerant and fault recoverable. Hence, proposed design will be more efficient & reliable to use in critical applications, than any other design present till today.
DUALISTIC THRESHOLD BASED MIN-MAX METHOD FOR VOICE SIGNAL ENHANCEMENTVLSICS Design
In this article, unwanted transitory assessment is specified by averaging previous phantom power
standards and through a levelling stricture that is in step by the symbol existence likelihood in sub-bands.
A two threshold based min-max method is proposed that we compare with the recursive averaging (RA)
approach for unwanted transient assessment with SAL (spectral amplitude with logarithm assessment) in
voice signal enrichment .The SAL procedure includes a transient assessment and the unwanted transient
PSDs in virtual stationary form, and enrichment of voice signal. It is proficient of tracing the incoming
signal rapid variations in spectra and supports to assessment of PSD for transients effectively. The
unwanted transient assessment is much efficient by proposed method as compared to SAL method and RA
in terms of the voice signal power to noise ratio (SNR). And finally by simulation modelling we show the
results.
Static power optimization using dual sub threshold supply voltages in digital...VLSICS Design
Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
In this paper, we propose and investigate a schottky tunneling source impact ionization MOSFET (STSIMOS)
with enhanced device performance. STS-IMOS has silicide (NiSi) source to lower the breakdown
voltage of conventional impact ionization MOS (IMOS). There is cumulative effect of both impact
ionization and source induced tunneling for the current gating mechanism of the device. The silicide source
offers immensely low parasitic resistance subsequently there is an increment in voltage drop across
intrinsic region. This leads to appreciable lowering of breakdown and threshold voltage for STS-IMOS.
Hence, it demonstrates enhanced device performance over conventional IMOS. Besides this for STS-IMOS
the location of maximum electric field has shifted towards the source and now it is quite away from gateoxide. Hence, it shows high immunity against Vth fluctuations due to hot electron damage. Consequently, itis found that device reliability is also improved significantly.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio (SDR) with high degree of flexibility and low power consumption has been a major challenge to the
scientific community ever since its conception. The basic philosophy of SDR is to implement different modulation or demodulation schemes on the same underlying hardware. Currently available high performance DSP processors, optimized with ‘Very Large Instruction Word (VLIW)’ architecture and multiply and accumulate (MAC) units, are unable to meet the near real time speed requirements of
Software Defined Radios (SDR) due to their inherent sequential execution of compute intensive signal
processing algorithms. Moreover, their power dissipation is considerably high. Even though, Application Specific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of their lack of flexibility. Various references on FPGA based implementations of reconfigurable architectures for SDRs are also available. However, the Look-up Table (LUT) based implementations of FPGAs are not
optimum and therefore, cannot offer highest performance at low silicon cost. Keeping this view, this paper presents the design of a configurable communication processor for Software Defined Radio. The proposed
scheme features the performance of an ASIC based design combined with the flexibility of software. Experimental results reveal that the proposed architecture has minimum hardware requirement, improved silicon area utilization and low power dissipation.
MODIFIED MICROPIPLINE ARCHITECTURE FOR SYNTHESIZABLE ASYNCHRONOUS FIR FILTER ...VLSICS Design
The use of asynchronous design approaches to construct digital signal processing (DSP) systems is a
rapidly growing research area driven by a wide range of emerging energy constrained applications such
as wireless sensor network, portable medical devices and brain implants. The asynchronous design
techniques allow the construction of systems which are samples driven, which means they only dissipate
dynamic energy when there processing data and idle otherwise. This inherent advantage of asynchronous
design over conventional synchronous circuits allows them to be energy efficient. However the
implementation flow of asynchronous systems is still difficult due to its lack of compatibility with industrystandard
synchronous design tools and modelling languages. This paper devises a novel asynchronous
design for a finite impulse response (FIR) filter, an essential building block of DSP systems, which is
synthesizable and suitable for implementation using conventional synchronous systems design flow and
tools. The proposed design is based on a modified version of the micropipline architecture and it is
constructed using four phase bundled data protocol. A hardware prototype of the proposed filter has been
developed on an FPGA, and systematically verified. The results prove correct functionality of the novel
design and a superior performance compared to a synchronous FIR implementation. The findings of this
work will allow a wider adoption of asynchronous circuits by DSP designers to harness their energy and
performance benefits.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
This paper presents a novel Handover mechanism to minimize target Femto Access Points (FAPs) list
during macro-to-femto and femto-to-femto handover in LTE based Macro-Femto Heterogeneous Networks.
HandOver is the procedure that transfers an ongoing call from one cell to another as the users move
through the coverage area of cellular system. The femtocell has a limited coverage area (15 meters to 30
meters), and subsequently, HandOver is decided based on mobile User Equipment (UE) speed for handover
between macrocell-to-femtocell and femtocell-to-femtocell. In the existing networks, for handover
procedure, serving Base Station will decide the cell selection based on mostly the signal strength of the
neighbouring femtocells. This information is provided by the Measurement Reports sent by the
corresponding UE. In this paper, we present a novel handover management scheme which considers both
the Received Signal Strength and Cell Load of the target Femtocells for making the Handover decision.
This proposed scheme for macro-femto heterogeneous network reduces the number of target FAPs to avoid
handover to overloaded femtocells and also reduce the number of handovers.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
A new efficient fpga design of residue to-binary converterVLSICS Design
In this paper, we introduce a new 6n bit Dynamic Range Moduli set { 22n, 22n + 1, 22n – 1} and then present
its associated novel reverse converters. First, we simplify the Chinese Remainder Theorem in order to
obtain an efficient reverse converter which is completely memory less and adder based. Next, we present a
low complexity implementation that does not require the explicit use of modulo operation in the conversion
process and we demonstrate that theoretically speaking it outperforms state of the art equivalent reverse
converters. We also implemented the proposed converter and the best equivalent state of the art reverse
converters on Xilinx Spartan 6 FPGA. The experimental results confirmed the theoretical evaluation. The
FPGA synthesis results indicate that, on the average, our proposal is about 52.35% and 43.94% better in
terms of conversion time and hardware resources respectively.
EVALUATION OF ATM FUNCTIONING USING VHDL AND FPGA VLSICS Design
It has been almost four decades that banks and other financial organizations have been gradually computerised, in order to improve service and efficiency and to reduce cost. The birth of Electronic Fund Transfer and Automated Teller Machines has given rise to 24-hour banking and a greater variety of services for the customer. This method uses a computer to transfer debits and credits, with the help of electronic pulses, which are carried through wires either to a magnetic disk or tape. ATM (Automated
Teller Machine) has become an important part in our daily lives. People use ATM for various purposes such as money withdrawal, checking balance, changing password etc. Since it mainly deals with people's
money, it has to be a secure system on which we can rely. We have taken a step towards increasing this
security and integrity by trying to implement the functioning of an ATM using VLSI-based programming, HDL(Hardware Description Language).The conventional coding languages such as C,C++ are replaced by VHDL(Very High Speed Integrated Circuit Hardware Description Language) so that the code cannot be easily hacked or changed. This article consists of an insight into the various functions that can be
performed using an ATM, a brief description of the Coding and the obtained simulation results. It alsoconsists of the implementation of the code using FPGA Kit (Spartan3; Model no.-XC 3S50).
An Enhanced FPGA Based Asynchronous Microprocessor Design Using VIVADO and ISIMjournalBEEI
This paper deals with the novel design and implementation of asynchronous microprocessor by using HDL on Vivado tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time. The complete design has been synthesized and simulated using Vivado. The complete design is targeted on Xilinx Virtex-7 FPGA. This paper more focuses on the use of Vivado Tool for advanced FPGA device. By using Vivado we get enhaced analysis result for better view of properly Route & Placed design.
System Development for Verification of General Purpose Input OutputRSIS International
In SoC no. of IP block inside it depends upon specific
application, increase in the Ip block increases no. of digital
control lines causes increase in the size of the chip. GPIO helps
internal IP blocks to share digital control lines using MUX and
avoids additional circuitry. Since design productivity cannot
follow the pace of nanoelectronics technology innovation, it has
been required to develop various design methodologies to
overcome this gap. In system level design, various design
methodologies such as IP reuse, automation of platform
integration and verification process have been proposed. GPIO
configuration register decides in which mode system has to work
GPIO has four modes i.e input, output, functional, interrupt. As
per operation particular mode is selected and the operation get
performed. Devices with pin scarcity like integrated circuits such
as system-on-a-chip, embedded and custom hardware, and
programmable logic devices cannot compromise with size can
perform well without additional digital control line circuitry.
A 16-bit microprocessor I designed during my final semester (2005) of my Bachelor of Technology program. The microprocessor circuitry design was coded in VHDL and then configured in a Xilinx XC9572 PC84 CPLD kit. Most of the design, the architecture and the instruction set were taken from Computer System Architecture (3rd ed.) by M. Morris Mano. See https://github.com/susam/mano-cpu for VHDL source code and other related files.
DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSORVLSICS Design
Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream
to get increased throughput, and it lessens the total time to complete the work. . The major objective of this
architecture is to design a low power high performance structure which fulfils all the requirements of the
design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E
XC3E 1600e device with Xilinx tool.
Design and Analysis of A 32-bit Pipelined MIPS Risc ProcessorVLSICS Design
Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the
design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models.
DESIGN AND ANALYSIS OF A 32-BIT PIPELINED MIPS RISC PROCESSORVLSICS Design
Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models.
This study paper portrays a fresh approach for
a course and laboratory design to establish low cost prototypes
and other entrenched devices that accentuate virtual
programmable logic device (VPLD), object oriented java and
real time processing tactics. JAVA is used for software
development. The study encompasses the use of host and node
application. A high performance, low power AVR with high
endurance non-volatile memory segments and with an advance
RISC structure is used to construct prototypes. The paperwork
deals with the VPLD board which is capable to work as
corresponding digital logic analyzer, equation parser, standard
digital IC and design wave studio
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Advanced Verification Methodology for Complex System on Chip VerificationVLSICS Design
Verification remains the most significant challenge in getting advanced SOC devices in market. The
important challenge to be solved in the Semiconductor industry is the growing complexity of SOCs.
Industry experts consider that the verification effort is almost 70% to 75% of the overall design effort.
Verification language cannot alone increase verification productivity but it must be accompanied by a
methodology to facilitate reuse to the maximum extent under different design IP configurations. This
Advanced reusable test bench development will decrease the time to market for a chip. It will help in code
reuse so that the same code used in sub-block level can be used in block level and top level as well that
helps in saving cost for a tape-out of a chip. This test bench development technique will help us to achieve
faster time to market and will help reducing the cost for the chip up to a large extent.
Accelerating Real Time Applications on Heterogeneous PlatformsIJMER
In this paper we describe about the novel implementations of depth estimation from a stereo
images using feature extraction algorithms that run on the graphics processing unit (GPU) which is
suitable for real time applications like analyzing video in real-time vision systems. Modern graphics
cards contain large number of parallel processors and high-bandwidth memory for accelerating the
processing of data computation operations. In this paper we give general idea of how to accelerate the
real time application using heterogeneous platforms. We have proposed to use some added resources to
grasp more computationally involved optimization methods. This proposed approach will indirectly
accelerate a database by producing better plan quality.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Epistemic Interaction - tuning interfaces to provide information for AI support
An integrated approach for designing and testing specific processors
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
AN INTEGRATED-APPROACH FOR DESIGNING
AND TESTING SPECIFIC PROCESSORS
1,2,3
Cesar Giacomini Penteado, 4Edward David Moreno, 1Sérgio Takeo Kofuji
1
University of Sao Paulo (USP), Sao Paulo, Brazil
LSI-TEC of University of Sao Paulo, Sao Paulo, Brazil
3
UNIVEM – Centro Universitário Euripides de Marilia, Brazil
4
Federal University of Sergipe (UFS), Aracaju, Brazil
2
ABSTRACT
This paper proposes a validation method for the design of a CPU on which, in parallel with the
development of the CPU, it is also manually described a testbench that performs automated testing on the
instructions that are being described. The testbench consists of the original program memory of the CPU
and it is also coupled to the internal registers, PORTS, stack and other components related to the project.
The program memory sends the instructions requested by the processor and checks the results of its
instructions, progressing or not with the tests. The proposed method resulted in a CPU compatible with the
instruction set and the CPU registers present into the PIC16F628 microcontroller. In order to shows the
usability and success of the depuration method employed, this work shows that the CPU developed is
capable of running real programs generated by compilers existing on the market. The proposed CPU was
mapped in FPGA, and using Cadence tools, was synthesized on silicon.
KEYWORDS
Validation, Testbench, FPGAs, Microcontroller, Cadence, ASICs
1. INTRODUCTION
The development of any processor includes an extra work to obtain a validation of each of the
operations done for it, which are seen by programmers as instruction implemented. During the
encoding of a processor, either in Verilog, VHDL, SystemC or other hardware description
language, the description evolves until the first stable versions are obtained. During this process
may occur a collapse of some instructions or blocks already previously validated, due to changes
in the hardware encoding.
This paper proposes a simple validation and development method which automatically validates
the computation of each instruction described. This method also keeps the CPU designed in an
idle state, in case of error detection. The encoded program memory itself can be described with
some structures of decision and it can be used as a testbench, simply connecting target registers as
a feedback.
The proposed method repeats the tests from the first instructions to the new and current
instruction being described. It easily shows possible errors during the progress of the CPU
encoding. Figure 1 illustrates the concept of the proposed method. In figure 1, on the top, it can
DOI : 10.5121/vlsic.2013.4501
1
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
be seen a classic simplified Von Neumann CPU being developed, and it accesses its program
memory. Several programs must be written in this memory to test the proper operation of its
instructions. At the bottom, it is proposed that this memory is modified and strongly coupled to
the CPU, in order to obtain a feedback of its own instructions that were requested by the CPU.
Thus, automatic tests can be performed to validate the correct execution of the each instruction.
For each register of interest, in each CPU project, it is proposed that it is made a bus connecting
the register and the program memory, making a testbench, which contains the instructions and
data to be sent to the CPU. Thus, the testbench is stimulated by the results of its own instructions,
progressing or not with the tests. To prove its efficiency, the proposed method was applied in the
development of a VHDL version of a real CPU. It is compatible with the CPU present in the
PIC16F628 microcontroller, which was successfully validated.
ADDR
DOUT
PROGRAM
MEMORY
A
B
ALU
PC
X
Y
R
4
3
2
1
0
STACK
UC
EXTERNAL RESET
ADDR
PROGRAM
MEMORY
DOUT
B
ALU
RESET
LOGIC
A
PC
X
Y
R
UC
4
3
2
1
0
STACK
Figure 1. Validation method where feedback registers act in the Testbench
A previous processor was designed by the autors and it called as UPEM (Processing Unit Specific
for Peripheral) [Penteado, 2009, Penteado, 2011]. The UPEM have a limited processing
capability and it was designed for specific purposes of low power and minimal area. The
presented method in this work was conceived to make a new UPEM processor, full compatible
with real programs existing on the market. Thus, the proposed CPU is an evolution of UPEM and
it is here referred to as UPEM2. It was validated in Cadence digital tools and physically validated
in FPGA. The tests were carried out in the LSITEC Design House of the University of Sao Paulo,
a laboratory specialized in microelectronics and project for industrial applications.
2
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
2. RELATED WORKS
The works listed here clearly show an evolution in the design methodology and verification of
processors. It is also related the works that performed VHDL descriptions of parts of the PIC
microcontroller.
In [Hu, 1994] the authors present an activity diagram with a technique of resources distribution
for verification. The verification methodology presented was divided into: (i) Specifications of
engineering requirements. The required information includes registers maps, descriptions of the
internal buffers, comparators, counters, initial values of registers, a fast algorithm of how the
project will be used and a list of external devices to be used; (ii) Verification plan, which is a
baseline for the verification engineer; (iii) Final test chip and code test; (iv) Layout preparation;
(v) Post-layout simulation and; (vi) Creation of operation vectors, that are useful for testing the
chip in operation.
In [Zhenyu, 2002], the authors present a methodology for functional verification based on
simulation to validate a 32 –bit RISC microprocessor, in which the pseudo-random generating
method and a method focused on pipeline were used to generate testbenches. This paper proposed
a bottom-up verification strategy, consisting of three stages: (i) in the first stage, the goal is to
check the basic functions of each module. So, the authors showed that are not necessary to have
many testbenches and the handwriting can be used. The authors showed that handwriting is a
good direction; (ii) in the second stage, the main functions and the interfaces between the blocks
need to be checked and, obviously, the number of needed testbenches increases considerably; (iii)
in the final stage, the handwriting method is used to verify borderline cases – minimum and
maximum values of registers, software parameters, addressing, stack use, and other parameters.
In [Schmitt, 2004], the Tricorel, an IP owner of a microcontroller, provided by the company
Infineon, was mapped in FPGA and the performance of some algorithms was verified, among
them the Euclidian algorithm that calculates the MDC of a number, the result of Fibonnacci for
number 10,000 and Erastothenes that calculates the first 1000 prime numbers.
In [Castro, 2008], the authors proposed an efficient and functional methodology based on a
framework of parameters domain. Additionally, this work has presented an automated tool for
generating sources of stimuli in SystemC language, from a specification module of parameters
domain. The authors implemented a test environment consisting of five modules around the RTL
model under test. Even with the use of automated tools, the source of stimuli needs to be defined
during the project and must be written manually.
In [Kwanghyun, 2008], the authors presented a reusable project platform for integration and
verification of SOC based on the IP reuse and IP-XACT standard, which is a specification for
SoC in Meta data XML, as a standard for describing the components of a SoC platform. This
specification describes an IP under several aspects: hardware model, signs, bus interface, memory
map, address space and model views.
In work [Penteado, 2009], the authors developed and physically validated a CPU, known as
UPEM (UPEM means Processing Unit Specific for Peripheral). The UPEM was developed to
perform peripheral functions of microcontrollers and consists of a reduced PIC CPU version. We
have used the CQPIC version [Morioka, 1999]. The UPEM has a few PIC registers, a reduced
address space and, thus, it is able to address only a single RAM block. The Morioka´s
development is different from our work, because it was focused on another microcontroller from
Microchip, the PIC16F84.
3
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
In [Wrona, 2011], the authors developed a design methodology of tests for the final digital circuit,
composed by a software/hardware environment in with, the software parts is being executed at a
Personal Computer and the hardware parts are mapped in a FPGA device. This methodology is
different from our work, because the tests are performed in the final digital circuit, while our
methodology is used during the development of digital circuit.
In [Amandeep, 2012] the authors proposed a system composed by a microcontoller chip and a
FPGA device that performs standard tests in the digital circuit under development. The novel
feature is that there no need of test patter generator and output analyser as microcontroller
performs the function of both. There are some similar characteristics with our work: the proposed
system is used while the digital circuit is under development and; the microcontroller is used to
compares the outputs of digital circuit with a predefined set of expected values. In our work, the
last task is performed by the testbench.
In other works, [Meng, 2010], [Becker, 2012], [Cha, 2012] and [Zhaohui, 2012] the authors
discuss about modern techniques to verify the final digital circuit, in order to detects errors in the
entire design. These techniques includes the use of SystemC and SystemVerilog languages, UVM
- Universal Verification Methodology - and, Co-design approaches to test and verify modern and
complexes System On a Chips. These researches has focus on development of systems composed
by digital and analog parts, differing of our purpose. Our work is exclusively aimed to digital
development.
3. AN INTEGRATED - APPROACH FOR DESIGNING AND TESTING
SPECIFIC PROCESSORS
The need to continually check a processor or a specific digital system under development is an
expensive task. Therefore, it is possible that the proposed method could assist in the development,
by means of self verification of the project under development. For this, we simply describe a
testbench with some feedback lines and continuously we made a comparison using a few
structures with previously known values.
According to [Hu, 1994], the hardware engineer encodes and performs basic tests on the chip
under development. These basic tests can be interpreted as being close tasks to the proposed
method. In [Zhenyu, 2002], the work cited the formal verification methods and the simulationbased verification. The last one applies testbenches to stimulate a project and a reference model.
Thus, the functionality of the project can be known by comparing the final results.
In [Schmitt, 2004], whereas TriCore1 IP is a complete microcontroller core and has already been
validated by Infineon, the verification method differs from our proposal since it is focused on
software and our method is implemented directed in hardware.
According to [Castro, 2008], one of the alternatives used to complete the design of a SoC, core
or task verification of a module is the functional verification, in which a model in hardware
description language in the RLT level is stimulated both random and direct stimuli. Even using
automated tools, the source of stimuli needs to be defined during the project and must be written
manually. In [Kwanghyun, 2008], the first step of the SoC platform design is an exploration and
optimization stage of the architecture, accompanied by an intense architectural analysis.
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5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
3.1 THE PROPOSED METHOD
The validation method used in this work could be reused in new developments of new processors.
Figure 2 illustrates an example of a developing processor and three simple programs to test the
correct execution of the instructions. The detailed architecture of the developing CPU is the same
as illustrated in Figure 1. In the examples in Figure 2, our convention is the following mnemonic:
(i) MOV X, to move data from the program memory to the destination register, (ii) STO X to
store the results of ALU´s operations and; (iii) ADD, SUB and MUL that perform addition,
subtraction and multiplication between registers A and B.
In Figure 2, the verification of the program results and the CPU running is done manually; it is an
expensive task and may contain typing errors, in case the CPU come to have complex instructions
and actions in many registers. In this stage, the CPU is under development and deep changes in
the RTL description may occur, leading to a new manual verification cycle of all instructions that
have already been validated.
DOUT
ADDR
PROGRAM ROM
DOUT
ADDR
0
1
2
3
4
5
MOV A
0x05
MOV B
0x03
ADD
STO R
MANUAL
VERIFICATION
R = 08
?
0
1
2
3
4
5
MOV A
0x05
MOV B
0x03
SUB
STO R
MANUAL
VERIFICATION
R = 02
?
0
1
2
3
4
5
MOV A
0x05
MOV B
0x03
MUL
STO R
CPU
UNDER
DESIGN
EXTERNAL
RESET
OTHERS
TESTS
MANUAL
VERIFICATION
R = 0F
?
TEST 1
TEST 2
TEST 3
PROGRAM ROM: MANY TEST PROGRAMS
Figure 2. Manual verification of the instructions being developed
Figure 3 illustrates in detail our method, proposed and used in this work, which can help during
the development of any CPU, making the verification of results an automated task. In figure 3,
the same CPU illustrated in figure 1 is under test. The same programs used in figure 2 are
represented by PROG 1, 2 and 3. The fundamental difference is that the program memory is no
longer a simple memory and it becomes an efficient depuration mechanism for the CPU
computations.
It has been necessary a simple coding of the verification logic of the results, represented by
LOGIC 1, 2 and 3. This coding was done manually. With a simple feedback from the target
registers, one comparison between the value received and the expected value is sufficient for
automatically validating the results of the instructions and the architecture.
In figure 3, the sequence of the automated testing occurs, if the logic indicates success; if any
value difference is detected, the CPU stops its activities.
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6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
At the end of each test successfully performed, a reset is sent to the CPU, making each test can be
independently from each other. Thus, the CPU description can be changed several times and, to
check it, just simulate the system again waiting for the successful passage through all instructions
or phases which were previously written and were related to validated tests.
ADDR
DOUT
RESET
PROGRAM ROM
(TESTBENCH)
ADDR
CPU
UNDER
DESIGN
DOUT
PROG 1
PROG 2
PROG 3
LOGIC 1
LOGIC 2
LOGIC 3
IDLE STATE
RESET
TEST 1
TEST 2
RESET
OTHERS TESTS
TEST 3
PROGRAM ROM: MANY TEST PROGRAMS
Figure 3. Detailing of the proposed method
3.2 APPLICATION OF THE PROPOSED METHOD
The validation method detailed in section 4 of this work was applied during the development of
UPEM2. The datasheet of PIC16F62X, provided by Microchip [PIC16F62X] was used for the
verification of operations. We used details of each instruction and we obtained the respective
numbers of cycles used for each instruction. The final simplified architecture of UPEM2 is
illustrated in figure 4. Both, PORTA and PORTB are bidirectional.
PC
STACK
(8 levels)
ROM PROGRAM MEMORY
2kbytes X 16
RAM REGISTER FILE
224 X 8
ALU
STATUS
PORTA
PORTB
W
TRISA
TRISB
Figure 4. UPEM2 compatible with the PIC16F628 CPU
To apply the method proposed in this work, the first step was to provide the direct access to the
internal registers through buses, as illustrated in figure 5.
In figure 5, only the registers considered important have been represented and we have shown
them in this work. In this CPU, we monitoring: (i) the current values in the main registers
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7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
STATUS, W, PORTA, TRISA, PORTB and TRISB; (ii) lower and upper limits of the cell, (iii) at
least one data present in the RAM memory, in this case RAM[0] and RAM[224]; (iv) the current
value in PC, which differs from the current value in ADDR; (v) the value of ADDR, which refers
to the access to different addressable internal registers and internal RAM memory; and (vi) two
temporary registers created for debugging purposes, CYCLES counting machine cycles and
CNT_CLK that stores the actual value of clocks spent in the instructions execution.
The second step in the application of the proposed method was the interconnection between the
buses listed in figure 5 and the developed testbench, partially illustrated in figure 6.
ADDR
DOUT
PC
PROGRAM
MEMORY
ADDR
0
RESET
7
LOGIC
224
RAM REGISTER
FILE 224 X 8
STATUS
0
STACK
(8 LEVELS)
W
PORTA
TRISA
PORTB
TRISB
CYCLES
CNT_CLK
Figure 5. External access to the target registers of UPEM2
In figure 6, the values of the registers are considered as stimuli for each test performed. The tests
consist of programs to test each instruction being developed. The results are verified using simple
comparators, written manually in code, with respectively comparison values which should
previously be known and encoded.
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8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
PC
ADDR
STACK 0
STACK 8
RAM[0]
STATUS
W
PORTA
TRISA
PORTB
TRISB
N
IDLE
STATE
S
MOVLW 0X05
NOP
NOP
NOP
NOP
NOP
NOP
1. RESET
2. NEXT TEST
PC
ADDR
STACK 0
STACK 8
RAM[0]
W
STATUS
W
PORTA
CYCLES
CNT_CLK
W = 05 ?
TEST 1
CYCLES
CNT_CLK
TRISA
PORTB
TRISB
0
1
2
3
4
5
6
W
W = 0F ?
IDLE
STATE
S
STATUS
STATUS
= 18 ?
S
Test 1: Instruction MOVLW
Store 0x05 in W
STATUS None
movlw 0x05
0
1
2
3
4
5
6
RAM[0]
N
TEST 2
DOUT
RAM[0]
= 05 ?
N
IDLE
STATE
MOVLW 0XFF
MOVWF 0X20
MOVLW 0X0F
MOVF 0X20,f
NOP
NOP
NOP
DOUT
S
1. RESET
2. NEXT TEST
N
IDLE
STATE
Test 2: Instruction MOVF
Store 0xFF in W,
0xFF in RAM[0],
0x0F in W
Return 0xFF in RAM[20]
STATUS None
Figure 6. Partial detailing of the testbench
The testbench has been developed taking care that each instruction can be validated in its origin
modes or data destiny. For this reason, our case study, the UPEM2´s processor has several
addressable registers.
Another care for writing this testbench, we have used only instructions that have already been
validated in previous tests which are used for writing new tests. Thus, it started with simple
instructions for moving data between registers (movlw, movwf) and then new instructions such as
arithmetic and logic (addwl, sublw, andlw, xorwl, etc.) were included.
Thus, the test advances to the next instruction if just the previous test has been successful. The
writing of this detailed testbench has allowed us a validation of the UPEM2, and possible changes
or enhancements have been revalidated by the testbench itself. This eliminates the visual
verification of functionality of each modified or optimized instruction.
When each instruction is validated, a reset pulse is automatically sent to UPEM2, ensuring that all
instructions under test will have all their registers “clean”. Thus, there will be no risk of previous
instructions influencing the next ones.
Figure 7 illustrates a part of this testbench, where it can be observed that according to the
received address in ADDR, the testbench returns instructions and data in “dout”. In the test
shown in figure 7, based on the input values RAM [0], the registers W and STATUS, the
testbench is able to validate or not the final values in these registers and the instruction set
involved.
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9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
--####################################################################
-- MOVF
--####################################################################
elsif count_inst = 131 then
case ADDR is
------------------------------------------------------------------------------- Test MOVF
-- Store 0xFF in W, 0xFF in RAM[0], 0x0F in W and return 0xFF in W
-- STATUS None
-------------------------------------------------------------------------------movlw 0xFF
--movwf 0x20
--movlw 0x0F
--movf 0x20,w
when conv_std_logic_vector(0,13) => dout <= "11000011111111";
when conv_std_logic_vector(1,13) => dout <= "00000010100000";
when conv_std_logic_vector(2,13) => dout <= "11000000001111";
when conv_std_logic_vector(3,13) => dout <= "00100000100000";
when others => dout <= "00000000000000";
end case;
if (W = "11111111") and (STATUS = "0011000") and (RAM = "11111111") then
inst_ok <= '1';
RST <= '0';
count_rst <= 0;
end if;
if inst_ok = '1' then
count_rst <= count_rst+1;
if count_rst = 1 then
RST <= '1';
inst_ok <= '0';
count_inst <= 132;
end if;
end if;
elsif count_inst = 132 then
case ADDR is
------------------------------------------------------------------------------- Test MOVF
.
.
.
Figure 7. Part of the testbench developed
If the final, in case of values match the expected values, the testbench generates a reset signal
RST and it starts a new test for a new instruction. If the final figures are not as expected, the data
throughout the system can be freeze, even with the clock active, leading the CPU to an idle state.
This testbench allowed the validation of about 150 tests in 34 instructions described. Possible
modifications and optimizations were easily revalidated, simply going over all the automated
tests. The instruction tests with the testbench were considered sufficient, and it was started the
final validation stage of UPEM2, with real programs.
In our methodology, we always chosen the main registers to be routed into memory, such as A
and B registers, ALU result register, Program Counter, Instruction Register, the top and bottom of
the stack, etc. Another specific registers of interest can be easily routed.
Modern processors involve hundreds of possible instructions and each of them might involve
multiple possible addressing modes. In this case, it is possible that several instructions have a
similar behavior and addressing modes. Some tests can be reutilized, just changing the expected
final values.
The method can be portable among processors with significantly different ISAs. The technique is
the same, regardless of ISA used. In this case, a new study of the architecture must be performed
and a new testbench must be written.
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10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
The proposed method includes an extra logic synthesized for validation purposes. This extra logic
can be easily removed. This is composed by buses between the program memory and the CPU
under development and a few comparators inside program memory.
4. A CASE STUDY - FINAL VALIDATION OF A PROCESSOR
For the final validation on physical level of a processor, in our case we have used the developing
of UPEM2, it is a specialized processor for running some peripheral functions of microcontrollers
[Penteado 2009, Penteado 2011]. In this paper, we have used two programs that make up games
in the PIC16F628 microcontroller which were simulated in three ways: (i) in the ModelSim
software [ModelSim, 2012], (ii) simulation Cadence tools and (iii) specific simulators for
PIC16F628. After achieving full compatibility between the simulations, the VHDL description
was mapped in FPGA Spartan XC2S200E with the software Xilinx ISE 9.1, both from Xilinx
[Xilinx, 2012]. The FPGA prototype faithfully reproduced the same behaviour obtained
previously by simulation way when we let the execution of the two programs tested. The Cadence
simulator indicated success in all the UPEM2´s operations and, subsequently, the project in ASIC
was started.
Aiming the full compatibility between UPEM2 and the existing compilers for the PIC16F628, the
following steps were completed: (i) to keep the compatibility between the UPEM2 and existing
programs, several simulators were studied and simulators with easy interaction have been chosen
for step-by-step functions when running the code execution; (ii) The simulators chosen were
Feersum miSim DE [Feersum, 2007] and Pic Simulator IDE developed by Vladimir Soso, from
OshonsSoft (2010); (iii) with PIC Simulator IDE, the number of cycles and the execution of each
isolated instruction were compared to the results obtained in the ModelSim and the UPEM2
testbench and; (iv) real programs that can use the greatest number of instructions from PIC and
that run properly with minimal external hardware was obtained;
The actual programs chosen were two games, Tetris an Pong, both developed by Rickard Gunée
[Rickard, 2003], which are complex programs that generate composite video signal NTSC.
It was initially conceived the use of the benchmark programs used in [Schmitt, 2004], however, it
was chosen the use of games to facilitate the visualization of the physical tests in FPGA. The
remainder of this section is divided into a short presentation of the Feersum miSim De software, a
comparison of the Tetris game execution when it is running into the UPEM2, using ModelSim
tool, and into the PIC Simulator IDE software and, we show physical tests of UPEM2 when it
was prototyped in FPGAs.
4.1 DEPURATION OF THE TETRIS GAME WITH FEERSUM MISIM SOFTWARE
The “Feersum miSim De” software [Feersum, 2007] does not provide advanced depuration
operation, however, it has been chosen because it provides a plug-in that allows doing simulations
using a television set and it receives a composite video signal.
Figure 8 illustrates the main interface of the “Feersum miSim De” program and figure 9
illustrates the result of the Tetris game in the simulator using that plug-in. This plug-in was
developed by the authors of the software specifically to emulate the behaviour of the two actual
programs (Testis ad Pong) which were selected by us as target test of our UPEM2´s processor.
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11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 8. Feersum miSim De simulator and its Tetris game plug-in
With this software installed and properly displaying the images of Tetris game in its plug-in, it
was possible to include breakpoints into the program memory to verify the exact moment when
the several images of the program are created and displayed in the plug-in.
The UPEM2 was charged with the Tetris program, compiled for PIC16F628, no longer using the
testbench. For this, the tetris.hex program available at [Rickard, 2003], has been translated
directly into a VHDL description that represents the program memory of PIC, through hex2vhd
program, this is a part of the CQPIC project [Morioka, 1999].
Some changes were necessary into the VHDL description after generated by the hex2vhd
program to make it adequate to our UPEM2. Thus, it was possible to simulate the execution of
the real Tetris program into the ModelSim environment.
4.2 THE PIC SIMULATOR IDE SOFTWARE
The PIC Simulator IDE software [Oshonsoft, 2010] is an excellent tool for debugging and
depuration of the operation of programs developed for PIC Microcontrollers. The features
considered most important to assist in the development of UPEM2 were: (i) its cycle count, the
depuration of the next instruction and the last opcode executed; (ii) inclusion of breakpoints and;
(i) the viewing of all the registers values, RAM, ROM, and I/O gates. The Tetris program was
charged into the PIC Simulator IDE software and its execution was compared to data obtained
when it executes the same program and we used the ModelSim software. The details of the PIC
Simulator IDE relevant to this work are highlighted and illustrated in figure 9.
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12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 9. PIC Simulator IDE, by OshonsSoft [Oshonsoft, 2010]
The main purpose of this comparison was to verify the count of cycles spent to execute the
programs and compare them to the cycle count of UPEM2 being simulated in the ModelSim
software, besides verifying the final behaviour of the actual program tested. In figure 10, we have
showed a simulation of UPEM2 in the ModelSim software with the same program that was
charged into the PIC Simulator IDE software, as seen in figure 9.
Figure 10. UPEM2 simulation in the ModelSim software
A very positive and encouraging point in the UPEM2 development was that in the highlighted
area (see figure 10), the number of clocks and cycles were identical in both simulations, at the
moment when the same change occurs in PORTAIO in the Pic Simulator IDE.
In figure 10, Instructions Counter and Clock Cycles Counter, have exactly the same value as
“countcicle” and “countclk_d”, in figure 9, which were signals implemented for depuration and
tests. In figure 10, the change is viewed in “portaio in synchrony” with the simulation in the PIC
Simulator IDE software.
After this, both simulators, ModelSim and PIC Simulator IDE, were left in continuous operation
and the results were compared in random points. At all points of our breakpoint the results were
identical and then we decided to stop these tests after ModelSim had run for more than 7 hours,
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on a Intel Core2Duo 4GB DRAM, reaching a bit more than 50 thousand instructions correctly
executed in relation to PIC Simulator IDE.
4.3 PHYSICAL TESTS IN FPGA
In figure 11 a real physical test is illustrated, in which UPEM2 was mapped into the FPGA
XC2S200 with the Tetris game, top right corner, and the Pong game, the lower right corner. The
FPGA, mapped with the UPEM2, RAM memory and ROM with Tetris game, properly generated
the composite video signal and it was possible to execute the game. The video signal being
correctly generated allowed us the implementation of the game´s sounds, which are mapped into
the PIC´s EEPROM. Following the same sequence presented in section 4.2 of this work, the
EEPROM´s information was automatically extracted using the hex2vhd program and some
modifications.
The final result was the Tetris game running in UPEM2, which properly generated the composite
video signal and sound, making it possible to play. With this positive result, it was decided to
repeat the sequence presented in section 4.2 and we execute the program that represents the Pong
game, which has also been correctly executed in UPEM2. Other real programs will still be tested
for further validation of UPEM2.
The UPEM2 was mapped in the FPGA XC2S200 and the utilization data in FPGA were 480
slices (20%) for the CPU and 2018 slices to CPU, four banks of RAM and ROM with program of
Tetris game.
Figure 11. Real test of UPEM2: The Pong and Tetris game on Television
Table 1 shows the final ISA set of UPEM2. The ISA set of the CPU present in the PIC
microcontroller has 35 instructions, while the proposed UPEM2 used 32 of these instructions.
The interruption control hardware was not implemented, so, the instruction RETFIE (interruption
return) can be discarded. There is not either any low-power mode, discarding the SLEEP
instruction. Finally, the watchdogtimer peripheral was not implemented and, therefore, the
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14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
instruction CLRWDT was discarded. For the correct execution of the real programs tested, two
obsolete instructions were implemented in the PIC, the TRISA and TRISB instructions, which
assign values to the gate control registers in only one machine cycle. Thus it amounted to 34
instructions.
Table 1: The ISA set of the proposed CPU
4.4 ASIC DEVELOPMENT
After the success of the description and implementation in FPGA, we begun the UPEM2 project
using the Cadence software [Cadence, 2012], for obtaining an ASIC chip. With the First
Encounter tool, the VHDL description of UPEM2 and the memories mapped with the Tetris
program were compiled for a Verilog description with the cells from the Foundry adopted.
With UPEM2 in Cadence, the description was simulated in the Cadence SimVision software and
the results were compared to the simulation in the ModelSim software.
The results were positive; therefore both simulations behaved the same way. Figures 12 and 13
illustrate both simulations, respectively in ModelSim and Cadence SimVision,
It can be seen at the bottom, highlighted in both figures that the sequence of values at the output
gate PORTB is identical: intermittent values of 00h and change to FEh. It indicates that UPEM2
can function properly in silicon.
The physical design in silicon was designed in the 0.18 technology with 6 metals. Considering the
highest number of metals, a compact layout was obtained without routing errors. The area used
for the whole system, including CPU, RAM, and ROM was approximately 621µm x 517µm, in
the 0.18 technology, disregarding the PADS.
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15. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
Figure 12. UPEM2 executing the Tetris program in ModelSim
Figure 13. UPEM2 executing the Tetris program in Cadence SimVision
5. CONCLUSIONS
This work showed the proposed method conceived to aids the designer in the encoding and
depuration fase of a CPU or dedicated logic. The method consists in some modifications in the
program memory and allows an automatic debug of the encoded logic. Also, this work showed
the applicability of the proposed method in the UPEM2 design, a CPU developed by authors. The
UPEM2 is compatible with the instruction set of the CPU inside in the PIC16F628
microcontroller. All programs tested in the UPEM2 was running successfully in both Modelsim
tool and Cadence tools and also in FPGA device.
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16. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.5, October 2013
The validation of our method proposed can be reused for the development of any other processor.
For this, simply describe the program memory to be connected to the target processor. Following
the same method, it may be possible to adapt any memory and any processor making it possible
to get an automatic validation of the system.
The validation method presented and used in this work has provided a successful development of
a complex CPU. After completing the tests with the testbench, the CPU executed correctly the
programs tested with a few changes in the structure previously validated by the methodology.
According to [Castro, 2008], the manual coding of the stimuli sources can lead to redundant
stimuli generation and invalid test vectors. This can be considered a negative point for the use of
our methodology. Even so, it is considered that the methodology can be used in the development
of any CPU, or even circuits that require stimuli and the results are known in advance.
In our case, the generated testbench has approximately 1000 lines of code manually written,
discounting the comments, and the CPU around 800 lines, only the CPU. Theoretically, the same
manual work, however, with considerable gains in facility of depuration and verification of
results. The evolution from UPEM to UPEM2 has allowed the execution of two real complex
problems developed for the PIC16F628. Other real programs must still be tested to ensure
compatibility with the compilers and real programs.
According to [Zhenyu, 2002], to ensure the functional verification, a code coverage analysis is
necessary to obtain code information not covered by the project verification. Therefore it is
believed that UPEM2 still has some error in the execution of its instructions. These errors can be
detected and corrected with other tools and verification methods, which still are under studied by
us. After the validation in the Cadence software, with the positive results in the SimVision
simulator, the digital layout in ASIC has been completed. The complete project is still in
progress.
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