This document discusses two types of timing analysis for integrated circuits (ICs): dynamic timing analysis (DTA) and static timing analysis (STA). DTA requires input stimuli to check both timing and functionality but is limited to small designs. STA is non-vector based, checks timing without input stimuli, and is suitable for large designs, though results may be pessimistic. While DTA only analyzes activated paths, STA considers all paths, potentially reporting false violations requiring exceptions.

1. DTA vs STA
Timing Analysis of an IC
By
PAYAL DWIVEDI

2. What is Timing Analysis in VLSI?
• Timing analysis is the process used to verify the timing of large digital
circuits (gate level) in order to meet the timing requirements.
• The functionality of an IC depends on the time period of the clock.
• Timing analysis can be done with or without input stimuli.
• It is an integral part of ASIC/VLSI design flow, as we cannot
compromise with the timing of an IC.

3. TYPES OF TIMING ANALYSIS
• The timing analysis in VLSI can be broadly divided as:
• A. Dynamic Timing Analysis
• B. Static Timing Analysis
DTA STA

4. DYNAMIC TIMING ANALYSIS
• This type of timing analysis requires input stimuli
• DTA checks for both timing and functionality of the design.
• Ideal for small design as input is given
• Requires SPICE models to simulate transistor level circuit
• Similarly functional and timing models to simulate gate level circuits

5. Limitations of DTA
• There are some limitations in DTA analysis that gave rise for the need
of STA. Few of them are:
• Designs with large number of inputs will require very large number of
input stimuli combinations for checking functionality and timing.
• Unrealistic number of combinations is required to simulate using DTA
• DTA will not work for large VLSI circuits.

6. STATIC TIMING ANALYSIS
• It is a non-vector based approach
• Here, the functionality of the design is pre assumed to be correct
only.
• It is the process of verifying large gate level circuits without the need
for input stimuli
• STA only checks the timing. Functionality is checked during RTL
Verification stage.

7. PROS & CONS OF STA
ADVANTAGES
• It verifies the timing check for all
paths in design
• It is fast as no input given
• Suitable for large designs
DISADVANTAGES
• Difficult for using in
asynchronous design
• Defined timing
constraints/exceptions required.
• Results are pessimistic

8. DTA vs STA
DTA
• DTA analyses only those paths of
a design that get resolved by
respective input vectors.
• If vector set is incomplete,
resulting in some violation.
• Add more coverage to increase
the coverage.
STA
• STA considers every path of the
design.
• False timing violations are
reported.
• In order to eliminate false
violations, timing exceptions are
added.

9. THANK YOU !