STA vs DTA.pptx
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This document discusses two types of timing analysis for integrated circuits (ICs): dynamic timing analysis (DTA) and static timing analysis (STA). DTA requires input stimuli to check both timing and functionality but is limited to small designs. STA is non-vector based, checks timing without input stimuli, and is suitable for large designs, though results may be pessimistic. While DTA only analyzes activated paths, STA considers all paths, potentially reporting false violations requiring exceptions.
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This document discusses engineering change orders (ECOs) used to fix timing, functional, power, and clock issues after physical design and sign-off. It describes the motivation for ECOs due to tool limitations and differences between implementation and sign-off. Common ECO techniques are listed for timing (driver upsizing, buffer insertion, etc.), power (vt-swapping, downsizing, etc.), and metal-only ECOs. Timing ECO tools from Synopsys, Cadence, and other vendors are also mentioned. Upcoming ECO technologies like dynamic power optimization and automatic legalization are noted.
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Here are the key points about setup time, hold time, and insertion delay in VLSI physical design:
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- Hold time is the minimum time after the clock edge that the data needs to remain stable. It provides a "window" after the clock edge for the data to remain valid.
- Insertion delay is the time it takes for the clock signal to propagate from the clock source to a flip-flop input pin through the clock tree.
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Implementing Useful Clock Skew Using Skew Groups
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The document provides an overview of the PrimeTime static timing analysis tool. It describes PrimeTime's capabilities for design checks and analysis, how it fits into the Synopsys implementation flow, its compatibility with other Synopsys tools, and an overview of static timing analysis concepts like timing paths. The document also discusses starting a PrimeTime session, generating input files, and important commands and reports in PrimeTime like report_timing, report_qor, and analysis_coverage_report.
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This document provides an overview of sequential clocking and static timing analysis for digital VLSI design. It discusses key timing parameters for sequential elements like setup time and hold time. It also explains how static timing analysis works by calculating arrival times and required arrival times for all nodes to find timing violations. The document notes that while static timing analysis is useful, it cannot analyze all timing issues and may report false paths. An example is provided to illustrate how arrival times, required arrival times and slack are calculated for a simple circuit. Finally, it mentions that design constraints must be specified to inform the timing analysis of requirements.
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みなさんこんにちはこれ何文字まで入るの？40文字以下不可とか本当に意味わからないけどこれ限界文字数書いてないからマジでやばい文字数いけるんじゃないの？えこ...
ここ3000字までしか入らないけどタイトルの方がたくさん文字入ると思います。
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みなさんこんにちはこれ何文字まで入るの？40文字以下不可とか本当に意味わからないけどこれ限界文字数書いてないからマジでやばい文字数いけるんじゃないの？えこ...
みなさんこんにちはこれ何文字まで入るの？40文字以下不可とか本当に意味わからないけどこれ限界文字数書いてないからマジでやばい文字数いけるんじゃないの？えこ...
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STA vs DTA.pptx
- 1. DTA vs STA Timing Analysis of an IC By PAYAL DWIVEDI
- 2. What is Timing Analysis in VLSI? • Timing analysis is the process used to verify the timing of large digital circuits (gate level) in order to meet the timing requirements. • The functionality of an IC depends on the time period of the clock. • Timing analysis can be done with or without input stimuli. • It is an integral part of ASIC/VLSI design flow, as we cannot compromise with the timing of an IC.
- 3. TYPES OF TIMING ANALYSIS • The timing analysis in VLSI can be broadly divided as: • A. Dynamic Timing Analysis • B. Static Timing Analysis DTA STA
- 4. DYNAMIC TIMING ANALYSIS • This type of timing analysis requires input stimuli • DTA checks for both timing and functionality of the design. • Ideal for small design as input is given • Requires SPICE models to simulate transistor level circuit • Similarly functional and timing models to simulate gate level circuits
- 5. Limitations of DTA • There are some limitations in DTA analysis that gave rise for the need of STA. Few of them are: • Designs with large number of inputs will require very large number of input stimuli combinations for checking functionality and timing. • Unrealistic number of combinations is required to simulate using DTA • DTA will not work for large VLSI circuits.
- 6. STATIC TIMING ANALYSIS • It is a non-vector based approach • Here, the functionality of the design is pre assumed to be correct only. • It is the process of verifying large gate level circuits without the need for input stimuli • STA only checks the timing. Functionality is checked during RTL Verification stage.
- 7. PROS & CONS OF STA ADVANTAGES • It verifies the timing check for all paths in design • It is fast as no input given • Suitable for large designs DISADVANTAGES • Difficult for using in asynchronous design • Defined timing constraints/exceptions required. • Results are pessimistic
- 8. DTA vs STA DTA • DTA analyses only those paths of a design that get resolved by respective input vectors. • If vector set is incomplete, resulting in some violation. • Add more coverage to increase the coverage. STA • STA considers every path of the design. • False timing violations are reported. • In order to eliminate false violations, timing exceptions are added.
- 9. THANK YOU !