The document discusses challenges in analog circuit design for ultra-deep-submicrometer (UDSM) CMOS technologies. Low supply voltages and increased gate leakage affect transistor performance and circuit design. A comparator circuit is modified from a 0.11-micron to 65-nanometer process to address these issues. The modified design uses amplifier pairs to boost voltages and improve timing at low supply voltages. Measurement results show the modified comparator achieves faster speeds and lower power compared to the original design migrated to 65nm technology.

1. UDSM effects in analog circuit design
Peter Sinko, X141: Advanced Design Techniques for Analog Intergrated-Circuits
UC Berkeley Extension
Abstract - Modern Ultra-Deep-Submicrometer
(UDSM) CMOS technologies pose new challenges
in analog circuit design. Annema et. al. [1]
discussed the significant effects of low supply
voltages and increased gate leakage, offering
practical techniques in analog UDSM CMOS
design. Goll, Zimmermann [2] demonstrated the
migration of a standard comparator to 65-nm
process at 0.65V supply voltage. Significant
performance increase has been achieved: 650ps
decision time at offset of 6.1mV and low delay time
of 93ps, and a power consumption of 128µW at
0.6GHz. The performance in speed and power
consumption of the new comparator and its offset
are an acceptable trade-off.
INTRODUCTION
Transistor scaling efforts dictated by Moore's Law
have proved beneficial for the digital CMOS
technology, but pose new challenges in the analog
arena. Modern mixed-signal systems consisting
of digital and analog blocks on the same die, the
digital CMOS technology in use will be applied to
analog circuits as well. One important result of
scaling is the reduction of supply voltages, from
5V to the current 1.2V. Ultra-Deep-
Submicrometer (UDSM) CMOS technologies
introduce several new phenomena at such low
supply voltages, leaving to challenge the
addressing of new problems in analog design.
Low supply voltages allowing for small voltage
headroom, the dc performance of the transistors
and thus signal integrity degrade. The challenge
now becomes the developing of new circuits that
can diminish the effects of these new phenomena
while preserving already existing performance.
LOW SUPPLY VOLTAGE
Annema et. al. [1] discussed a number of these
significant problems and offered specific
strategies when migrating designs to UDSM
CMOS processes. The low supply voltages at
these technologies offer low voltage headroom
and gate leakage is significant, resulting in
degraded dc properties of MOS transistors and
low signal integrity.
It has been stated by [1] that power consumption
of analog circuits is proportional to the level of
signal integrity and signal frequency. Signal
integrity is generally characterized by its signal-
to-noise ratio SNR and its bandwidth BW. The
available low supply voltages result in low SNR
that, if preserved in the migration to new process,
will result in increased power consumption. This
is a general consequence of importing a fixed
topology to a new process, with signal swing, bias
conditions and device dimensions optimized for
minimum power consumption. According to the
relation between analog performance and power
consumption where only thermal noise is taken
into account
this direct proportion is readily confirmed, where
kT are the Boltzmann's constant and temperature,
SNR is the circuit's signal-to-noise ratio, fsig is
signal frequency, ƞvol is the ratio between peak-to-
peak signal swing and supply voltage, ƞcur is the
efficiency of using supply current. When only
noise within a certain frequency band is taken into
account, the minimum power consumption
relation for a desired SNR becomes
where vOD the overdrive voltage for MOS
transistors, BW is bandwidth, and V is signal
amplitude. Lowering vOD in proportion to
lowering the supply voltage and signal swing is
necessary to avoid further increase in power

2. consumption. Therefore most analog circuits will
require higher power consumption for higher
performance (P~SNR*BW).
Lower supply voltages due to scaling present
additional changes in dc and ac properties of
individual transistors. With vOD levels in
proportion to decreased supply voltage the dc
voltage gain and output are significantly reduced,
Fig. 1. Compensation techniques to boost gain
may include use of cascodes as allowed by the
low voltage overhead, otherwise signal magnitude
reduction to maintain acceptable SNR levels-at
the cost of higher power consumption. The other
strategy is to operate only the necessary parts of
analog circuits at higher supply voltages, that can
reduce overall power consumption for a given
performance.
Gain Output
Fig. 1. gain and output dependence on gate-overdrive
voltage vOD
The ac properties of transistors improve with
smaller dimensions. The relevant factors are the
intrinsic capacitances of transistors whose impact
hardly changes, and junction capacitances that are
in proportion to feature size, leading to smaller
total parasitics and therefore better ac
performance.
GATE LEAKAGE
In addition to low supply voltages, scaling yields
another significant problem in analog design:
gate leakage, the gate current due to tunneling
through the thin gate-oxide. Gate leakage
expressed as the ratio iD/iG is shown to be strongly
dependent on gate length for two leaking
technologies in Fig. 2., and the low current-gain
is clearly identifiable that render long transistors
unusable in UDSM technologies.
Fig. 2. Gate leakage dependence on gate-
length
In circuits utilizing MOS transistor capacitance
for charge storage, gate leakage results in self-
discharge effects that limit the hold-time of
charge stored and also the operating frequency.
Contrasting hold times in the ms range for 180-
nm technologies with low-ns range for 65-nm
technologies, MOS capacitors can no longer be
used in low to medium sample-rate circuits,
rather larger (thick-oxide) MOS devices need be
used instead.
Gate-leakage causes mismatch related limits on
performance in terms of offsets and accuracy, and
improving matching by the classical approach of
simply spending area alone to set an optimum
gm/iD is only effective to certain extent in 90-nm
and 65-nm technologies. Linearly increasing W
and L results in very large leaking areas thus gate-
leakage mismatch becoming a significant effect
that rather be dealt with using mismatch
cancellation techniques or re-design.
DESIGN IMPLEMENTATION: THE
COMPARATOR
In consideration of previous discussion, a widely
used comparator design is presented by Goll,
Zimmermann [2] in 65-nm CMOS technology
with supply voltages down to 0.65V. To
demonstrate design migration to UDSM CMOS,
the design from 0.11-µm/1.2V process is
discussed, and subsequently proposed modified to
65-nm technology.
THE ORIGINAL DESIGN - This comparator
is shown in Fig. 3, a cross-coupled inverters latch

3. featuring high-impedance input, rail-to-rail output
swing and no static power consumption.
Fig. 3. Comparator design for 0.11-μm process
The functioning of the comparator is based on
amplification of the differential input signal
CINP-CINN by turning transistors P0 and P1 on
at different times depending on the magnitude of
the differential inputs, delivering a value at the
output indicating the polarity of the differential
input. The operation of the comparator is as
follows: at first the comparator is reset by
CLK=Vss and N6=OFF, and transistors P2 and P3
initialize outputs OUT and OUT/ to Vco. The
input signals are then applied, and for
CINP>CINN the comparison phase begins with
CLK=Vco, where transistors P2 and P3 are OFF,
N6 is ON. N3 begins discharging OUT/ and N2
discharges OUT, OUT/ reaching the voltage level
Vco-Vtp before OUT does, therefore turning P0
on before P1 is turned on. At this point the
differential output OUT-OUT/ is the amplified
input differential signal CINP-CINN.
Subsequently OUT is pulled to Vco by P0 (N0 is
OFF) and OUT/ is pulled to Vss by N3, indicating
that CINP-CINN is positive or CINP>CINN as
originally applied. Noteworthy fact is that the
drain parasitic capacitances of N2 are cut off from
the output OUT by N0 turning OFF, thereby N2
not contributing to load capacitances and
therefore not affecting switching speed. The
input transistors N2 and N3 can therefore be large
to minimize mismatch and offset. As for the case
CINP<CINN, P1 is turned on before P0, and OUT
is pulled to Vss by N2 and OUT/ to Vco by P1,
indicating the negative polarity of the differential
input.
THE MODIFIED DESIGN - This comparator
designed for 0.11-µm process is not well suited
for UDSM technologies due to the many stacked
transistors, the very low supply voltages available
will be problematic even for a standalone latch,
causing high delay-time. In order the latch to
begin regeneration, transistors P0 or P1 need be
turned on by Vco-Vtp. At much lower supply
voltages this gate-source voltage is also much
smaller: the delay time of the latch will be large
due to low transconductances. In order to migrate
this design to 65-nm process (Vt=0.4V) and
0.65V supply voltage, [2] proposed the modified
latch design of Fig. 4.
Fig. 4. Modified comparator for 65-nm process
Its operation is as follows: the reset phase at
CLK=Vss initializes both outputs
OUT=OUT/=Vco where N6 is OFF, and P2, P3,
N4, N5 are ON. The initial high value at the
outputs turn P4 and P5 OFF, and nodes FB and
FB/ are pulled to Vss by N4, N5 (CLK/). FB, FB/
turn on P0, P1, that in turn pull OUT, OUT/ to the
final value Vco. The next phase is the
comparison phase with CLK=Vco: N6 turns ON,

4. P2, P3, N4, N5 turn OFF. At this point
OUT=OUT/=Vco, FB=FB/=Vss. Transistors P0,
P1, N2, N3 form an amplifier (with N0, N1 ON).
For applied input signals CINP>CINN, transistor
N3 pulls the voltage level at OUT/ down faster
than N2 at node OUT, hence P4 starts to conduct
charging FB toward Vco, and positive feedback in
the cross-coupled latch is started. P1 is turned off
by FB while P0 is still conducting. P5 remains
OFF and FB/ near Vss. Finally N1, P4, P0 are
turned ON, and N0, P1, P5 are turned OFF.
Therefore OUT=Vco, OUT/=Vss, the decision
has been made and no static current can flow. For
the other case CINP<CINN the results are the
opposite: OUT=Vss, OUT/=Vco, indicating the
polarity of the differential input signal. These
results can be inspected in the transient simulation
of Fig. 5. for the cases of 10mV and 100mV input
differences.
Fig. 5. Transient simulation for 10mV (gray) and
100mV (black) input differences
From the timing discussion it can be seen that the
modified latch operates similarly to the original
with the exception of P0, P1 immediately being
turned on to create amplifier structures with N2,
N3 in order to enhance gate-source voltage to N0,
N1. This vgs enhancement is necessary due to the
low supply voltage, and N0, N1 can contribute to
the positive feedback of the latch. Complete
positive feedback starts when P4 or P5 turn on
creating further amplification. This amplified
initial voltage difference causes the latch to
switch at a lower input-referred offset. The
features of high-impedance input and rail-to-rail
output swing have been kept, along with no
parasitic capacitances at the outputs due to N2,
N3 by turning off the load transistors P0 or P1
during regeneration; and no static power
consumption after decision by turning N0, P1, P5
off.
RESULTS - A comparison of the decision
time between the two comparators is shown in
Fig. 6: the original comparator needs 2.95ns at
supply voltage Vco=1.2V, whereas the modified
comparator at the low supply voltage Vco=0.65V
needs only 650ps.
Fig. 6. Decision time of conventional and modified
comparators
On-chip delay-time measurements are shown in
Fig. 7, where input CINN is biased with a
reference voltage, and CINP is a rectangular
signal superimposed by a bias voltage for offset
compensation. For an amplitude of 100mV
(black case) delay time td1 has been measured, for
the amplitude of 10mV (gray case) a larger delay
time td2 has been measured. Mean delay times on
ten chip samples have been determined for the
amplitude CINP=15mV as 93ps at CINN=0.65V
reference voltage, 104ps at CINN=0.6V, and
115ps at CINN=0.55V. The power consumption
was 2.88mW at 5GH (1.2V), 295µW at 1GHz
(0.75V), and 128µW at 0.6 GHz (0.65V).
DISCUSSION
Annema et. al. [1] discussed the additional
problems caused by low supply voltages and gate
leakage that need to be addressed in analog design

5. Fig. 7. Delay-time measurements: CINP=100mV
(black case), 10mV (gray case)
when migrating to UDSM CMOS. At low supply
voltages power consumption will increase if
performance is to be kept or improved. Signal
integrity being proportional to power
consumption, low supply voltages allow for
reduced voltage headroom, signal swing and
biasing, resulting in low SNR and degraded
signal. The process of raising signal integrity will
then increase power consumption. According to
the power/performance relation, the overdrive
voltage for MOS transistors had to be lowered
proportionally to the lowering supply voltages.
Lowering the power consumption therefore has
become a trade-off between signal
integrity/bandwidth and offset/speed. The
numerical results confirm this relation: lower
power consumption at the expense of lower
amplitudes, slower speed and lower bandwidth.
Delay-time measurements also confirm this
relation: reducing power consumption at the
expense of higher delay times/lower reference
voltages, amplitudes, and signal integrity. Gate-
leakage caused mismatch becomes significant,
classical strategies being effective only to a
certain extent, mismatch cancellation techniques
or re-design must be employed to mitigate their
effects. Charge storage concepts do not directly
apply any longer at these dimensions.
To demonstrate the application of the strategies
discussed by [1], Goll, Zimmermann [2]
contrasted the widely used comparator design
migrated to 65-nm process from 0.11-µm
technology. This migration was motivated by the
higher ac performance of MOS transistors,
however dc performance had to be preserved or
improved. The original design featured high-
impedance input, robustness against mismatch,
rail-to-rail output swing and no static power
consumption. The proposed design for 65-nm
process of Fig. 4. had to be re-designed to
accomodate for the low supply voltage of 0.65V
and cope with associated effects. The modified
latch incorporates two paths between the supply
rails, and amplifier pair N4, P4, N5, P5 had to be
added to further amplify the output. This further
amplification was necessary due to low output
swing, and this amplified initial voltage difference
enabled the latch to switch at a lower input-
referred offset. This amplifier pair also modifies
timing by turning transistors P0, P1 on
immediately at the beginning of the comparison
phase. The amplifiers P0, P1, N2, N3 provide vgs
enhancement to N0, N1, that participate in the
positive feedback of the latch. This vgs
enhancement was necessary due to the low supply
voltage, without which not enough gate-source
voltage would be available to transistors N0, N1.
As in the case of the original design, the input
transistors have been kept large to improve gate-
leakage related mismatch. No other mismatch
cancellation techniques have been utilized, as the
comparator has shown a good trade-off between
offset and speed, both in decision and delay time.
The features of high-impedance input and rail-to-
rail output swing have also been kept, along with
no parasitic capacitances at the outputs due to N2,
N3 by turning off the load transistors P0 or P1
during regeneration; also no static power
consumption after decision by turning N0, P1, P5
off.
A strategy discussed was selectively operating

6. certain functional blocks at higher supply
voltages. On-chip delay-time measurements
involved operating the comparator at 1.2V and
0.65V for comparison. During measurements at
low supply voltage, peripheral functional blocks
have still been operating at the high supply
voltage. This was done for comparison, however
the concept can be applied in actual applications.
For the purpose of reducing power consumption,
some necessary parts of the chip may be operated
at a high supply voltage while the critical parts at
the low supply voltage for high performance.
CONCLUSION
It has been stated by [1] that power consumption
of analog circuits is proportional to the level of
signal integrity. When migrating to UDSM
processes, signal integrity needs to be preserved
or improved. In order to lower power
consumption, specific strategies have been
discussed to mitigate the effects of low supply
voltages and significant gate leakage. [2] have
demonstrated these strategies by re-designing a
standard comparator for 65-nm process (.65V).
The operation and timing discussion offered
insights to re-design and strategies in UDSM
CMOS analog design. The results were a
significant increase in speed and reduced power
consumption advocating the discussion by [1] and
design efforts by [2]. The comparator designed
for 0.11-µm/1.2V technology had a decision time
of 2.95ns, offset of 1.9mV and a power
consumption of 2.88mW at 5GHz, whereas the
new comparator at 65-nm/0.65V needed 650ps
decision time at offset of 6.1mV and low delay
time of 93ps, and a power consumption of 128µW
at 0.6GHz. The performance in speed and power
consumption of the new comparator at its offset
are an acceptable trade-off.
REFERENCES
[1] A. J. Annema, B. Nauta, R. V. Langevelde,
H. Tuinhout, “Analog Circuits in Ultra-
Deep- Submicron CMOS,” IEEE Journal
of Solid-State Circuits, vol. 40, no. 1,
pp. 132-143, January 2005.
[2] B. Goll, H. Zimmermann, “A Comparator
With Reduced Delay Time in 65-nm
CMOS for Supply Voltages Down to
0.65 V,” IEEE Transactions On Circuits
And Systems-II: Express Briefs, vol. 56,
no. 11, pp. 810-814, November 2009.
May 5, 2014