To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 µW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 µW while CVSL shows total power consumption of 18.94 µW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
Reconfigurable of current-mode differentiator and integrator based-on current...IJECEIAES
The reconfigurable of the differentiator and integrator based on current conveyor transconductance amplifiers (CCTAs) have been presented in this paper. The proposed configurations are provided with two CCTAs and grounded elements. The configurations can be operated in the differentiator and integrator by selecting external passive elements. The input and output currents have low and high impedances, respectively; therefore, the configurations can be cascaded without additional current buffer. The proposed configurations can be electronically tuned by external direct current (DC) bias currents, and it also has slight fluctuation with temperature. An application of universal filter is demonstrated to confirm the ability of the proposed configurations. The results of simulation with Pspice program are accordance with the theoretical analysis.
A hybrid algorithm for voltage stability enhancement of distribution systems IJECEIAES
This paper presents a hybrid algorithm by applying a hybrid firefly and particle swarm optimization algorithm (HFPSO) to determine the optimal sizing of distributed generation (DG) and distribution static compensator (D-STATCOM) device. A multi-objective function is employed to enhance the voltage stability, voltage profile, and minimize the total power loss of the radial distribution system (RDS). Firstly, the voltage stability index (VSI) is applied to locate the optimal location of DG and D-STATCOM respectively. Secondly, to overcome the sup-optimal operation of existing algorithms, the HFPSO algorithm is utilized to determine the optimal size of both DG and D-STATCOM. Verification of the proposed algorithm has achieved on the standard IEEE 33-bus and Iraqi 65-bus radial distribution systems through simulation using MATLAB. Comprehensive simulation results of four different cases show that the proposed HFPSO demonstrates significant improvements over other existing algorithms in supporting voltage stability and loss reduction in distribution networks. Furthermore, comparisons have achieved to demonstrate the superiority of HFPSO algorithms over other techniques due to its ability to determine the global optimum solution by easy way and speed converge feature.
The impact of channel fin width on electrical characteristics of Si-FinFET IJECEIAES
This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W F =5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applica...ijsrd.com
In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF.
Reconfigurable of current-mode differentiator and integrator based-on current...IJECEIAES
The reconfigurable of the differentiator and integrator based on current conveyor transconductance amplifiers (CCTAs) have been presented in this paper. The proposed configurations are provided with two CCTAs and grounded elements. The configurations can be operated in the differentiator and integrator by selecting external passive elements. The input and output currents have low and high impedances, respectively; therefore, the configurations can be cascaded without additional current buffer. The proposed configurations can be electronically tuned by external direct current (DC) bias currents, and it also has slight fluctuation with temperature. An application of universal filter is demonstrated to confirm the ability of the proposed configurations. The results of simulation with Pspice program are accordance with the theoretical analysis.
A hybrid algorithm for voltage stability enhancement of distribution systems IJECEIAES
This paper presents a hybrid algorithm by applying a hybrid firefly and particle swarm optimization algorithm (HFPSO) to determine the optimal sizing of distributed generation (DG) and distribution static compensator (D-STATCOM) device. A multi-objective function is employed to enhance the voltage stability, voltage profile, and minimize the total power loss of the radial distribution system (RDS). Firstly, the voltage stability index (VSI) is applied to locate the optimal location of DG and D-STATCOM respectively. Secondly, to overcome the sup-optimal operation of existing algorithms, the HFPSO algorithm is utilized to determine the optimal size of both DG and D-STATCOM. Verification of the proposed algorithm has achieved on the standard IEEE 33-bus and Iraqi 65-bus radial distribution systems through simulation using MATLAB. Comprehensive simulation results of four different cases show that the proposed HFPSO demonstrates significant improvements over other existing algorithms in supporting voltage stability and loss reduction in distribution networks. Furthermore, comparisons have achieved to demonstrate the superiority of HFPSO algorithms over other techniques due to its ability to determine the global optimum solution by easy way and speed converge feature.
The impact of channel fin width on electrical characteristics of Si-FinFET IJECEIAES
This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W F =5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applica...ijsrd.com
In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Novel technique in charactarizing a pv module using pulse width modulatoreSAT Journals
Abstract The fabrication and characterization of PV modules are always done under standard test conditions (STC). However, The condition of operation are often far from thisstandard conditions. As a result, developing a characterization circuit is considered as a point of interest for researchers.This paper presents a new methodology in characterizing a PV module using an electronic load circuit. The circuit is implemented using a power MOSFET driven by a pulse width modulator (PWM) developed by LABVIEW. The system is tested and its results are validated by comparing it with simulation results performed by Comsol Multiphysics and Matlab. The system shows high accuracy with respect to the previous published work with lower cost and higher simplicity. Keywords: Photovoltaic, Characterization, Electronic load, and Pulse width modulation (PWM)…
Low Power Full Adder using 9T Structureidescitation
In this paper, we propose a new 9T 1-bit full adder.
The main objective is full output voltage swing, low power
consumption and temperature sustainability. The proposed
design is more reliable in terms of power consumption, Power
Delay Product (PDP) and temperature sustainability as
compared to the existing full adder designs. The design has
been implemented 45nm technology on Tanner EDA Tool
version 13.0. The simulation results demonstrate the power
consumption, delay and power delay product at different input
voltages ranging 0.4V to 1.4V.
This work compacts with the modeling, simulation, and application of a Fractional Order Proportional Integral Differential (FOP-I-D) controlled Cascaded Flyback Switched Mode Power Supply (CFSMPS) system. It recommends Parallel cascaded flyback converter for the production of essential DC voltage from the input supply voltage. The output from CFSMPS is regulated by using closed loop configuration. The simulation of Closed-loop Proportional-Integral (PI) and FOP-I-D controlled CFSMPS system has been done and the results of the systems are related. The outcomes signify that the FOP-I-D based system has presented an enhanced response to represent as similar to the PI controlled CFSMPS system. The FOP-I-D controlled CFSMPS system has benefits like decreased steady-state error and enhanced time-domain response.
Compensator Based Performance Enhancement Strategy for a SIQO Buck ConverterIAES-IJPEDS
This paper attempts to design lag and lag-lead compensators for improving the performance of a Single Inductor Quad Output (SIQO) dc-dc buck converter in terms of time domain and frequency domain specifications. It develops the state space averaged model to find the duty ratio of the desired output voltages at steady state. The exercise arrives at the transfer function model from the state space averaged model through the use of its lumped small signal equivalent circuit which allows analyzing the performance of the system in frequency and time domains.The responses are derived in the MATLAB/Simulink® using discrete components incorporating compensators of the converter. The hardware results obtained using Data Acquisition Module DT9834® interfaced to MATLAB/Simulink® and prototype model establish the performance of the compensator based converter and further emphasize its ability to minimize the ripples over a range of operating loads.
Real Coded Genetic Algorithm Based Improvement of Efficiency in Interleaved B...IJPEDS-IAES
The reliability, efficiency, and controllability of Photo Voltaic power systems can be increased by embedding the components of a Boost Converter. Currently, the converter technology overcomes the main problems of manufacturing cost, efficiency and mass production. Issue to limit the life span of a Photo Voltaic inverter is the huge electrolytic capacitor across the Direct Current bus for energy decoupling. This paper presents a two-phase interleaved boost converter which ensures 180 angle phase shift between the two interleaved converters. The Proportional Integral controller is used to reshape that the controller attempts to minimize the error by adjusting the control inputs and also real coded genetic algorithm is proposed for tuning of controlling parameters of Proportional Integral controller. The real coded genetic algorithm is applied in the Interleaved Boost Converter with Advanced Pulse Width Modulation Techniques for improving the results of efficiency and reduction of ripple current. Simulation results illustrate the improvement of efficiency and the diminution of ripple current.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
BPSK Modulation and Demodulation with Power Line Carrier Communication and GS...IAES-IJPEDS
GSM/GPRS and PLC communication are used for Automatic Meter Reading
(AMR) applications. These AMR systems have made substantial progress
over the recent years in terms of functionality, scalability, performance
and openness such that they can perform remote metering applications for
very demanding and complex systems. By using BPSK (Binary Phase Shift
Keying) modulation with Power Line Carrier Communication, Smart
Metering can be done in Rural Smart Micro-grids. The design
and Simulation of BPSK Modulation and Demodulation are successfully
done by using MATLAB/Simulink software. The advantages of using BPSK
modulation over the QPSK modulation and the advantages of PLC
Communication over the GSM Communication is identified in this paper.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Novel technique in charactarizing a pv module using pulse width modulatoreSAT Journals
Abstract The fabrication and characterization of PV modules are always done under standard test conditions (STC). However, The condition of operation are often far from thisstandard conditions. As a result, developing a characterization circuit is considered as a point of interest for researchers.This paper presents a new methodology in characterizing a PV module using an electronic load circuit. The circuit is implemented using a power MOSFET driven by a pulse width modulator (PWM) developed by LABVIEW. The system is tested and its results are validated by comparing it with simulation results performed by Comsol Multiphysics and Matlab. The system shows high accuracy with respect to the previous published work with lower cost and higher simplicity. Keywords: Photovoltaic, Characterization, Electronic load, and Pulse width modulation (PWM)…
Low Power Full Adder using 9T Structureidescitation
In this paper, we propose a new 9T 1-bit full adder.
The main objective is full output voltage swing, low power
consumption and temperature sustainability. The proposed
design is more reliable in terms of power consumption, Power
Delay Product (PDP) and temperature sustainability as
compared to the existing full adder designs. The design has
been implemented 45nm technology on Tanner EDA Tool
version 13.0. The simulation results demonstrate the power
consumption, delay and power delay product at different input
voltages ranging 0.4V to 1.4V.
This work compacts with the modeling, simulation, and application of a Fractional Order Proportional Integral Differential (FOP-I-D) controlled Cascaded Flyback Switched Mode Power Supply (CFSMPS) system. It recommends Parallel cascaded flyback converter for the production of essential DC voltage from the input supply voltage. The output from CFSMPS is regulated by using closed loop configuration. The simulation of Closed-loop Proportional-Integral (PI) and FOP-I-D controlled CFSMPS system has been done and the results of the systems are related. The outcomes signify that the FOP-I-D based system has presented an enhanced response to represent as similar to the PI controlled CFSMPS system. The FOP-I-D controlled CFSMPS system has benefits like decreased steady-state error and enhanced time-domain response.
Compensator Based Performance Enhancement Strategy for a SIQO Buck ConverterIAES-IJPEDS
This paper attempts to design lag and lag-lead compensators for improving the performance of a Single Inductor Quad Output (SIQO) dc-dc buck converter in terms of time domain and frequency domain specifications. It develops the state space averaged model to find the duty ratio of the desired output voltages at steady state. The exercise arrives at the transfer function model from the state space averaged model through the use of its lumped small signal equivalent circuit which allows analyzing the performance of the system in frequency and time domains.The responses are derived in the MATLAB/Simulink® using discrete components incorporating compensators of the converter. The hardware results obtained using Data Acquisition Module DT9834® interfaced to MATLAB/Simulink® and prototype model establish the performance of the compensator based converter and further emphasize its ability to minimize the ripples over a range of operating loads.
Real Coded Genetic Algorithm Based Improvement of Efficiency in Interleaved B...IJPEDS-IAES
The reliability, efficiency, and controllability of Photo Voltaic power systems can be increased by embedding the components of a Boost Converter. Currently, the converter technology overcomes the main problems of manufacturing cost, efficiency and mass production. Issue to limit the life span of a Photo Voltaic inverter is the huge electrolytic capacitor across the Direct Current bus for energy decoupling. This paper presents a two-phase interleaved boost converter which ensures 180 angle phase shift between the two interleaved converters. The Proportional Integral controller is used to reshape that the controller attempts to minimize the error by adjusting the control inputs and also real coded genetic algorithm is proposed for tuning of controlling parameters of Proportional Integral controller. The real coded genetic algorithm is applied in the Interleaved Boost Converter with Advanced Pulse Width Modulation Techniques for improving the results of efficiency and reduction of ripple current. Simulation results illustrate the improvement of efficiency and the diminution of ripple current.
Implementation of Full Adder Cell Using High Performance CMOS Technologyijsrd.com
This paper proposed design and implementation of full adder cell which is efficient in terms of both speed and energy consumption which becomes even more significant as the world length of the adder increases. We are introducing adders for low power imprecise applications. In this we propose a full adder design having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. We will explain how to realize a general full adder circuit based on transistor using CMOS technology. The performance of the proposed full adder is evaluated by the comparison of the simulation result. In this system, not signals are generated internally that control the selection of the output multiplexers. Instead, the input signal, exhibiting a full voltage swing and no extra delay, is used to drive the multiplexers, reducing the overall propagation delays. The capacitive load for the input has been reduced, as it is connected only to some transistor gates and some drain or source terminals. The design a full adder having low complexity, higher computing speed, lower energy consumption, and lower operating voltage. Full Adder models to make it understandable for designer. We are giving high throughput with less complex system by showing synthesizable and simulated results.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
BPSK Modulation and Demodulation with Power Line Carrier Communication and GS...IAES-IJPEDS
GSM/GPRS and PLC communication are used for Automatic Meter Reading
(AMR) applications. These AMR systems have made substantial progress
over the recent years in terms of functionality, scalability, performance
and openness such that they can perform remote metering applications for
very demanding and complex systems. By using BPSK (Binary Phase Shift
Keying) modulation with Power Line Carrier Communication, Smart
Metering can be done in Rural Smart Micro-grids. The design
and Simulation of BPSK Modulation and Demodulation are successfully
done by using MATLAB/Simulink software. The advantages of using BPSK
modulation over the QPSK modulation and the advantages of PLC
Communication over the GSM Communication is identified in this paper.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators. The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. To implement power efficient and high performance analog-to-digital converters the designers are urged to design an optimized dual tail comparator. In this paper, It is shown that in the proposed dual tail comparator both the power and delay time is significantly reduced.
A power efficient delta-sigma ADC with series-bilinear switch capacitor volta...TELKOMNIKA JOURNAL
In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study and implementation of comparator in cmos 50 nm technologyeSAT Journals
Abstract This paper describes the comparator circuits used in FLASH Analog to digital converter (ADC). The performance of FLASH ADC is greatly influenced by the choice of comparator. In this paper, first a single ended “Threshold Inverter Quantizer” (TIQ) is presented. The TIQ comparator is based on a CMOS inverter cell, in which voltage transfer characteristics (VTC) are changed by systematic transistor sizing. However, TIQ comparator is very sensitive to power supply noise. Another comparator circuit presented in this paper is “Two stage open loop comparator”. It is implemented in 50 nm CMOS Technology. Pre-simulation of comparator is done in LT-Spice and post layout simulation is done in Microwind 3.1. Keywords: CMOS, Comparator, TIQ (Threshold Inverter Quantizer), LT-Spice.
ANALYSIS AND DESIGN OF DOUBLE TAIL COMPARATOR USING A LOW POWER GATING TECHNI...RK CONSULTANCY SERVICES
Comparator techniques are the basic elements of designing the modern Analog and varied mixed signals systems. The speed and area is the main factors of high speed applications. Various types of dynamic double tail comparators is compared to an in terms of Delay, Area, Power, Glitches, Speed and average times. The accuracy of comparators is mainly defined by power consumption and speed. The comparators are mainly achieving by the overall higher performance of ADC. The High speed comparator is fully suffered from low voltage supply. Threshold voltage devices are not scaled at the same times, as the supply voltage of the devices. In modern CMOS technologies the double tail comparator is designed by a using the dynamic method it mainly reduces the power and voltages. The analytical expression methods it can obtain an intuitions about the contributors, comparators delay and explore the trade off dynamic comparator designs.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
This paper proposes the grid application of modified three-phase topology of Modular Multilevel Converter (MMC) using finite-control-set predictive control. This topology has reduced number of switch counts compared to the conventional MMC, eliminates the problem of circulating current and having higher efficiency. A single dc source is required to produce sinusoidal outputs. The number of sub-modules (SMs) in this topology is half of the SMs required in case of MMC, in addition to a single H-bride circuit per phase. The finite-control-set predictive current control scheme for the grid connected dc source through the Hybrid Modular Multilevel Converter (HMMC). This controller controls the desired real and reactive power demand of the grid instantaneously. The simulation study of a three phase grid connected system has been done in Matlab/Simulink and the results are provided for the different real and reactive power demands, to validate the concepts.
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
Adiabatic describe the thermodynamic processes in which there is no energy exchange with the environment, and therefore very less dissipated energy loss. These circuits are low power circuits which use reversible logic to conserve energy. Adiabatic logic works with the concept of switching activities which reduces the power by giving stored energy back to the supply. The main design changes are focused on power clock which plays the vital role in the principle of operation. This has been used because many adiabaticcircuits use a combined power supply and clock, or a power clock (Four Phase).To achieve this, the power supply of adiabatic logic circuits have used time varying voltage charging signal, in contrast to traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply. Thereby the circuit topology and operation of the circuit has been changed so that the source current of CMOS transistor change its direction and goes back to the supply(Recovery) when the power clock falls from VDD to zero. Power efficient blocks can be designed by using adiabatic logic which can be used in combinational and sequential circuits. The simulation of the designs is done using a backend tool called MENTOR GRAPHICS in 130nm technology
Cmos Full Adder and Multiplexer Based Encoder for Low Resolution Flash AdcIOSRJECE
The present investigation proposed a low power encoding scheme of thermometer code to binary code converter for flash analog to digital conversion by the design of different circuits. In this paper, we have proposed three encoding techniques for the conversion of analog to digital signal using Multiplexer based encoder, heterogeneous encoder and encoding technique using dynamic logic circuits providing low power of operation and we compare the results obtained from each technique based on power consumption. The multiplexer based encoder was designed with the help of multiplexers which consumes less amount of power comparing with other designs.
High-efficiency 2.45 and 5.8 GHz dual-band rectifier design with modulated in...IJECEIAES
This paper presents a new rectifier design for radio frequency (RF) energy harvesting by adopting a particular circuit topology to achieve two objectives at the same time. First, work with modulated input signal sources instead of only continuous waveform (CW) signals. Second, operate with a wide input power range using the Wilkinson power divider (WPD) and two different rectifier diodes (HSMS2852 and SMS7630) instead of using active components. According to the comparison with dual-band rectifiers presented in the literature, the designed rectifier is a high-efficiency rectifier for wide RF power input ranges. A peak of 67.041% and 49.089% was reached for 2.45 and 5.8 GHz, respectively, for CW as the input signal. An efficiency of 72.325% and 45.935% is obtained with a 16 QAM modulated input signal for the operating frequencies, respectively, 69.979% and 54.579% for 8PSK. The results obtained demonstrate that energy recovery systems can use modulated signals. Therefore, the use of a modulated signal over a CW signal may have additional benefits.
Similar to Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques (20)
Bibliometric analysis highlighting the role of women in addressing climate ch...IJECEIAES
Fossil fuel consumption increased quickly, contributing to climate change
that is evident in unusual flooding and draughts, and global warming. Over
the past ten years, women's involvement in society has grown dramatically,
and they succeeded in playing a noticeable role in reducing climate change.
A bibliometric analysis of data from the last ten years has been carried out to
examine the role of women in addressing the climate change. The analysis's
findings discussed the relevant to the sustainable development goals (SDGs),
particularly SDG 7 and SDG 13. The results considered contributions made
by women in the various sectors while taking geographic dispersion into
account. The bibliometric analysis delves into topics including women's
leadership in environmental groups, their involvement in policymaking, their
contributions to sustainable development projects, and the influence of
gender diversity on attempts to mitigate climate change. This study's results
highlight how women have influenced policies and actions related to climate
change, point out areas of research deficiency and recommendations on how
to increase role of the women in addressing the climate change and
achieving sustainability. To achieve more successful results, this initiative
aims to highlight the significance of gender equality and encourage
inclusivity in climate change decision-making processes.
Voltage and frequency control of microgrid in presence of micro-turbine inter...IJECEIAES
The active and reactive load changes have a significant impact on voltage
and frequency. In this paper, in order to stabilize the microgrid (MG) against
load variations in islanding mode, the active and reactive power of all
distributed generators (DGs), including energy storage (battery), diesel
generator, and micro-turbine, are controlled. The micro-turbine generator is
connected to MG through a three-phase to three-phase matrix converter, and
the droop control method is applied for controlling the voltage and
frequency of MG. In addition, a method is introduced for voltage and
frequency control of micro-turbines in the transition state from gridconnected mode to islanding mode. A novel switching strategy of the matrix
converter is used for converting the high-frequency output voltage of the
micro-turbine to the grid-side frequency of the utility system. Moreover,
using the switching strategy, the low-order harmonics in the output current
and voltage are not produced, and consequently, the size of the output filter
would be reduced. In fact, the suggested control strategy is load-independent
and has no frequency conversion restrictions. The proposed approach for
voltage and frequency regulation demonstrates exceptional performance and
favorable response across various load alteration scenarios. The suggested
strategy is examined in several scenarios in the MG test systems, and the
simulation results are addressed.
Enhancing battery system identification: nonlinear autoregressive modeling fo...IJECEIAES
Precisely characterizing Li-ion batteries is essential for optimizing their
performance, enhancing safety, and prolonging their lifespan across various
applications, such as electric vehicles and renewable energy systems. This
article introduces an innovative nonlinear methodology for system
identification of a Li-ion battery, employing a nonlinear autoregressive with
exogenous inputs (NARX) model. The proposed approach integrates the
benefits of nonlinear modeling with the adaptability of the NARX structure,
facilitating a more comprehensive representation of the intricate
electrochemical processes within the battery. Experimental data collected
from a Li-ion battery operating under diverse scenarios are employed to
validate the effectiveness of the proposed methodology. The identified
NARX model exhibits superior accuracy in predicting the battery's behavior
compared to traditional linear models. This study underscores the
importance of accounting for nonlinearities in battery modeling, providing
insights into the intricate relationships between state-of-charge, voltage, and
current under dynamic conditions.
Smart grid deployment: from a bibliometric analysis to a surveyIJECEIAES
Smart grids are one of the last decades' innovations in electrical energy.
They bring relevant advantages compared to the traditional grid and
significant interest from the research community. Assessing the field's
evolution is essential to propose guidelines for facing new and future smart
grid challenges. In addition, knowing the main technologies involved in the
deployment of smart grids (SGs) is important to highlight possible
shortcomings that can be mitigated by developing new tools. This paper
contributes to the research trends mentioned above by focusing on two
objectives. First, a bibliometric analysis is presented to give an overview of
the current research level about smart grid deployment. Second, a survey of
the main technological approaches used for smart grid implementation and
their contributions are highlighted. To that effect, we searched the Web of
Science (WoS), and the Scopus databases. We obtained 5,663 documents
from WoS and 7,215 from Scopus on smart grid implementation or
deployment. With the extraction limitation in the Scopus database, 5,872 of
the 7,215 documents were extracted using a multi-step process. These two
datasets have been analyzed using a bibliometric tool called bibliometrix.
The main outputs are presented with some recommendations for future
research.
Use of analytical hierarchy process for selecting and prioritizing islanding ...IJECEIAES
One of the problems that are associated to power systems is islanding
condition, which must be rapidly and properly detected to prevent any
negative consequences on the system's protection, stability, and security.
This paper offers a thorough overview of several islanding detection
strategies, which are divided into two categories: classic approaches,
including local and remote approaches, and modern techniques, including
techniques based on signal processing and computational intelligence.
Additionally, each approach is compared and assessed based on several
factors, including implementation costs, non-detected zones, declining
power quality, and response times using the analytical hierarchy process
(AHP). The multi-criteria decision-making analysis shows that the overall
weight of passive methods (24.7%), active methods (7.8%), hybrid methods
(5.6%), remote methods (14.5%), signal processing-based methods (26.6%),
and computational intelligent-based methods (20.8%) based on the
comparison of all criteria together. Thus, it can be seen from the total weight
that hybrid approaches are the least suitable to be chosen, while signal
processing-based methods are the most appropriate islanding detection
method to be selected and implemented in power system with respect to the
aforementioned factors. Using Expert Choice software, the proposed
hierarchy model is studied and examined.
Enhancing of single-stage grid-connected photovoltaic system using fuzzy logi...IJECEIAES
The power generated by photovoltaic (PV) systems is influenced by
environmental factors. This variability hampers the control and utilization of
solar cells' peak output. In this study, a single-stage grid-connected PV
system is designed to enhance power quality. Our approach employs fuzzy
logic in the direct power control (DPC) of a three-phase voltage source
inverter (VSI), enabling seamless integration of the PV connected to the
grid. Additionally, a fuzzy logic-based maximum power point tracking
(MPPT) controller is adopted, which outperforms traditional methods like
incremental conductance (INC) in enhancing solar cell efficiency and
minimizing the response time. Moreover, the inverter's real-time active and
reactive power is directly managed to achieve a unity power factor (UPF).
The system's performance is assessed through MATLAB/Simulink
implementation, showing marked improvement over conventional methods,
particularly in steady-state and varying weather conditions. For solar
irradiances of 500 and 1,000 W/m2
, the results show that the proposed
method reduces the total harmonic distortion (THD) of the injected current
to the grid by approximately 46% and 38% compared to conventional
methods, respectively. Furthermore, we compare the simulation results with
IEEE standards to evaluate the system's grid compatibility.
Enhancing photovoltaic system maximum power point tracking with fuzzy logic-b...IJECEIAES
Photovoltaic systems have emerged as a promising energy resource that
caters to the future needs of society, owing to their renewable, inexhaustible,
and cost-free nature. The power output of these systems relies on solar cell
radiation and temperature. In order to mitigate the dependence on
atmospheric conditions and enhance power tracking, a conventional
approach has been improved by integrating various methods. To optimize
the generation of electricity from solar systems, the maximum power point
tracking (MPPT) technique is employed. To overcome limitations such as
steady-state voltage oscillations and improve transient response, two
traditional MPPT methods, namely fuzzy logic controller (FLC) and perturb
and observe (P&O), have been modified. This research paper aims to
simulate and validate the step size of the proposed modified P&O and FLC
techniques within the MPPT algorithm using MATLAB/Simulink for
efficient power tracking in photovoltaic systems.
Adaptive synchronous sliding control for a robot manipulator based on neural ...IJECEIAES
Robot manipulators have become important equipment in production lines, medical fields, and transportation. Improving the quality of trajectory tracking for
robot hands is always an attractive topic in the research community. This is a
challenging problem because robot manipulators are complex nonlinear systems
and are often subject to fluctuations in loads and external disturbances. This
article proposes an adaptive synchronous sliding control scheme to improve trajectory tracking performance for a robot manipulator. The proposed controller
ensures that the positions of the joints track the desired trajectory, synchronize
the errors, and significantly reduces chattering. First, the synchronous tracking
errors and synchronous sliding surfaces are presented. Second, the synchronous
tracking error dynamics are determined. Third, a robust adaptive control law is
designed,the unknown components of the model are estimated online by the neural network, and the parameters of the switching elements are selected by fuzzy
logic. The built algorithm ensures that the tracking and approximation errors
are ultimately uniformly bounded (UUB). Finally, the effectiveness of the constructed algorithm is demonstrated through simulation and experimental results.
Simulation and experimental results show that the proposed controller is effective with small synchronous tracking errors, and the chattering phenomenon is
significantly reduced.
Remote field-programmable gate array laboratory for signal acquisition and de...IJECEIAES
A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embeddedsystem design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.
Detecting and resolving feature envy through automated machine learning and m...IJECEIAES
Efficiently identifying and resolving code smells enhances software project quality. This paper presents a novel solution, utilizing automated machine learning (AutoML) techniques, to detect code smells and apply move method refactoring. By evaluating code metrics before and after refactoring, we assessed its impact on coupling, complexity, and cohesion. Key contributions of this research include a unique dataset for code smell classification and the development of models using AutoGluon for optimal performance. Furthermore, the study identifies the top 20 influential features in classifying feature envy, a well-known code smell, stemming from excessive reliance on external classes. We also explored how move method refactoring addresses feature envy, revealing reduced coupling and complexity, and improved cohesion, ultimately enhancing code quality. In summary, this research offers an empirical, data-driven approach, integrating AutoML and move method refactoring to optimize software project quality. Insights gained shed light on the benefits of refactoring on code quality and the significance of specific features in detecting feature envy. Future research can expand to explore additional refactoring techniques and a broader range of code metrics, advancing software engineering practices and standards.
Smart monitoring technique for solar cell systems using internet of things ba...IJECEIAES
Rapidly and remotely monitoring and receiving the solar cell systems status parameters, solar irradiance, temperature, and humidity, are critical issues in enhancement their efficiency. Hence, in the present article an improved smart prototype of internet of things (IoT) technique based on embedded system through NodeMCU ESP8266 (ESP-12E) was carried out experimentally. Three different regions at Egypt; Luxor, Cairo, and El-Beheira cities were chosen to study their solar irradiance profile, temperature, and humidity by the proposed IoT system. The monitoring data of solar irradiance, temperature, and humidity were live visualized directly by Ubidots through hypertext transfer protocol (HTTP) protocol. The measured solar power radiation in Luxor, Cairo, and El-Beheira ranged between 216-1000, 245-958, and 187-692 W/m 2 respectively during the solar day. The accuracy and rapidity of obtaining monitoring results using the proposed IoT system made it a strong candidate for application in monitoring solar cell systems. On the other hand, the obtained solar power radiation results of the three considered regions strongly candidate Luxor and Cairo as suitable places to build up a solar cells system station rather than El-Beheira.
An efficient security framework for intrusion detection and prevention in int...IJECEIAES
Over the past few years, the internet of things (IoT) has advanced to connect billions of smart devices to improve quality of life. However, anomalies or malicious intrusions pose several security loopholes, leading to performance degradation and threat to data security in IoT operations. Thereby, IoT security systems must keep an eye on and restrict unwanted events from occurring in the IoT network. Recently, various technical solutions based on machine learning (ML) models have been derived towards identifying and restricting unwanted events in IoT. However, most ML-based approaches are prone to miss-classification due to inappropriate feature selection. Additionally, most ML approaches applied to intrusion detection and prevention consider supervised learning, which requires a large amount of labeled data to be trained. Consequently, such complex datasets are impossible to source in a large network like IoT. To address this problem, this proposed study introduces an efficient learning mechanism to strengthen the IoT security aspects. The proposed algorithm incorporates supervised and unsupervised approaches to improve the learning models for intrusion detection and mitigation. Compared with the related works, the experimental outcome shows that the model performs well in a benchmark dataset. It accomplishes an improved detection accuracy of approximately 99.21%.
Developing a smart system for infant incubators using the internet of things ...IJECEIAES
This research is developing an incubator system that integrates the internet of things and artificial intelligence to improve care for premature babies. The system workflow starts with sensors that collect data from the incubator. Then, the data is sent in real-time to the internet of things (IoT) broker eclipse mosquito using the message queue telemetry transport (MQTT) protocol version 5.0. After that, the data is stored in a database for analysis using the long short-term memory network (LSTM) method and displayed in a web application using an application programming interface (API) service. Furthermore, the experimental results produce as many as 2,880 rows of data stored in the database. The correlation coefficient between the target attribute and other attributes ranges from 0.23 to 0.48. Next, several experiments were conducted to evaluate the model-predicted value on the test data. The best results are obtained using a two-layer LSTM configuration model, each with 60 neurons and a lookback setting 6. This model produces an R 2 value of 0.934, with a root mean square error (RMSE) value of 0.015 and a mean absolute error (MAE) of 0.008. In addition, the R 2 value was also evaluated for each attribute used as input, with a result of values between 0.590 and 0.845.
A review on internet of things-based stingless bee's honey production with im...IJECEIAES
Honey is produced exclusively by honeybees and stingless bees which both are well adapted to tropical and subtropical regions such as Malaysia. Stingless bees are known for producing small amounts of honey and are known for having a unique flavor profile. Problem identified that many stingless bees collapsed due to weather, temperature and environment. It is critical to understand the relationship between the production of stingless bee honey and environmental conditions to improve honey production. Thus, this paper presents a review on stingless bee's honey production and prediction modeling. About 54 previous research has been analyzed and compared in identifying the research gaps. A framework on modeling the prediction of stingless bee honey is derived. The result presents the comparison and analysis on the internet of things (IoT) monitoring systems, honey production estimation, convolution neural networks (CNNs), and automatic identification methods on bee species. It is identified based on image detection method the top best three efficiency presents CNN is at 98.67%, densely connected convolutional networks with YOLO v3 is 97.7%, and DenseNet201 convolutional networks 99.81%. This study is significant to assist the researcher in developing a model for predicting stingless honey produced by bee's output, which is important for a stable economy and food security.
A trust based secure access control using authentication mechanism for intero...IJECEIAES
The internet of things (IoT) is a revolutionary innovation in many aspects of our society including interactions, financial activity, and global security such as the military and battlefield internet. Due to the limited energy and processing capacity of network devices, security, energy consumption, compatibility, and device heterogeneity are the long-term IoT problems. As a result, energy and security are critical for data transmission across edge and IoT networks. Existing IoT interoperability techniques need more computation time, have unreliable authentication mechanisms that break easily, lose data easily, and have low confidentiality. In this paper, a key agreement protocol-based authentication mechanism for IoT devices is offered as a solution to this issue. This system makes use of information exchange, which must be secured to prevent access by unauthorized users. Using a compact contiki/cooja simulator, the performance and design of the suggested framework are validated. The simulation findings are evaluated based on detection of malicious nodes after 60 minutes of simulation. The suggested trust method, which is based on privacy access control, reduced packet loss ratio to 0.32%, consumed 0.39% power, and had the greatest average residual energy of 0.99 mJoules at 10 nodes.
Fuzzy linear programming with the intuitionistic polygonal fuzzy numbersIJECEIAES
In real world applications, data are subject to ambiguity due to several factors; fuzzy sets and fuzzy numbers propose a great tool to model such ambiguity. In case of hesitation, the complement of a membership value in fuzzy numbers can be different from the non-membership value, in which case we can model using intuitionistic fuzzy numbers as they provide flexibility by defining both a membership and a non-membership functions. In this article, we consider the intuitionistic fuzzy linear programming problem with intuitionistic polygonal fuzzy numbers, which is a generalization of the previous polygonal fuzzy numbers found in the literature. We present a modification of the simplex method that can be used to solve any general intuitionistic fuzzy linear programming problem after approximating the problem by an intuitionistic polygonal fuzzy number with n edges. This method is given in a simple tableau formulation, and then applied on numerical examples for clarity.
The performance of artificial intelligence in prostate magnetic resonance im...IJECEIAES
Prostate cancer is the predominant form of cancer observed in men worldwide. The application of magnetic resonance imaging (MRI) as a guidance tool for conducting biopsies has been established as a reliable and well-established approach in the diagnosis of prostate cancer. The diagnostic performance of MRI-guided prostate cancer diagnosis exhibits significant heterogeneity due to the intricate and multi-step nature of the diagnostic pathway. The development of artificial intelligence (AI) models, specifically through the utilization of machine learning techniques such as deep learning, is assuming an increasingly significant role in the field of radiology. In the realm of prostate MRI, a considerable body of literature has been dedicated to the development of various AI algorithms. These algorithms have been specifically designed for tasks such as prostate segmentation, lesion identification, and classification. The overarching objective of these endeavors is to enhance diagnostic performance and foster greater agreement among different observers within MRI scans for the prostate. This review article aims to provide a concise overview of the application of AI in the field of radiology, with a specific focus on its utilization in prostate MRI.
Seizure stage detection of epileptic seizure using convolutional neural networksIJECEIAES
According to the World Health Organization (WHO), seventy million individuals worldwide suffer from epilepsy, a neurological disorder. While electroencephalography (EEG) is crucial for diagnosing epilepsy and monitoring the brain activity of epilepsy patients, it requires a specialist to examine all EEG recordings to find epileptic behavior. This procedure needs an experienced doctor, and a precise epilepsy diagnosis is crucial for appropriate treatment. To identify epileptic seizures, this study employed a convolutional neural network (CNN) based on raw scalp EEG signals to discriminate between preictal, ictal, postictal, and interictal segments. The possibility of these characteristics is explored by examining how well timedomain signals work in the detection of epileptic signals using intracranial Freiburg Hospital (FH), scalp Children's Hospital Boston-Massachusetts Institute of Technology (CHB-MIT) databases, and Temple University Hospital (TUH) EEG. To test the viability of this approach, two types of experiments were carried out. Firstly, binary class classification (preictal, ictal, postictal each versus interictal) and four-class classification (interictal versus preictal versus ictal versus postictal). The average accuracy for stage detection using CHB-MIT database was 84.4%, while the Freiburg database's time-domain signals had an accuracy of 79.7% and the highest accuracy of 94.02% for classification in the TUH EEG database when comparing interictal stage to preictal stage.
Analysis of driving style using self-organizing maps to analyze driver behaviorIJECEIAES
Modern life is strongly associated with the use of cars, but the increase in acceleration speeds and their maneuverability leads to a dangerous driving style for some drivers. In these conditions, the development of a method that allows you to track the behavior of the driver is relevant. The article provides an overview of existing methods and models for assessing the functioning of motor vehicles and driver behavior. Based on this, a combined algorithm for recognizing driving style is proposed. To do this, a set of input data was formed, including 20 descriptive features: About the environment, the driver's behavior and the characteristics of the functioning of the car, collected using OBD II. The generated data set is sent to the Kohonen network, where clustering is performed according to driving style and degree of danger. Getting the driving characteristics into a particular cluster allows you to switch to the private indicators of an individual driver and considering individual driving characteristics. The application of the method allows you to identify potentially dangerous driving styles that can prevent accidents.
Hyperspectral object classification using hybrid spectral-spatial fusion and ...IJECEIAES
Because of its spectral-spatial and temporal resolution of greater areas, hyperspectral imaging (HSI) has found widespread application in the field of object classification. The HSI is typically used to accurately determine an object's physical characteristics as well as to locate related objects with appropriate spectral fingerprints. As a result, the HSI has been extensively applied to object identification in several fields, including surveillance, agricultural monitoring, environmental research, and precision agriculture. However, because of their enormous size, objects require a lot of time to classify; for this reason, both spectral and spatial feature fusion have been completed. The existing classification strategy leads to increased misclassification, and the feature fusion method is unable to preserve semantic object inherent features; This study addresses the research difficulties by introducing a hybrid spectral-spatial fusion (HSSF) technique to minimize feature size while maintaining object intrinsic qualities; Lastly, a soft-margins kernel is proposed for multi-layer deep support vector machine (MLDSVM) to reduce misclassification. The standard Indian pines dataset is used for the experiment, and the outcome demonstrates that the HSSF-MLDSVM model performs substantially better in terms of accuracy and Kappa coefficient.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
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2. Int J Elec & Comp Eng ISSN: 2088-8708
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction ... (Anil Khatak)
4923
domain [12], [13]. So, in order to counter this regenerative comparator is designed by incorporating different
power reduction techniques such that it can comply with the device designer’s requisites.
Three different power reduction techniques are employed on regenerative comparator [13] in order
to drop its power consumption level so that it can be employed for designing high performance circuits with
marginal power consumption. Initially regenerative comparator is design with pseudo NMOS technology
with load circuit used as grounded PMOS transistor [14]. After that CVSL (cascode voltage switch
logic)/DCVS (differential cascode voltage switch) technology is used on regenerative comparator. CVSL
technique certainly improves parameters like circuit delay, power dissipation. One more point which makes
this technique more applicable is that the digital circuits can be easily structured on the basis of tabular
methods and Karnaugh maps (K-maps) [15]. Third power reduction technique is power gating that
substantially reduces the power consumption of regenerative comparator. Power gating technique provides a
mechanism through gating device that save static leakage power [16]. Nano scale circuits are very subtle to
temperature variations so temperature variations are also noted for these comparators [17].
The further arrangement of article is as follows. Segment 2 provides a hasty overview of the circuit
description along with different power reduction techniques. Section 3 provides details about the simulations,
analysis of power dissipation and temperature variation for different power reduction techniques following
comparison with conventional comparators in segment 4 with conclusion & references in the end.
2. DIFFERENT POWER REDUCTION TECHNIQUES
2.1. Regenerative Comparator in CMOS Technology
Figure 1 depicts the architecture for regenerative comparator in CMOS technology. The input is a
differential pair amplifier which cosists mos devices. These devices are kept in feeble inversion state that
amplifies the input difference signal. Positive feedbeck & regeneration are employed in the second stage &
they became active when reset point is initiated with low signal and thus difference signal is transformed to
VDD & VSS accordingly as final digital output [13]. This comparator architecture easily incorporates large
signals due to high input common-mode range. An ON & OFF chip current source utilized in this schematic
provides additional functionalities with which current can be modified for various sampling frequencies.
Inputs are given through transistor T1, T2 and lower rail of MOS transistors are used for biasing purpose.
Two NOR gates are used at end of the schematic which are latched together to provide regenerative feedback
at the output that enhances the speed of this comparator.
Figure 1. Regenerative Comparator in CMOS Technology
2.2. Regenerative Comparator in PSUEDO NMOS Technology
Figure 2 shows the structure of regenerative comparator employing pseudo NMOS technology [14],
[18]. This technique engages a grounded PMOS as load for NMOS steering circuit.
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Figure 2. Regenerative comparator in pseudo NMOS technology
This circuit use overall 25 MOSFET. The input signal is feed through T1 & T2 MOSFET’s which
are arranged in fully differential pair. Second stage is used for amplification then two NOR gates to provide
regenerative feedback in the end. G1, G2, G3, G4, G5 & G6 MOSFET’S are structured in pseudo NMOS
technology which forms the two NOR gates at end of circuit. Inverted and non-inverted output is then taken
from Vout (-) & Vout (+).
2.3. Regenerative Comparator in CVSL Technology
Figure 3 depicts the architecture for regenerative comparator designed in CVSL technology [15]
[19]. CVSL technology is nothing but cascade voltage switch logic or differential voltage switch logic [20].
MOS transistors G1 to G12 are used to design NOR gates in CVSL technology. Gate voltage to these
MOSFET’S are applied in differential form that alter the on & off time of these MOSFET’S which results in
decrease in power dissipation [21]. Inputs are given to the gate terminal of T1 & T2 MOSFET’s & output
from Vout (+) and Vout (-). The number of MOSFET used for this architecture is 31.
Figure 3. Regenerative Comparator in CVSL technology
2.4. Regenerative Comparator in Power Gating Technology
Figure 4 depicts the architecture for regenerative comparator using power gating technology [16].
Power Gating is the most effective technique to reduce the power dissipation especially leakage power [22]
[23]. Pre-charge and evaluation mode are followed for the execution of full comparison phase. Dual input
fully differential pair that comprise of T1 & T2 MOSFET’s are used for feeding the input signal and output
4. Int J Elec & Comp Eng ISSN: 2088-8708
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction ... (Anil Khatak)
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from Vout (+) and Vout (-). P1, P2, P3 & P4 MOSFETS are used to operate the circuit in Pre-charge and
evaluation mode. G1 to G8 MOSFET’S are used for designing two nor gates at the end of the schematic.
Substantial power reduction is obtained with this technique. Total MOS devices used in this technique is
same as CVSL technology.
Figure 4. Regenerative Comparator in Power Gating Technology
3. RESULTS AND DISCUSSION
In this segment transient analysis for the above four circuits are done by varying channel width,
supply voltage and temperature. Simulations are performed using spice based 90 nm CMOS technology.
Figure 5 gives the graphical details regarding to the power consumption and current drawn for the
regenerative comparator [8] and its variation with channel width and supply voltage respectively. In Figure
5(a) channel width is varied from 1 µm to 5 µm by keeping the supply voltage constant (0.7 V). The
percentage increase due to the variation in channel width is 38.67. Figure 5(b) shows variations in power
dissipation and current drawn by varying the supply voltage from 1.7 V to 0.7 V at channel width of 1µm.
Due to this variation power dissipation decreases by 98 percent.
(a) (b)
Figure 5. (a) Power consumption & current drawn vs channel width; (b) Power consumption & current drawn
vs supply voltage
Table 1 gives the details regarding to the variations in power consumption and current drawn by the
circuit to the varying temperature in different modes i.e. leakage, static, dynamic, total. Power consumption
and current drawn values shows variations when temperature varies from -35ᵒ to 80ᵒ Celsius.
0.6 0.8 1.0 1.2 1.4 1.6
0
500
1000
1500
Supply voltage (volts)
Power consumption (µW) Current drawn (µA)
1 3 50 2 4 6
20
40
60
80
100
120
Channel width (µm)
Power consumption (µW) Current drawn (µA)
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Table 1. Total, static, dynamic & leakage power consumption of regenerative comparator at different
temperature
Temp
Leakage Static Dynamic Total
PC (nW) CD (nA) PC (µW) CD (µA) PC (µW) CD (µA) PC (µW) CD (µA)
80ᵒ 122.85 175.50 13.57 19.39 1.91 2.73 15.49 22.12
75ᵒ 111.62 159.46 13.62 19.45 1.84 2.64 15.47 22.10
65ᵒ 091.41 130.59 13.70 19.58 1.71 2.44 15.41 22.02
55ᵒ 074.02 105.75 13.78 19.69 1.56 2.23 15.35 21.93
45ᵒ 059.22 084.60 13.85 19.79 1.41 2.02 15.26 21.81
35ᵒ 046.76 066.81 13.90 19.86 1.25 1.79 15.16 21.65
25ᵒ 036.42 052.03 13.92 19.89 1.09 1.56 15.02 21.46
15ᵒ 027.96 039.94 13.92 19.89 0.93 1.34 14.86 21.23
05ᵒ 021.14 030.20 13.88 19.83 0.78 1.12 14.66 20.95
00ᵒ 018.28 026.11 13.84 19.77 0.71 1.01 14.55 20.79
-05ᵒ 015.74 022.49 13.79 19.70 0.64 0.91 14.43 20.62
-15ᵒ 011.56 016.52 13.64 19.49 0.51 0.73 14.16 20.23
-25ᵒ 008.39 011.99 13.44 19.20 0.41 0.58 13.85 19.79
-35ᵒ 006.04 008.63 13.18 18.82 0.32 0.46 13.50 19.29
As the temperature increases leakage & dynamic power consumption increases on the other hand
static power consumption also shows this increasing pattern but slight variation at higher temperatures. Thus,
the total power consumption also increases from 13.50 µW at -35ᵒ C to 15.49 µW at 80ᵒ C. Total power
consumption increases by 14 percent due to the variation in temperature.
Figure 6 gives the graphical details regarding to the power consumption and current drawn for the
regenerative comparator designed using psuedo NMOS technology and its variation with channel width and
Supply voltage respectively. In Figure 6(a) channel width is varied from 1 µm to 5 µm by keeping the supply
voltage constant (0.7 V). The power consumption is maximum at 2.5 µm that is 137.13 µW at this circuit
also draw maximum current from supply voltage. Figure 6(b) shows variations in power dissipation and
current drawn by varying the supply voltage from 1.7 V to 0.7 V at channel width of 1 µm. Due to this
variation minimum power consumption is at 0.7 V that is 126.53 µW and maximum at 1.5 V that is 1106.00
µW.
(a) (b)
Figure 6. (a) Power consumption & current drawn vs channel width; (b) Power consumption & current drawn
vs supply voltage
Table 2 gives the details regarding to the variations in power consumption and current drawn by the
circuit to the varying temperature in different modes i.e. leakage, static, dynamic, total. Power consumption
and current drawn values shows variations when temperature varies from -35ᵒ to 80ᵒ Celsius. As the
temperature increases leakage & dynamic power consumption increases with approximately 300% variation.
0.6 0.8 1.0 1.2 1.4 1.6
0
500
1000
1500
Supply voltage (volts)
Power consumption (µW) Current drawn (µA)
1 3 52 4
20
40
60
80
100
120
140
160
180
200
220
Channel width (µm)
Power consumption (µW) Current drawn (µA)
6. Int J Elec & Comp Eng ISSN: 2088-8708
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4927
Table 2. Total, static, dynamic & leakage power consumption of regenerative comparator (psuedo NMOS) at
different temperature
Temp
Leakage Static Dynamic Total
PC (µW) CD (µA) PC (µW) CD (µA) PC (µW) CD (µA) PC (µW) CD (µA)
80ᵒ 15.62 22.31 080.43 114.90 326.61 466.59 407.04 581.49
75ᵒ 14.84 21.20 081.36 116.23 330.40 472.00 411.77 588.24
65ᵒ 13.34 19.06 083.29 118.99 080.38 114.83 163.67 233.82
55ᵒ 11.92 17.03 085.31 121.87 063.16 090.23 148.47 212.11
45ᵒ 10.59 15.13 087.42 124.89 051.38 073.40 138.81 198.30
35ᵒ 09.35 13.36 089.64 128.06 042.21 060.30 131.85 188.37
25ᵒ 08.22 11.74 091.97 131.39 034.55 049.36 126.53 180.75
15ᵒ 07.19 10.28 094.42 134.89 027.51 039.30 121.93 174.19
05ᵒ 06.28 08.98 097.01 138.58 020.06 028.66 117.07 167.25
00ᵒ 05.87 08.39 098.35 140.50 016.10 023.00 114.46 163.51
-05ᵒ 05.49 07.84 099.73 142.48 012.09 017.27 111.82 159.75
-15ᵒ 04.82 06.89 102.61 146.59 004.00 005.72 106.62 152.32
-25ᵒ 04.29 06.13 105.66 150.95 -003.97 -005.68 101.69 145.27
-35ᵒ 03.89 05.56 108.90 155.57 -011.31 -016.17 097.58 139.40
On the other hand, static power consumption follows inverse rule with temperature having
maximum value of 108.90 µW at -35ᵒ C. Thus, the total power consumption also increases from 97.58 µW at
-35ᵒ C to 407.04 µW at 80ᵒ C. Total power consumption increases by 317% due to the variation in
temperature.
Figure 7 gives the graphical details regarding to the power consumption and current drawn for the
regenerative comparator designed using CVSL technology and its variation with channel width and supply
voltage respectively. Figure 7(a) depict the varitions when channel width is varied from 1 µm to 5 µm by
keeping the supply voltage constant (0.7 V). The power consumption for this circuit is maximum at 5 µm that
is 256.67 µW and draw maximum current from supply voltage. On the otherside in figure 7(b) the variations
in power dissipation and current drawn by varying the supply voltage from 1.7 V to 0.7 V at channel width of
1 µm is shown. Due to this variation minimum power consumption is at 0.7 V that is 18.94 µW and
maximum at 1.3 V that is 399.59 µW.
(a) (b)
Figure 7. (a) Power consumption & current drawn vs channel width; (b) Power consumption & current drawn
vs supply voltage
Table 3 gives the details regarding to the variations in power consumption and current drawn by the
regenerative comparator designed using CVSL technology to the varying temperature in different modes i.e.
leakage, static, dynamic, total. Power consumption and current drawn values shows variations when
temperature varies from -35ᵒ to 80ᵒ Celsius. As the temperature increases leakage power consumption
increases with approximately 300% percent variation maximum value of 2378.64 nW at 80ᵒ C. On the other
hand, static power consumption increases with increase in temperature having maximum value of 0.93 µW at
80ᵒ C. Dynamic power consumption shows abrupt nature as it increases and decreases with temperature
variations. Maximum value of dynamic power consumption is 23.37 µW at 65ᵒ C & minimum value of 16.34
µW at -5° C. Thus, the total power consumption also follows the same abrupt nature as dynamic power
consumption follows. Total power consumption attains its maximum value of 24.20µW at 65ᵒ C and
minimum value of 16.77 µW at -5° C.
1 3 52 4
20
40
60
80
100
120
Channel width (µm)
Power consumption (µW) Current drawn (µA)
0.6 0.8 1.0 1.2 1.4 1.6
0
500
1000
1500
Supply voltage (volts)
Power consumption (µW) Current drawn (µA)
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Table 3. Total, static, dynamic & leakage Power consumption of regenerative comparator (CVSL
Technology) at different temperature
Temp
Leakage Static Dynamic Total
PC (nW) CD (nA) PC (µW) CD (µA) PC (µW) CD (µA) PC (µW) CD (µA)
80ᵒ 2378.64 3398.06 0.93 1.33 00.00 00.01 00.94 01.34
75ᵒ 2261.27 3230.38 0.89 1.28 00.00 00.01 00.90 01.29
65ᵒ 2035.81 2908.30 0.82 1.18 23.37 33.39 24.20 34.57
55ᵒ 1823.35 2604.78 0.76 1.08 21.25 30.36 22.02 31.45
45ᵒ 1624.54 2320.77 0.69 0.99 19.96 28.52 20.66 29.52
35ᵒ 1439.97 2057.09 0.63 0.91 19.06 27.23 19.70 28.14
25ᵒ 1270.13 1814.47 0.58 0.83 18.36 26.23 18.94 27.06
15ᵒ 1115.49 1593.55 0.52 0.75 17.74 25.34 18.27 26.10
05ᵒ 0976.45 1394.94 0.47 0.68 17.05 24.37 17.53 25.05
00ᵒ 0912.92 1304.18 0.45 0.64 16.69 23.85 17.15 24.50
-05ᵒ 0853.44 1219.21 0.43 0.61 16.34 23.34 16.77 23.96
-15ᵒ 0746.86 0166.95 0.38 0.55 22.19 31.71 22.58 32.26
-25ᵒ 0657.17 0938.82 0.34 0.49 19.33 27.62 19.68 28.12
-35ᵒ 0584.98 0835.69 0.30 0.44 18.03 25.76 18.34 26.20
Figure 8 gives the details regarding to the power consumption and current drawn for the
regenerative comparator designed using power gating technology. Figure 8(a) grphicaly shows the variations
when channel width is varied from 1 µm to 5 µm by keeping the supply voltage constant (0.7 V). The power
consumption is maximum at 5 µm that is 62.20 µW at this circuit also draw maximum current of 88.86 µA
from supply voltage. Figure 8(b) shows variations in power dissipation and current drawn by varying the
supply voltage from 1.7 V to 0.7 V at channel width of 1 µm. Due to this variation minimum power
consumption is at 0.7 V that is 21.66 µW and maximum at 1.5 V that is 192.75 µW.
(a) (b)
Figure 8. (a) Power consumption & current drawn vs channel width; (b) Power consumption & current drawn
vs supply voltage
Table 4 gives the details regarding to the variations in power consumption and current drawn by the
regenerative comparator designed using power gating technology to the varying temperature in different
modes i.e. leakage, static, dynamic, total. As the temperature increases leakage power consumption increases
with approximately 300% percent variation maximum value of 33.53 nW at 80ᵒ C. On the other hand, static
power consumption increases with increase in temperature having maximum value of 46.53 nW at 80ᵒ C.
1 3 50 2 4 6
20
40
60
80
100
Channel width (µm)
Power consumption (nW) Current drawn (nA)
0.6 0.8 1.0 1.2 1.4 1.6
0
20
40
60
80
100
120
140
160
180
200
220
Supply voltage (volts)
Power consumption (nW) Current drawn (nA)
8. Int J Elec & Comp Eng ISSN: 2088-8708
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction ... (Anil Khatak)
4929
Table 4. Total, static, dynamic & leakage Power consumption of regenerative comparator (gating
Technology) at different temperature
Temp
Leakage Static Dynamic Total
PC (nW) CD (nA) PC (nW) CD (nA) PC (nW) CD (nA) PC (nW) CD (nA)
80ᵒ 33.53 47.91 46.53 66.47 0.00760 0.01086 46.52 66.46
75ᵒ 30.36 43.37 43.74 62.48 0.00511 0.00730 43.73 62.48
65ᵒ 24.66 35.24 38.48 54.97 0.00238 0.00339 38.48 54.97
55ᵒ 19.80 28.29 33.66 48.09 0.00118 0.00167 33.66 48.08
45ᵒ 15.69 22.41 29.26 41.81 0.00062 0.00087 29.26 41.80
35ᵒ 12.25 17.51 25.26 36.09 0.00034 0.00048 25.26 36.09
25ᵒ 09.43 13.47 21.66 30.95 0.00019 0.00026 21.66 30.95
15ᵒ 07.13 10.19 18.46 26.38 0.00009 0.00013 18.46 26.38
05ᵒ 05.30 07.58 15.68 22.41 0.00003 0.00003 15.68 22.41
00ᵒ 04.54 06.49 14.45 20.65 0.00000 0.00000 14.45 20.65
-05ᵒ 03.58 05.11 13.32 19.03 0.00003 0.00003 13.32 19.03
-15ᵒ 02.58 03.68 11.37 16.25 0.00007 0.00009 11.37 16.25
-25ᵒ 01.83 02.62 09.82 14.03 0.00011 0.00015 09.82 14.03
-35ᵒ 01.41 02.01 08.92 12.95 0.28376 0.61164 08.64 12.34
Dynamic power consumption shows very small variations of few nW. Thus, the total power
consumption also attains marginal value as compared to earlier discuss circuits. Total power consumption
attains its maximum value of 46.52 nW at 80ᵒ C and minimum value of 8.64 nW at -35° C.
Table 5 shows the brief comparison of the results for all four types of schematics discussed above.
The regenerative comparator using power gating technique shows minimum power consumption of 21.66614
nW as compared to others while drawing a current of 30.95163 nA from 0.7 V supply voltage.
Table 5. Comparison of results
Regenerative
comparator
Regenerative
comparator with
pseudo NMOS
Regenerative
comparator with
CVSL
Regenerative
comparator with
power gating
Temperature 25ᵒC 25ᵒC 25ᵒC 25ᵒC
No. Of MOSFETS 27 25 31 31
Channel Length 90 nm 90 nm 90 nm 90 nm
Channel Width 1 µm 1 µm 1 µm 1 µm
Supply voltage 0.7 V 0.7 V 0.7 V 0.7 V
Total Power consumption 15.02696µW 126.53128 µW 18.94745 µW 21.66614nW
Total Current drawn 21.46708µA 180.75897 µA 27.06779 µA 30.95163nA
Table 6 shows the variations in the power consumptions for all four schematics when the
temperature is varied from -35ᵒ to +80ᵒ Celsius.
Table 6. Percentage variation Power consumption (PC) with temperature
Regenerative
comparator
Regenerative comparator
with pseudo NMOS
Regenerative comparator
with CVSL
Regenerative comparator
with power gating
Temperature -35ᵒ to +80ᵒ -35ᵒ to +80ᵒ -35ᵒ to +80ᵒ -35ᵒ to +80ᵒ
Leakage PC 83.39 to 237.27 52.63 to 89.93 45957.2 to 87.27 85.02 to 255.65
Static PC 5.37 to 2.51 18.40 to 12.55 46.79 to 60.57 58.80 to 114.76
Dynamic PC 70.19 to 74.16 132.75 to 845.24 1.79 to 99.95 149247 to 3900
Total PC 10.10 to 3.08 22.87 to 221.69 3.17 to 95.02 60.11 to 114.72
4. COMPARISON
In order to compare simulation results four more comparator structures are again simulated in 90nm
CMOS technology. These four structures are dynamic comparator (conventional) [24], dynamic comparator
(double tail) [24], dynamic comparator (modified double tail) [24], comparator with two cross-coupled
inverters [25]. Results that are obtained after simulation along with four recent comparator structures [26]
[27]-[29] which are also included for comparison are shown in Table 7. Regenerative comparator (Power
gating) shows optimum results in comparison.
9. ISSN: 2088-8708
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Table 7. Comparison of results at 25ᵒ Celsius
No. of
MOSFETS
Channel
Length
Channel
Width
Supply
voltage
Total Power
consumption
Dynamic Comparator (Conventional) [24] 09 90 nm 1 µm 0.7 V 02.77 nW
Dynamic Comparator (Double Tail) [24] 14 90 nm 1 µm 0.7 V 10.60 nW
Dynamic Comparator (Modified Double Tail) [24] 18 90 nm 1 µm 0.7 V 14.19 nW
Comparator with two cross-coupled inverters [25] 15 90 nm 1 µm 0.7 V 13.84 µW
[26] 14 90 nm - 1.0 V 82.00 µW
[27] - 40 nm - 0.6 V 01.50 µW
[28] 16 180 nm - 1.6 V 17.00 µW
[29] 06 65 nm - 1.2 V 755.00 µW
Regenerative comparator [13] 27 90 nm 1 µm 0.7 V 15.02 µW
Regenerative comparator with power gating 31 90 nm 1 µm 0.7 V 21.66 nW
So, by comparing on the basis of power consumption with its variation with channel width, supply
voltage & temperatures it is clearly observed that regenerative comparator with power gating show good
performance with respect to others.
5. CONCLUSION
Three different power reduction techniques are implemented on regenerative comparator circuits.
Out of these three techniques power gating technique shows substantial decrease in total power consumption
along with the reduction in leakage current. Total power consumption of 15.026 µW reduced to 21.666 nW
for regenerative comparator with power gating technique which certainly improves its performance. Four
conventional & four recent comparator structures are compared with regenerative comparator (power gating).
Hence it is observed that the regenerative comparator with power gating technique shows optimum power
consumption with high speed of operation due to regenerative latch at its end. This definitely will increase its
applicabilties in high speed and low power UDSM data converter circuits designs.
REFERENCES
[1] B. Razavi, “Principles of Data Conversion System Design,” AT&T Bell laboratories, IEEE Press, 1995.
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