In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Analysis and Comparison of CMOS Comparator At 90 NM TechnologyIJERA Editor
In this paper, A CMOS comparator with low power dissipation is presented. The preamplifier latch comparator is compared with conventional double tail comparator. The comparators designed and simulated in 90nm Cadence virtuoso environment technology. The particular preamplifier latch comparator will be mix of a good amplifier and a latch comparator can easily effect higher velocity and also low electric power dissipation. The proposed circuit topology improves kickback noise and reduces power dissipation compared with a conventional double tail comparator.Analysis are testified and compared with conventional comparator and enhancements are detected in this paper.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
Analysis and Comparison of CMOS Comparator At 90 NM TechnologyIJERA Editor
In this paper, A CMOS comparator with low power dissipation is presented. The preamplifier latch comparator is compared with conventional double tail comparator. The comparators designed and simulated in 90nm Cadence virtuoso environment technology. The particular preamplifier latch comparator will be mix of a good amplifier and a latch comparator can easily effect higher velocity and also low electric power dissipation. The proposed circuit topology improves kickback noise and reduces power dissipation compared with a conventional double tail comparator.Analysis are testified and compared with conventional comparator and enhancements are detected in this paper.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
A Novel Approach of Position Estimation and Power Factor Corrector Converter ...IJPEDS-IAES
This paper proposes a Power factor Corrected (PFC) Bridgeless Buck-Boost converter fed BLDC motor drive. The Bridgeless configuration eliminates the Diode Bridge Rectifier in order to reduce the number of components and the conduction loss. The position sensors used in BLDC drives have drawbacks of additional cost, mechanical alignment problems. These bottle necks results in sensorless technique. The Sensorless technique mostly relies on measurement of Back EMF to determine relative positions of stator and rotor for the correct coil energising sequence can be implemented. This paper introduces the offline Finite Element method for sensorless operation. The proposed sensorless scheme estimates the motor position at standstill and running condition. The obtained Power Factor is within the acceptable limits IEC 61000-3-2. The proposed drive is simulated in MATLAB/Simulink the obtained results are validated experimentally on a developed prototype of the drive.
This paper presents the optimization of PFC Cuk converter parameter design for the minimization of THD and voltage ripple. In this study, the PFC Cuk converter is designed to operate in discontinuous conduction mode (DCM) in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Nevertheless, the ranges of duty cycle for buck and boost operations are 0<D<0.5 and 0.5<D<1, respectively for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor for minimization of THD current. In addition, the selection of high output capacitance will minimize the output voltage ripple significantly. A 65 W PFC Cuk converter prototype is developed and experimentally tested to confirm the parameters design optimization principle. The experimental results show that the THD current is reduced to 4.5% from 61.3% and the output voltage ripple is reduced to 7 V from 18 V after parameters optimization are realized. Furthermore, it is confirmed that the output voltage ripple frequency is always double of the input line frequency, 50 Hz and the output voltage ripple is always lower than the maximum input voltage ripple.
MODELLING OF 200W LED DRIVER CIRCUIT DESIGN WITH LLC CONVERTERJournal For Research
LED is a recent technology, which has replaced all other conventional light sources in the past few years and since it is current controlled, accurate driver design is necessary. The LED driver should have the capability of providing constant current regardless of the LED forward voltage variations. The LLC converter is controlled to operate as a constant current mode LED driver. A 100 kHz, 200W LLC LED driver is designed and calculated to verify the proposed circuit and design method. This paper proposes mathematical model of 200W LED driver circuit design with LLC resonant converter. The proposed circuit uses a full bridge rectifier to convert AC to DC and increases the rectified output voltage using boost converter which is operated in continuous conduction mode and a quasi-half bridge resonant converter to drive the LED lamp load with coupling transformer. The LLC converter is designed such that solid state switches of quasi half bridge are working under zero switching scheme to reduce switching losses. The analysis, design and modelling of 200 W LED driver is carried out by mathematical model and stability analysis for universal AC mains.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
Design and Simulation of First Order Sigma-Delta Modulator Using LT spice ToolIJERA Editor
A switched-capacitor single-stage Sigma-Delta ADC with a first-order modulator is proposed. Efficient low power first Order 1-Bit Sigma-Delta ADC designed which accepts input signal bandwidth of 10 MHz. This circuitry performs the function of an analog-to-digital converter. A first-order 1-Bit Sigma-Delta (Σ-Δ) modulator is designed, simulated and analyzed using LTspice standard 250nm CMOS technology power supply of 1.8V. The modulator is proved to be robustness, the high performance in stability. The simulations are compared with those from a traditional analog-to-digital converter to prove that Sigma-Delta is performing better with low power and area.
AN ACTIVE PFC WITH FLYBACK DESIGN FOR INTELLIGENCE IN STREET LIGHT APPLICATIONJournal For Research
As the requirement of energy demand is increasing due to rapid industrial development, it is necessary to meet the growing demand of energy. This can be achieved in two ways: find alternate resource to supply power or energy; or reduce the energy consumption of present resources available. The proposed work is basically the design and implementation of an intelligent street light of 50 W power output from the offline converter by using power LED. As power LED draws huge non sinusoidal current due to the presence of AC-DC converter, a Boost PFC and a fly back converter is used for better power factor and for dc voltage regulation. Along with this a PIR sensor and LDR sensors are also used. A PIC microcontroller is used for PWM dimming. This makes to reduce the power consumption in street light especially in urban cities in which most of the power is wasted in lighting streets during late night.
Improved power quality buck boost converter for SMPSIJECEIAES
In this paper, a Neural Network (NN) controlled Buck-Boost Converter (BBC) based Switched Mode Power Supply (SMPS) for a PC application is proposed. The proposed BBC is analyzed, modeled and designed for the rated load. Generally, the utilization of Multiple Output SMPS (MOSMPS) for PC application introduces Power Quality (PQ) issues in the power system network. Unlike conventional SMPS the proposed NN controlled BBC can accomplish improvement of power quality. The NN controller reduces the Total Harmonic Distortion (THD) of source current below 5%, maintains input side Power Factor (PF) to be nearly unity and improves the output voltage regulation. In the proposed system, NN controller replaces the conventional PI controller and overcomes the drawbacks of the conventional system. The proposed BBC is validated adopting MATLAB/SIMULINK software. The simulation analysis validate that the proposed NN controlled BBC performs better than conventional converter in terms of PQ indices under fluctuating conditions.
A three level quasi-two-stage single-phase pfc converter with flexible output...LeMeniz Infotech
A three level quasi-two-stage single-phase pfc converter with flexible output voltage and improved conversion efficiency
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
A Novel Approach of Position Estimation and Power Factor Corrector Converter ...IJPEDS-IAES
This paper proposes a Power factor Corrected (PFC) Bridgeless Buck-Boost converter fed BLDC motor drive. The Bridgeless configuration eliminates the Diode Bridge Rectifier in order to reduce the number of components and the conduction loss. The position sensors used in BLDC drives have drawbacks of additional cost, mechanical alignment problems. These bottle necks results in sensorless technique. The Sensorless technique mostly relies on measurement of Back EMF to determine relative positions of stator and rotor for the correct coil energising sequence can be implemented. This paper introduces the offline Finite Element method for sensorless operation. The proposed sensorless scheme estimates the motor position at standstill and running condition. The obtained Power Factor is within the acceptable limits IEC 61000-3-2. The proposed drive is simulated in MATLAB/Simulink the obtained results are validated experimentally on a developed prototype of the drive.
This paper presents the optimization of PFC Cuk converter parameter design for the minimization of THD and voltage ripple. In this study, the PFC Cuk converter is designed to operate in discontinuous conduction mode (DCM) in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Nevertheless, the ranges of duty cycle for buck and boost operations are 0<D<0.5 and 0.5<D<1, respectively for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor for minimization of THD current. In addition, the selection of high output capacitance will minimize the output voltage ripple significantly. A 65 W PFC Cuk converter prototype is developed and experimentally tested to confirm the parameters design optimization principle. The experimental results show that the THD current is reduced to 4.5% from 61.3% and the output voltage ripple is reduced to 7 V from 18 V after parameters optimization are realized. Furthermore, it is confirmed that the output voltage ripple frequency is always double of the input line frequency, 50 Hz and the output voltage ripple is always lower than the maximum input voltage ripple.
MODELLING OF 200W LED DRIVER CIRCUIT DESIGN WITH LLC CONVERTERJournal For Research
LED is a recent technology, which has replaced all other conventional light sources in the past few years and since it is current controlled, accurate driver design is necessary. The LED driver should have the capability of providing constant current regardless of the LED forward voltage variations. The LLC converter is controlled to operate as a constant current mode LED driver. A 100 kHz, 200W LLC LED driver is designed and calculated to verify the proposed circuit and design method. This paper proposes mathematical model of 200W LED driver circuit design with LLC resonant converter. The proposed circuit uses a full bridge rectifier to convert AC to DC and increases the rectified output voltage using boost converter which is operated in continuous conduction mode and a quasi-half bridge resonant converter to drive the LED lamp load with coupling transformer. The LLC converter is designed such that solid state switches of quasi half bridge are working under zero switching scheme to reduce switching losses. The analysis, design and modelling of 200 W LED driver is carried out by mathematical model and stability analysis for universal AC mains.
Analysis and Characterization of Different Comparator TopologiesAalay Kapadia
Comparator is one of the most important analog circuits required in many analog integrated circuits. It is used for the comparison between two different or same electrical signals. The design of Comparator becomes an important issue when technology is scaled down. Due to the non-linear behavior of threshold voltage (VT) when technology is scaled down, performance of Comparator is affected. Many versions of comparator are proposed to achieve desirable output in sub-micron and deep sub-micron technologies. The selection of particular topology is dependent upon the requirements and application. In this paper, we have shown the implementation of different topologies in 0.5 μm technology using the Mentor Graphics Tool. We have done the pre-layout simulation of two different topologies. We have performed DC, AC and transient analysis. We have also calculated output impedance. We have prepared a comparative analysis about them.
Design and Simulation of First Order Sigma-Delta Modulator Using LT spice ToolIJERA Editor
A switched-capacitor single-stage Sigma-Delta ADC with a first-order modulator is proposed. Efficient low power first Order 1-Bit Sigma-Delta ADC designed which accepts input signal bandwidth of 10 MHz. This circuitry performs the function of an analog-to-digital converter. A first-order 1-Bit Sigma-Delta (Σ-Δ) modulator is designed, simulated and analyzed using LTspice standard 250nm CMOS technology power supply of 1.8V. The modulator is proved to be robustness, the high performance in stability. The simulations are compared with those from a traditional analog-to-digital converter to prove that Sigma-Delta is performing better with low power and area.
AN ACTIVE PFC WITH FLYBACK DESIGN FOR INTELLIGENCE IN STREET LIGHT APPLICATIONJournal For Research
As the requirement of energy demand is increasing due to rapid industrial development, it is necessary to meet the growing demand of energy. This can be achieved in two ways: find alternate resource to supply power or energy; or reduce the energy consumption of present resources available. The proposed work is basically the design and implementation of an intelligent street light of 50 W power output from the offline converter by using power LED. As power LED draws huge non sinusoidal current due to the presence of AC-DC converter, a Boost PFC and a fly back converter is used for better power factor and for dc voltage regulation. Along with this a PIR sensor and LDR sensors are also used. A PIC microcontroller is used for PWM dimming. This makes to reduce the power consumption in street light especially in urban cities in which most of the power is wasted in lighting streets during late night.
Improved power quality buck boost converter for SMPSIJECEIAES
In this paper, a Neural Network (NN) controlled Buck-Boost Converter (BBC) based Switched Mode Power Supply (SMPS) for a PC application is proposed. The proposed BBC is analyzed, modeled and designed for the rated load. Generally, the utilization of Multiple Output SMPS (MOSMPS) for PC application introduces Power Quality (PQ) issues in the power system network. Unlike conventional SMPS the proposed NN controlled BBC can accomplish improvement of power quality. The NN controller reduces the Total Harmonic Distortion (THD) of source current below 5%, maintains input side Power Factor (PF) to be nearly unity and improves the output voltage regulation. In the proposed system, NN controller replaces the conventional PI controller and overcomes the drawbacks of the conventional system. The proposed BBC is validated adopting MATLAB/SIMULINK software. The simulation analysis validate that the proposed NN controlled BBC performs better than conventional converter in terms of PQ indices under fluctuating conditions.
A three level quasi-two-stage single-phase pfc converter with flexible output...LeMeniz Infotech
A three level quasi-two-stage single-phase pfc converter with flexible output voltage and improved conversion efficiency
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study and implementation of comparator in cmos 50 nm technologyeSAT Journals
Abstract This paper describes the comparator circuits used in FLASH Analog to digital converter (ADC). The performance of FLASH ADC is greatly influenced by the choice of comparator. In this paper, first a single ended “Threshold Inverter Quantizer” (TIQ) is presented. The TIQ comparator is based on a CMOS inverter cell, in which voltage transfer characteristics (VTC) are changed by systematic transistor sizing. However, TIQ comparator is very sensitive to power supply noise. Another comparator circuit presented in this paper is “Two stage open loop comparator”. It is implemented in 50 nm CMOS Technology. Pre-simulation of comparator is done in LT-Spice and post layout simulation is done in Microwind 3.1. Keywords: CMOS, Comparator, TIQ (Threshold Inverter Quantizer), LT-Spice.
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Comparator holds a dominant place in fast ADC circuit for the conversion of analog to digital signal. In this modernized digital world every utilization circuits requires an ADC’s with low power to consumption. This in turn reflects in the design of comparators during the design process of the fast ADC circuits, scope is due to the higher number of comparator usage. As the technologies are scaling down, the number of transistor per unit area increases, so that the sub threshold leakage current increases which leads to power consumption in any circuit. This sources the project idea to design a comparator. It is presumed during the design that, it consumes low power in its double tail configuration which when replaces an inverter circuit in latch stage of the double tail comparator by a sleepy inverter. This presumption is validated through the analysis of the simulation results. The power consumption of the designed proposed double tail comparator is 30μw when compared to 35 μw in the conventional type. 2-bit flash ADC circuit is designed and analyzed under two different configurations of the double tail comparator. From the results, it is clear that the power consumption of the ADC circuit designed with proposed sleepy inverter based double tail comparator is observed to be 45mw.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational
transconductance amplifier (OTA) is one of the most important components of ADC. This paper presents a
new design of two stages OTA. The design incorporates Sleep insertion technique and leakage feedback current
approach for improving design parameters such as gain, and power as compared to earlier work. The design is
simulated in 0.18µm CMOS technology with supply voltage 1.8V.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
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International Journal of Engineering Research and DevelopmentIJERD Editor
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Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Application
1. Rohit Mongre Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 8( Version 1), August 2014, pp. 146-153
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Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Application Rohit Mongre1, R. C. Gurjar2 1Department of Electronics & Instrumentation Engineering, Shri G S Institute of Technology & Science, 23, Park Road, Indore, M.P., India – 452003 2Electronics & Instrumentation Engineering Department, Shri G S Institute of Technology & Science, 23, Park Road, Indore, M.P., India – 452003 Abstract In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Index Terms – Preamplifier based Comparator, dynamic comparator, dynamic comparator with positive feedback, Dynamic comparator with positive feedback PMOS as switch, low power, low offset, high speed, low noise, A/D Converter.
I. INTRODUCTION
The fast growing electronics industry is pushing towards high speed low power analog to digital converters. Comparator is electronic devices which are mainly used in Analog to Digital converter (ADC). In ADC they are used for quantization process, and are mainly responsible for the delay produced and power consumed by an ADC. A high speed low power comparator is required to satisfy the future demands The Comparators are used in analog- to-digital converters (ADCs), data transmission applications, switching power regulators and many other applications. The voltages that appear at the inputs are compared by the comparator that produces a binary output which represents a difference between them. They are critical components in analog-to-digital converters. Designing high-speed comparators becomes more challenging when working with smaller supply voltages. In other words, for a given technology, to attain high speed, transistors with increased width and length values are required to compensate for the reduction of supply voltage, which also means increased chip area and power. So, Transistor width and length are adjusted accordingly. For minimum power consumption and maximum operating speed. A model for the comparator is developed and discussed, and its functionality is verified by showing a comparison of result obtained for the proposed model and the existing model. The platform used to develop and analyze the existing model Cadence Environment (Virtuoso). The
comparator is basically excluded from application to the high speed A/D converters with high resolution owning to its large offset voltage which significantly affects the resolution. As a consequence, the preamplifier based comparator topology in which an amplifier is added before a latched comparator, aiming at achieving small offset voltage and high speed, has been developed . The preamplifier based comparator , which combine of an amplifier and a latch comparator can obtain high speed and low power dissipation. Thus, by considering factors of speed and power dissipation, preamplifier latch comparator is the choice of A/D converters . Block representation of the proposed design of the comparator is shown in Fig. 1. This designed comparator consists of three stages namely input stage, decision stage and output stage. The input stage (pre amplification) amplifies the input signal to improve the comparator sensitivity and isolate the input of the Comparator from switching noise coming from positive feedback stage . The decision circuit is the heart of the comparator and should be capable of discriminating mV level signals and it is used to determine which of the input signals is larger .The final stage is the output stage (post amplification) . The final component in our comparator design is the output buffer or post-amplifier. The main purpose of the output buffer is to convert the output of the decision circuit into a logic signal (i.e., 0 or 5V).
RESEARCH ARTICLE OPEN ACCESS
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ISSN : 2248-9622, Vol. 4, Issue 8( Version 1), August 2014, pp. 146-153
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Figure 1. Block diagram of preamplifier based
comparator
II. DESIGN SPECIFICATION
A. Clock frequency
The clock frequency “fc” is defined as the
reciprocal of the time interval T, as:
fc = 1/ T (1)
The clock frequency has to be equal or greater than
twice of the frequency bandwidth of analog signals .
B. Power dissipation
The power dissipated by comparator is simply
the product of the sum of the current flowing in the
current source with power supply voltage. We were
primarily considering high speed and low voltage.
Dynamic comparator power dissipation resembles
that of digital gates, which have a power dissipation
given approximately by :
2
DD p fcv (2)
Where,
f = output frequency,
VDD = supply voltage
C = output capacitance
If a square pulse is applied to the input of the
comparator with a period t and frequency f, the
average amount of current that the comparator must
pull from VDD, recalling the current is being supplied
from VDD only when p-channel is on. Notice that the
power dissipation is a function of the clock
frequency. A great deal of effort is put into reducing
the power dissipation in CMOS circuits. One of the
major advantages of dynamic logic is its power
dissipation.
C. Offset Voltage
The offset of this stage is dependent on both the
input amplifiers and the latching stage. Input-offset
voltage can be a particularly difficult problem in
comparator design. In precision applications, such as
high-resolution converters, large input-offset voltages
cannot be tolerated. The offset-voltage of the
comparator is reduced, using either Input Offset
Storage (IOS) or Output Offset Storage (OOS)
around the comparator preamplifier. In the IOS
configuration, the preamplifier must be stable in the
unity feedback configuration. Also, the MOSFETs of
the preamplifier must remain in saturation when the
offset voltage is stored on the capacitors. For the IOS
scheme the input storage capacitance must be much
larger than the input capacitance of the preamplifier,
so that the storage capacitors do not attenuate the
input signals. For the OOS scheme the storage
capacitors should be much larger than the input
capacitance of the dynamic latch. The total offset
voltage of the comparator consists of the sum of both
source coupled pairs. The offset of one differential
pair has the well-known dependency on the mismatch
of the threshold voltage ΔVT, load resistance ΔRL and
transistor dimensions Δβ and their corresponding
average values VT, RL, and β.
2
gs T L
OS T
L
V V R
V V
R
(3)
III. DESIGN OF COMPARATORS
Fig.5 presents the schematic view of the
proposed design. In this when clock (Clk) is low, the
latch comparator is reset, and at this time Clk1 is
high, latch-comparator can receive the amplified
signal of preamplifier. Fig.2 is a schemetic diagram
differential amplifier which amplifies the input signal
which enhances the sensitivity of comparator. Fig.3
is schemetic diagram of latch circuit also known as
heart of the comparator . Fig.4 is schemetic diagram
of output buffer, this part of comparator is needed to
amplify the signal coming from latch and to provide
enough current for the load
Fig :2
Fig:3
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Fig:4 output stage (post amplification). Preamplification This circuit is a differential amplifier with active loads. The sizes of NM0 and NM1 are set by considering the diff-amp transconductance and the input resistance. The transconductance sets the gain of the stage, while the input capacitance of the comparator is determined by the size of NM0 and NM1. We will concentrate on speed in the design, and therefore we will set the channel lengths of the MOSFETs to 180nm. (Channel length modulation gives rise to an unwanted offset voltage). Using the sizes given in the schematic, we can relate the input voltages to output currents by
To further increase the gain of the first stage, we can size up the widths of MOSFETs PM3 and PM4 relative to the widths of PM0 and PM1. Decision circuit The decision circuit is the heart of the comparator and should be capable of discriminating mV level signals. We should also be able to design the circuit with some hysteresis for use in rejecting noise on a signal. The circuit uses positive feedback from the cross-gate connection of NM1 and NM2 to increase the gain of the decision element. Let’s begin by assuming that io+ is much larger than io- so that M5 and M7 are ON and NM1 and NM3 are off. We will also assume that βNM0 = βNM3 = βA and βNM1 =β NM2 = βB. Under these circumstances, νo- is approximately 0V and νo+ is
If we start to increase io- and decrease io+ , switching takes place when the drain-source voltage of NM2 is equal to VTHN of NM1. At this point, NM1 starts to take current away from NM0. This decreases the drain-source voltage of NM0 and thus starts to turn NM2 off. If we assume that the maximum value of νo+ or νo- is equal to 2VTHN ,then NM1 and NM2 operate, under steady state βA=β5=β8 , βB =β6=β 7 .
Conditions, in either cutoff or the triode regions. Under these circumstances, the voltage across NM2 reaches VTHN, and thus NM2 enters the saturation region, when the current through NM2 is
This is the point at which switching takes place. That is , NM2 shuts off and NM1 turns on. If βA= βB, then switching takes place when the currents io+ and io- are equal. Unequal βs cause the comparator to exhibit hysteresis. A similar analysis for increasing io+ and decreasing io- yields a switching point of
Output Buffer:- The final component in our comparator design is the output buffer or post-amplifier. The main purpose of the output buffer is to convert the output of the decision circuit into a logic signal (i.e., 0 or 5V). The output buffer should accept a differential input signal and not have slew-rate limitations. The circuit used as an output buffer in our basic comparator design .This circuit is a self-biasing differential amplifier. We can see a problem in connecting the decision circuit directly to the output buffer. The MOSFET NM3 is added in series with the decision circuit to increase the average voltage out of the decision circuit. The size of the MOSFET is somewhat arbitrary. We will set W17/L17 =5 μm/100nm so that the output of the decision circuit is increased by approximately VTHN Design I : Proposed Comparator
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The complete schematic of the comparator is shown in fig . Here the input Voltage as a ref parameter. And sweep this parameter from 0 to 1.8 V. The reference Voltage as 1 Volt. So as above the Circuit is connected and the wave forms of the Output Voltages of Decision Circuit and Output Buffer are shown in Fig . Here the reference Voltage as 1V.So if the input Voltage is greater than reference Voltage it is giving output Voltage as logic 1.And if the Input Voltage is less than reference Voltage it gives the Output as logic 0.And also the output waveforms are shown. These waveforms are also changing at the reference Voltage. Transient analysis To calculate the delay of the comparator Transient analysis is needed. Here I have given input pulse to the one input of the Pre-amplifier. And I have given 500mv DC Voltage to the other end of the Pre-amplifier.
Fig:6 Transient Analysis of Preamplifier based Comparator
Fig:7 Power Dissipation of Preamplifier based Comparator Design II : DYNAMIC COMPARATOR DESIGN
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Fig : 9 Transient Analysis of Dynamic Comparator.
Fig:10 Power Dissipation of Dynamic Comparator Design III: Dynamic comparator with positive feedback
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Fig:13 Power Dissipation of Dynamic comparator with positive feedback. Design IV: DYNAMIC COMPARATOR USING POSITIVE FEEDBACK USING PMOS AS A SWITCH
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Fig:15 Transient Analysis of dynamic comparator with positive feedback using PMOS as switch
Fig:16 Power Dissipation of Dynamic Comparator with positive feedback using PMOS as Switch
IV. SIMULATION RESULTS AND DISCUSSION
Finally simulations of the comparator designs is done in cadence virtuoso with 0.18μm UMC Technology . Simulation results are presented including power dissipation, speed and delay. In these designs we have used single power supply i.e. 1.8 V. Through simulation we have obtained parameters of the comparator like power dissipation, clock frequency, time delay . In this work four comparator designs i.e preamplifier based fig:5, dynamic comparator, dynamic comparator with positive feedback, dynamic comparator with positive feedback using PMOS as switch has been simulated to obtain the low power and high speed parameters as it is required for robustness of the A/D converters. Final simulation results of the comparators are shown in Table1 and Table2. TABLE 1:SIMULATED POWER DISSIPATION OF COMPARATORS.
TYPES OF COMPARATOR
TECHNOLOGY USED
POWER SUPPLY
POWER DISSIPATION
DESIGN I
0.18μm
1.8V
108.0318μW
DESIGN II
0.18μm
1.8V
605.57mW
DESIGN III
0.18μm
1.8V
939.879 μW
DESIGN IV
0.18μm
1.8V
939.714 μW