The document discusses recent trends in using artificial neural networks (ANNs) for analog circuit design. It provides an introduction to analog design flows and challenges. ANNs can help automate analog circuit sizing and placement tasks. The document reviews literature on using ANNs for tasks like sizing circuits for different technologies and optimizing parameters. In conclusion, ANNs show promise for reducing analog design time and efforts by training on previous simulation data to optimize circuits.
Automated layout synthesis tool for op ampNurahmad Omar
Design Environment: Mentor Graphics
Language: Perl
OS: Unix
An algorithm is developed for designing an automatic Op-amp layout generation by using scripting language. The layout of the two-stage Op-amp will automatically draw out in the Mentor Graphics IC station by inserting the essential data. The main challenges are design a common-centroid layout template, and how to route each transistor automatically without violating the DRC (Design Rule Check).
The algorithm invokes DRC file, using circuit netlist information to generate circuit layout automatically with a common-centroid layout template.
Artificial intelligence in the design of microstrip antennaRaj Kumar Thenua
This work presents a Neural Network model for the design of Microstrip Antenna for a desired frequency between 3.5 GHz to 5.5 GHz. The results obtained from the proposed method are compared with the results of IE3D and are found to be in good agreement. The advantage of the proposed method lies with the fact that the various parameters required for the design of specific Microstrip antenna at a particular frequency of interest can be easily extracted without going into the rigorous time consuming, iterative design procedures using a costly software package. In this work, a general design procedure is suggested for the Microstrip antennas using artificial neural networks and this is demonstrated using the rectangular patch geometry.
Automated layout synthesis tool for op ampNurahmad Omar
Design Environment: Mentor Graphics
Language: Perl
OS: Unix
An algorithm is developed for designing an automatic Op-amp layout generation by using scripting language. The layout of the two-stage Op-amp will automatically draw out in the Mentor Graphics IC station by inserting the essential data. The main challenges are design a common-centroid layout template, and how to route each transistor automatically without violating the DRC (Design Rule Check).
The algorithm invokes DRC file, using circuit netlist information to generate circuit layout automatically with a common-centroid layout template.
Artificial intelligence in the design of microstrip antennaRaj Kumar Thenua
This work presents a Neural Network model for the design of Microstrip Antenna for a desired frequency between 3.5 GHz to 5.5 GHz. The results obtained from the proposed method are compared with the results of IE3D and are found to be in good agreement. The advantage of the proposed method lies with the fact that the various parameters required for the design of specific Microstrip antenna at a particular frequency of interest can be easily extracted without going into the rigorous time consuming, iterative design procedures using a costly software package. In this work, a general design procedure is suggested for the Microstrip antennas using artificial neural networks and this is demonstrated using the rectangular patch geometry.
Hi, im Perlis polytechnic student, and now i undergo last semester already. And i taken one interesting subject is CMOS IC design. So this is one of lab work that i uploading. Using L-Edit to design NAND gate.
This ppt is about full adder design using pass transistor logic. This circuit describe power reduction using proposed cell as standard element in technology library design for ultra low power. we provide guidance to m.tech students in thier final year research projects. We assist on IEEE projects to M.tech or PhD students. Students can contact us for VLSI Projects, Antenna Projects, MATLAB Projects
This presentation discusses the Lambda based design rules for drawing the layouts. The spacing between ltwo layers, extent if of overlap, minimum dimensions of each layer etc are decided by the lambda based design rules. the separation between metal and poly, poly and diffusion , width of metal etc
HFSS MICROSTRIP PATCH ANTENNA- ANALYSIS AND DESIGNShivashu Awasthi
ANALYSIS AND DESIGN OF MICROSTRIP SQUARE PATCH ANTENNA USING HFSS SIMULATION TOOL.
Its the Final Year Presentation at 75% of its full flow.
Hopefully It should Help..do leave your reviews and suggestions / queries.
Thanks.
The attached narrated power point presentation attempts to explain the methods of computation of total power loss and system rise time in a fiber optic link. The material will be useful for KTU final year B Tech students who prepare for the subject EC 405, Optical Communications.
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Estimation of Optimized Energy and Latency Constraint for Task Allocation in ...ijcsit
In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation
schemes which affect the performance of the system. In this paper we test the pre-existing proposed
algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic
and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The
proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life
application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing mapping algorithm spiral and crinkle and has shown better
reduction in the communication energy consumption and shows improvement in the performance of the
system. On performing experimental analysis of proposed algorithm results shows that average reduction
in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%.
Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and
Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of
cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.
Hi, im Perlis polytechnic student, and now i undergo last semester already. And i taken one interesting subject is CMOS IC design. So this is one of lab work that i uploading. Using L-Edit to design NAND gate.
This ppt is about full adder design using pass transistor logic. This circuit describe power reduction using proposed cell as standard element in technology library design for ultra low power. we provide guidance to m.tech students in thier final year research projects. We assist on IEEE projects to M.tech or PhD students. Students can contact us for VLSI Projects, Antenna Projects, MATLAB Projects
This presentation discusses the Lambda based design rules for drawing the layouts. The spacing between ltwo layers, extent if of overlap, minimum dimensions of each layer etc are decided by the lambda based design rules. the separation between metal and poly, poly and diffusion , width of metal etc
HFSS MICROSTRIP PATCH ANTENNA- ANALYSIS AND DESIGNShivashu Awasthi
ANALYSIS AND DESIGN OF MICROSTRIP SQUARE PATCH ANTENNA USING HFSS SIMULATION TOOL.
Its the Final Year Presentation at 75% of its full flow.
Hopefully It should Help..do leave your reviews and suggestions / queries.
Thanks.
The attached narrated power point presentation attempts to explain the methods of computation of total power loss and system rise time in a fiber optic link. The material will be useful for KTU final year B Tech students who prepare for the subject EC 405, Optical Communications.
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Estimation of Optimized Energy and Latency Constraint for Task Allocation in ...ijcsit
In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation
schemes which affect the performance of the system. In this paper we test the pre-existing proposed
algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic
and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The
proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life
application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing mapping algorithm spiral and crinkle and has shown better
reduction in the communication energy consumption and shows improvement in the performance of the
system. On performing experimental analysis of proposed algorithm results shows that average reduction
in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%.
Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and
Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of
cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.
Intrusion Detection and Countermeasure in Virtual Network Systems Using NICE ...IJERA Editor
The cloud computing has increased in many organizations. It provides many benefits in terms of low cost and accessibility of data. Ensuring the security of cloud computing is a major factor in the cloud computing environment, as users often store sensitive information with cloud storage providers but these providers may be untrusted. In this project we propose anIntrusion Detection and Countermeasure in Virtual Network Systems mechanism called NICE to prevent vulnerable virtual machines from being compromised in the cloud. NICE detects and mitigates collaborative attacks in the cloud virtual networking environment. The system performance evaluation demonstrates the feasibility of NICE and shows that the proposed solution can significantly reduce the risk of the cloud system from being exploited and abused by internal and external attackers.
Reconfigurable High Performance Secured NoC Design Using Hierarchical Agent-b...IJECEIAES
With the rapid increase in demand for high performance computing, there is also a significant growth of data communication that leads to leverage the significance of network on chip. This paper proposes a reconfigurable fault tolerant on chip architecture with hierarchical agent based monitoring system for enhancing the performance of network based multiprocessor system on chip against faulty links and nodes. These distributed agents provide healthy status and congestion information of the network. This status information is used for further packet routing in the network with the help of XY routing algorithm. The functionality of Agent is enhanced not only to work as information provider but also to take decision for packet to either pass or stop to the processing element by setting the firewall in order to provide security. Proposed design provides a better performance and area optimization by avoiding deadlock and live lock as compared to existing approaches over network design.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
Recent articles published in VLSI design & Communication SystemsVLSICS Design
International Journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Energy-aware strategy for data forwarding in IoT ecosystem IJECEIAES
The Internet of Things (IoT) is looming technology rapidly attracting many industries and drawing research attention. Although the scale of IoT-applications is very large, the capabilities of the IoT-devices are limited, especially in terms of energy. However, various research works have been done to alleviate these shortcomings, but the schemes introduced in the literature are complex and difficult to implement in practical scenarios. Therefore, considering the energy consumption of heterogeneous nodes in IoT eco-system, a simple energy-efficient routing technique is proposed. The proposed system has also employed an SDN controller that acts as a centralized manager to control and monitor network services, there by restricting the access of selfish nodes to the network. The proposed system constructs an analytical algorithm that provides reliable data transmission operations and controls energy consumption using a strategic mechanism where the path selection process is performed based on the remaining energy of adjacent nodes located in the direction of the destination node. The proposed energy-efficient data forwarding mechanism is compared with the existing AODV routing technique. The simulation result demonstrates that the protocol is superior to AODV in terms of packet delivery rate, throughput, and end-to-end delay.
LOAD BALANCED CLUSTERING WITH MIMO UPLOADING TECHNIQUE FOR MOBILE DATA GATHER...Munisekhar Gunapati
A three-layer framework is proposed for mobile data collection in wireless sensor networks, which includes the sensor layer, cluster head layer, and mobile collector (called SenCar) layer. The framework employs distributed load balanced clustering and dual data uploading, which is referred to as LBC-MIMO. The objective is to achieve good scalability, long network lifetime and low data collection latency. At the sensor layer, a distributed load balanced clustering (LBC) algorithm is proposed for sensors to self-organize themselves into clusters. In contrast to existing clustering methods, our scheme generates multiple cluster heads in each cluster to balance the work load and facilitate dual data uploading. At the cluster head layer, the inter-cluster transmission range is carefully chosen to guarantee the connectivity among the clusters. Multiple cluster heads within a cluster cooperate with each other to perform energy-saving inter-cluster communications. Through inter-cluster transmissions, cluster head information is forwarded to SenCar for its moving trajectory planning. At the mobile collector layer, SenCar is equipped with two antennas, which enables two cluster heads to simultaneously upload data to SenCar in each time by utilizing multi-user multiple-input and multiple-output (MU-MIMO) technique. The trajectory planning for SenCar is optimized to fully utilize dual data uploading capability by properly selecting polling points in each cluster. By visiting each selected polling point, SenCar can efficiently gather data from cluster heads and transport the data to the static data sink. Extensive simulations are conducted to evaluate the effectiveness of the proposed LBC-MIMO scheme. The results show that when each cluster has at most two cluster heads, LBC-MIMO achieves over 50 percent energy saving per node and 60 percent energy saving on cluster heads comparing with data collection through multi-hop relay to the static data sink, and 20 percent shorter data collection time compared to traditional mobile data gathering.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Fundamentals of Electric Drives and its applications.pptx
Presentation
1. A Seminar on
Recent Trends in Analog Circuit Design using ANN
Submitted By:
MITESH KALAL
(P19VL003)
Supervisor:
DEEPAK JOSHI
Assistant Professor, ECED
DEPARTMENT OF ELECTRONICS ENGINEERING
SARDAR V
ALLABHBHAI NA
TIONAL INSTITUTE OF TECHNOLOGY, SURAT
NOVEMBER 2020
2. Outline
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 2
Introduction
Analog Design Flow
ANN and Analog Circuit Design
Overview of ANN
Difficulties in Analog Circuit Design
Literature Survey
Summary
3. • Complexity of ICs is increasing day by
day.
• ICs or SoCs are implemented using
both Digital and Analog circuitry.
• Figure 1 represents the contrast
between the design efforts of analog
and digital blocks on SoCs or ICs [1].
• Designing of Analog part takes longer
time than Digital [2].
Introduction
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 3
Figure 1: Contrast between analog and digital blocks’ design effort
[1]. N. Lourenço, R. Martins, N. Horta,” Automatic Analog IC Sizing and Optimization
Constrained with PVT Corners and Layout Effects,” (Springer, 2017)
[2] R. Martins, N. Lourenço, N. Horta, “Analog Integrated Circuit Design Automation—Placement, Routing and Parasitic Extraction Techniques,” (Springer, Berlin, 2017)
4. Analog Design Flow
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 4
Figure 2: Design tasks of analog design flow
[1]. N. Lourenço, R. Martins, N. Horta,” Automatic Analog IC Sizing and Optimization
Constrained with PVT Corners and Layout Effects,” (Springer, 2017)
5. Overview of ANN
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 5
• ANN is a collection of connected neurons(nodes) shown in
Figure 4.
• A neuron sums its weighted inputs, passes that results through
a function called activation function and outputs that value.
• The process carried out by neuron in an ANN is shown in
Figure 5.
Figure 4: Representation of an artificial neuron
[3] K. Hornik, M. Stinchcombe, H. White, “Multilayer
feedforward networks are universalapproximators,” Neural
Netw. 2(5), 359–366 (1989)
Figure 5: Process carried by neuron in a Neural Network
[4] The Complete Guide to Artificial Neural Networks: Concepts and Models. Retrieved from: https://missinglink.ai/guides/neural-network-concepts/complete-guide-artificial-
neural-networks/ (November 2020)
6. Overview of ANN…
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 6
• Figure 6 shows the ANN with 2 hidden layers with all the training process.
Figure 6: ANN with 2 hidden layers
[P.C. : https://www.slideshare.net/ashokktiwari/ann-load-forecasting]
7. Activation Function and their Derivatives
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 7
• Activation Function determines
the output of the neural network.
• It is attached with each neuron to
decide whether the node should
be activated or not depending on
the input parameters.
• Derivatives of Activation
Functions are used for back
propagation to update the weights
of the neuron.
• Figure 7 shows the different
activation functions. Figure 7: Activation Functions
[https://engmrk.com/activation-function-for-dnn/]
8. • ML is the process in which a computer improves its capabilities through
the analysis of past experiences.
• Recent developments in ML opens a new research in EDA tools for
analog IC design.
• ANNs are capable of solving analog IC sizing as a direct map from
specifications to the device sizes [5].
• Using ANNs automation of two design tasks of an analog IC can be done:
1) Circuit Sizing
2) Placement
ANN and Analog Circuit Design
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 8
9. ANN for Circuit Sizing
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 9
Figure 8: Circuit Sizing using ANN
[5] João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins and Nuno C. C. Lourenço,” Using Artificial Neural Networks for Analog Integrated Circuit Design Automation,” (Springer, 2019)
10. ANN for Placement
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 10
Figure 8: ANN for Placement
[5] João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins and Nuno C. C. Lourenço,” Using Artificial Neural Networks for Analog Integrated Circuit Design Automation,” (Springer, 2019)
11. • Lack of systematic design flows supported by EDA tools.
• Integration of analog circuits using technologies optimized for digital
circuits.
• Difficulty in reusing analog blocks because they are sensitive to
surrounding circuitry and environmental and process variations.
• As the technology is scaling down square law equation is not followed
and thus optimization is difficult.
Difficulties in Analog Circuit Design
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 11
12. Sr. no. Paper Paper Description
[1] G. İslamoğlu, T. O. Çakici, E. Afacan and G.
Dündar, "Artificial Neural Network Assisted Analog
IC Sizing Tool," 2019 16th International Conference
on Synthesis, Modeling, Analysis and Simulation
Methods and Applications to Circuit Design
(SMACD), Lausanne, Switzerland, 2019, pp. 9-12,
doi: 10.1109/SMACD.2019.8795293.
• This paper proposes utilization of neural networks to estimate circuit performance
and hence, reduce the execution time.
• Two circuits, Single stage current mirror based differential amplifier and folded
cascode OTA are taken for case study.
[2] A. Jafari, S. Sadri and M. Zekri, "Design
optimization of analog integrated circuits by using
artificial neural networks," 2010 International
Conference of Soft Computing and Pattern
Recognition, Paris, 2010, pp. 385-388, doi:
10.1109/SOCPAR.2010.5686736.
• In this paper neural network is used in order to find a set of circuit parameters
such that the design objectives are optimized while satisfying performance
constraints for different Op-Amp topologies.
[3] N. Kahraman and T. Yildirim, "Technology
independent circuit sizing for fundamental analog
circuits using artificial neural networks," 2008
Ph.D. Research in Microelectronics and
Electronics, Istanbul, 2008, pp. 1-4, doi:
10.1109/RME.2008.4595710.
• In this paper ANN is trained with data of different technologies to give the
transistor sizes of circuit for an unknown technology that has not been trained
before.
• Trained technologies: 1.5um, 0.5um, 0.35um, 0.25um. Test Technology: 0.18um
[4] Qi-Jun Zhang, K. C. Gupta and V. K.
Devabhaktuni, "Artificial neural networks for RF
and microwave design - from theory to practice,"
in IEEE Transactions on Microwave Theory and
Techniques, vol. 51, no. 4, pp. 1339-1350, April
2003, doi: 10.1109/TMTT.2003.809179.
• In this paper ANN is used to design and optimize RF and microwave circuits.
Neural networks are trained to learn the behavior of passive/active
components/circuits.
Literature Survey
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 12
13. Literature Survey
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 13
Ref. no. Author Paper Description
[5] M. Seok, M. Yang, Z. Jiang, A. A. Lazar and J. Seo,
"Cases for Analog Mixed Signal Computing
Integrated Circuits for Deep Neural Networks,"
2019 International Symposium on VLSI Design,
Automation and Test (VLSI-DAT), Hsinchu,
Taiwan, 2019, pp. 1-2, doi: 10.1109/VLSI-
DAT.2019.8742044.
• In this paper, the emerging analog and mixed-signal circuit techniques to improve
energy efficiency using ANN are discussed.
• This paper has reviewed on two such techniques, one on the speech recognition
processor in hybrid analog and digital circuits and the other on the embedded
SRAM circuits that support analog-mixed-signal in-memory (in-bitcell)
computing for convolutional and deep neural networks.
[6] A. Viveros-Wacher and J. E. Rayas-Sánchez,
"Analog Fault Identification in RF Circuits using
Artificial Neural Networks and Constrained
Parameter Extraction," 2018 IEEE MTT-S
International Conference on Numerical
Electromagnetic and Multiphysics Modeling and
Optimization (NEMO), Reykjavik, 2018, pp. 1-3,
doi: 10.1109/NEMO.2018.8503117.
• Authors explain about fault diagnosis problem in analog circuits and an ANN
based modeling approach to efficiently emulate the injection of analog faults in
the circuits.
[7] Guerra, A. Canelas, R. Póvoa, N. Horta, N.
Lourenço and R. Martins, "Artificial Neural
Networks as an Alternative for Automatic Analog
IC Placement," 2019 16th International Conference
on Synthesis, Modeling, Analysis and Simulation
Methods and Applications to Circuit Design
(SMACD), Lausanne, Switzerland, 2019, pp. 1-4,
doi: 10.1109/SMACD.2019.8795267.
• Authors explain, use of ANNs for automation of the placement task of analog IC
layout design.
• ANNs were trained with the data of different layout structures of analog circuit
and gives different placement alternatives as output.
14. • Analog IC designing is not as fast as digital design.
• Many sources and technology are available for designing of digital circuits.
• For SoCs, designing of analog circuits is equally important as digital circuits.
• Designing of analog circuits takes longer time and less immune to noise compared to digital.
• As the circuit complexity increases the designing time and efforts increases.
• To reduce the designing time with less human efforts ANN is one of the prominent field for optimization in
analog IC designing.
• The network is trained with the data of previous simulations and used to optimize the circuit parameters and
size.
• ANN can also be trained for placement task in IC layout design.
• ANN has great scope in field of analog IC design automation for circuit sizing and placement.
Summary
December 6, 2021 Recent Trends in Analog Circuit Design Using ANN 14
15. [1] N. Lourenço, R. Martins, N. Horta,” Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects,” (Springer, 2017)
[2] R. Martins, N. Lourenço, N. Horta, “Analog Integrated Circuit Design Automation—Placement, Routing and Parasitic Extraction Techniques,” (Springer, Berlin, 2017)
[3] K. Hornik, M. Stinchcombe, H. White, “Multilayer feedforward networks are universalapproximators,” Neural Netw. 2(5), 359–366 (1989)
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