Optimization techniques are important in analog circuit design to minimize circuit size and maximize performance under constraints. Available techniques for optimization include classical methods, nature-inspired algorithms like particle swarm optimization and ant colony optimization, and learning-based optimization. Single-objective optimization aims to optimize a single metric like power or area, while multi-objective optimization aims to optimize multiple conflicting objectives simultaneously, such as power and speed.

1. Optimization Techniques in Analog Circuit Design
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2. OUTLINE
 Introduction to Optimization
Technique
 Why in Analog Circuit Design
 Available Techniques
 Single objective optimization
 Multi- objective optimization
 Reference
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Introduction
Analog Circuit Design.
Circuit Sizing
Need of Optimization Algorithm

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•The complexity of ICs is increasing day by day.
•ICs or SoCs are implemented using both Digital and Analog circuitry.
•Designing of Analog part is time consuming than Digital part.
•The contrast between the design efforts of analog and digital blocks on ICs
or SoCs .
Introduction…….

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%Area %Effort
Digital
Analog
• Why in Analog circuit design?

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Analog Circuit design as a mathematical
program

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Available Techniques
 Classical Methods
 Nature Inspired Algorithm
 Particle Swarm Optimization
 Firefly Algorithm
 Ant Colony Optimization
 Hybrid Algorithm
 Learning Based Optimization

8. Single-objective Optimization
• A Single-objective Optimization Problem (SOOP) has an
objective function, f(x) which has to be maximize or minimize
under a number of constraints g(x)’s. The generalized form of
the SOOP is expressed as:
Maximize f(x)
s.t. gj (x)≥0 (j=1…..m)
Where x is a vector of the n decision variables, x=(x1, x2, …, xn)
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9. Why Multi-objective Optimization?
Most optimization problems naturally have several objectives
to be achieved (normally conflicting with each other), but in
order to simplify their solution, they are treated as if they had
only one (the remaining objectives are normally handled as
constraints).
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10. 10
.
.
   
   
1
Minimize
Subject to 0, 1
k
M
m m
m
F x f x
h x k l


 



1
1
M
m
m
w



1 1 2 2 3 3
* * * ........... *
obj M M
F w F w F w F w F
  
where, M is the total number of objective functions. Total objective function in weighted sum
approach can be defined as
The mathematical definition of weighted sum method is
shown in Equation
F1 …FM are the individual objective functions which are to be optimized simultaneously.
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Weighted Sum Approach

11. References
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[1] Chang, C. P., J. H. Chen, S. H. Hung, C. C. Su, and Y. H. Wang, A novel post-
linearization technique for fully integrated 5.5 GHz high-linearity LNA," IEEE
Int. Innovative Computing, Information and Control Conf., 577-580, Kaohsiung,
Taiwan, December 2009.
[2] Low Noise and High Linearity LNA based on In GaP/GaAs HBT for 5.3 GHz
WLAN Seong-Sik Myoung , Sang-Hoon Cheon, Jong-Gwan Yook Dept.
of Electrical and Electronic Eng. Yonsei Univ., Seoul.
[3] Yuan-Kai Chu, Che-Hong Liao, and Huey-Ru Chuang, "5.7 GHz 0.18 /spl mu/m
CMOS gain controlled LNA and mixer for 802.11a WLAN applications," IEEE
Radio Frequency Integrated Circuits (RFIC) Symposium, pp.221–224, June 2003.
[4] M.K. Raja, T.T.C. Boon, K.N. Kumar, and W. S. Jau, "A fully integrated variable
gain 5.75- GHz LNA with on chip active balun for WLAN," 2003
IEEE Radio Integrated Circuits (RFIC) Symposium, pp. 439-442, June 2003.
[5] A5.8-GHz Two-Stage High-Linearity Low-Voltage Low Noise Amplifier in a
0.35-pm Technology Ren-Chieh Liu, Chung-Rung Lee, Huei Wang and Chomg
-Kuang Wang Dept. of Electrical Engineering, National Taiwan University Taipei,
Taiwan, Republic of China
[6] C. Xin and E. Sánchez-Sinencio, “A linearization technique for RF low noise
amplifier,” in Proc. IEEE Int. Circuits Syst. Symp., Vancouver,BC, Canada, May
2004, vol. IV, pp. 313– 316.
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12. References
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[7] N. Kim, V. Aparin, K. Barnett, and C. Persico, “A cellular-band CDMA
CMOS LNA linearized using active post-distortion,” IEEE J. Solid-
State Circuits, vol. 41, no. 7, pp. 1530–1534, Jul. 2006.
[8] Im , D., I. Nam, H. Kim, and K. Lee, A wideband CMOS low noise
amplifier employing noise and IM2 distortion cancellation for a digital
TV tuner,“ IEEE J. Solid- State Circuits, Vol. 44, 686-698, March 2009.
[9] Chang C-P, Chien W-C, Su C-C, Wang Y-H “Linearity improvement of
cascade CMOS LNA using a diode connected NMOS transistor with
parallel RC CKT” Progress In Electromagnetic Research C vol 17.pp29-
38 2010.
[10] T.-S. Kim and B.S.Kim , “Post-linearization of cascode CMOS LNA using
folded PMOS IMD sinker,” IEEE Microw. Wireless Comp. Lett., vol.
16, no. 4, pp. 182–184, Apr. 2006.
[11] H. Zhang, X. Fan, and E. Sánchez-Sinencio, “A low-power, linearized,
ultra- wideband LNA design technique,” IEEE J. Solid-State
Circuits, vol. 44, no. 2, pp. 320–330, Feb. 2009.
[12] V. Aparin, G. Brown, and L. E. Larson, “Linearization of CMOS LNAs via
optimum gate biasing,” in Proc. IEEE Int. Circuits Syst. Symp , Vancouver,
BC, Canada, May 2004, vol.4, pp. 748–751.
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[14] Ram Kumar, Anandini Devi, Abahan Sarkar, F.A.Talukdar, “Design of 5.5
GHz linear low noise amplifier using post distortion technique with
body biasing” Microsyst Technol DOI 10.1007/s00542-015-2556-x 2015.
[15] X. Fan, H. Zhang, and E. Sánchez-Sinencio, “A noise reduction and linearity
improvement technique for a differential cascode LNA,” IEEE.J. Solid-State
Circuits, Mar. 2008 pp. 588–599,.
[16] Mabrouki Aya, Taris Thierry, Deval Yann, Begueret Jean-Baptiste. IEEE“A
Very Low Voltage Low power CMOS Low Noise Amplifier with
Forward Body Bias “June 2010, pp.341-344.
[17] Yuan-Kai Chu, Che-Hong Liao, and Huey-Ru Chuang, "5.7 GHz 0.18 /spl
u/m CMOS gain-controlled LNA and mixer for 802.11a WLAN
applications, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June
2003, pp.221–224.
[18] H.-W.Chiu.S.-S.Lu and Y.-S.Lin, “A 2.17-dB NF 5-GHz-band monolithic
CMOS LNA with 10-mW dc power consumption”, IEEE Trans.Micro,
Theory Tech, Mar.2005, pp.813-824.
[19] M.K. Raja, T.T.C. Boon, K.N. Kumar, and W. S. Jau, "A fully integrated
variable gain 5.75-GHz LNA with on chip active balun for WLAN," IEEE
Radio Frequency Integrated Circuits (RFIC) Symposium, June 2003, pp. 439-
442.
References
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THANK YOU
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