The document provides an overview of various power converter topologies, including:
- Non-isolated converter topologies like boost, buck, and buck-boost converters and their isolated derivatives.
- Single-ended converter topologies like forward and flyback converters that use transformer reset techniques like reset winding and resonant reset.
- Double-ended topologies like push-pull, half-bridge, and full-bridge converters.
- It discusses the advantages of different topologies for applications like low, mid, and high power as well as operating modes like continuous and discontinuous conduction.
IC Design of Power Management Circuits (I)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
IC Design of Power Management Circuits (II)Claudia Sin
The document discusses various aspects of integrated circuit design for power management circuits. It covers control loop design including biasing circuits, oscillators, comparators and operational amplifiers. It also discusses power stage design such as power transistors, synchronous rectification and active diodes. Finally it discusses peripheral circuits including undervoltage lockout, overcurrent protection and soft start circuits. The document provides guidelines and examples for analog integrated circuit design of switching converters and related circuits.
This document discusses power bipolar transistors and power MOSFETs. It describes the vertical structure of power bipolar transistors which allows for higher current handling. Power transistors have lower current gain but larger safe operating areas bounded by maximum current, voltage and power limits to prevent damage. Power MOSFETs provide advantages over bipolar transistors like no second breakdown and stable performance over temperature. They have lower on-resistance and can switch large currents with small control currents. DMOS and VMOS structures are described for power MOSFETs.
The document discusses dc-dc converters and their functions. Dc-dc converters are used to (1) convert a dc input voltage into a regulated dc output voltage against variations, (2) reduce ac voltage ripple on the output, and (3) optionally provide isolation between the input and load. Common types of dc-dc converters include buck, boost, buck-boost, forward, push-pull, half-bridge, full-bridge, flyback, and Cuk converters.
A detailed step-by-step procedure for the design of a buck converter. Different active and passive components are selected as per the requirement specified in the design problem.
This document discusses switched-capacitor circuits. It begins by introducing the concept of using switched capacitors to emulate resistors and implement functions like integration. It then provides examples of basic switched-capacitor circuits like integrators. It discusses issues like noise and non-ideal effects in switched-capacitor circuits. It also provides examples of applications that use switched-capacitor circuits, such as filters, sigma-delta modulators, and pipelined ADCs.
1. The document introduces phase locked loops (PLLs), which are electronic circuits that lock the phase of the output signal to the phase of the input signal.
2. A basic PLL system consists of a phase detector that detects the phase difference between the input and output signals, a low pass filter, and a voltage controlled oscillator whose frequency is adjusted based on the output of the filter to reduce the phase difference.
3. Modern PLLs often use a phase/frequency detector and a charge pump instead of just a phase detector, which allows the loop to lock faster and be more stable. Charge pump PLLs work by using the phase/frequency detector to control switches that charge or discharge a capacitor, producing the control voltage
It contains POWER MOSFET INTRODUCTION, POWER MOSFET STRUCTURE, types of power MOSFET, symbols, output characteristics , applications etc. https://amzn.to/3x56Qro click here to buy GATE 2022 Electronics & Communication Engineering - 35 Years Topic-wise Previous Solved Papers
IC Design of Power Management Circuits (I)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
IC Design of Power Management Circuits (II)Claudia Sin
The document discusses various aspects of integrated circuit design for power management circuits. It covers control loop design including biasing circuits, oscillators, comparators and operational amplifiers. It also discusses power stage design such as power transistors, synchronous rectification and active diodes. Finally it discusses peripheral circuits including undervoltage lockout, overcurrent protection and soft start circuits. The document provides guidelines and examples for analog integrated circuit design of switching converters and related circuits.
This document discusses power bipolar transistors and power MOSFETs. It describes the vertical structure of power bipolar transistors which allows for higher current handling. Power transistors have lower current gain but larger safe operating areas bounded by maximum current, voltage and power limits to prevent damage. Power MOSFETs provide advantages over bipolar transistors like no second breakdown and stable performance over temperature. They have lower on-resistance and can switch large currents with small control currents. DMOS and VMOS structures are described for power MOSFETs.
The document discusses dc-dc converters and their functions. Dc-dc converters are used to (1) convert a dc input voltage into a regulated dc output voltage against variations, (2) reduce ac voltage ripple on the output, and (3) optionally provide isolation between the input and load. Common types of dc-dc converters include buck, boost, buck-boost, forward, push-pull, half-bridge, full-bridge, flyback, and Cuk converters.
A detailed step-by-step procedure for the design of a buck converter. Different active and passive components are selected as per the requirement specified in the design problem.
This document discusses switched-capacitor circuits. It begins by introducing the concept of using switched capacitors to emulate resistors and implement functions like integration. It then provides examples of basic switched-capacitor circuits like integrators. It discusses issues like noise and non-ideal effects in switched-capacitor circuits. It also provides examples of applications that use switched-capacitor circuits, such as filters, sigma-delta modulators, and pipelined ADCs.
1. The document introduces phase locked loops (PLLs), which are electronic circuits that lock the phase of the output signal to the phase of the input signal.
2. A basic PLL system consists of a phase detector that detects the phase difference between the input and output signals, a low pass filter, and a voltage controlled oscillator whose frequency is adjusted based on the output of the filter to reduce the phase difference.
3. Modern PLLs often use a phase/frequency detector and a charge pump instead of just a phase detector, which allows the loop to lock faster and be more stable. Charge pump PLLs work by using the phase/frequency detector to control switches that charge or discharge a capacitor, producing the control voltage
It contains POWER MOSFET INTRODUCTION, POWER MOSFET STRUCTURE, types of power MOSFET, symbols, output characteristics , applications etc. https://amzn.to/3x56Qro click here to buy GATE 2022 Electronics & Communication Engineering - 35 Years Topic-wise Previous Solved Papers
The document describes the operation of a series-resonant LLC half-bridge converter. It discusses the topology, key waveforms at different operating frequencies relative to the resonant frequency, and the operating sequence in each resonant mode through detailed circuit diagrams and explanations. Design examples are provided to illustrate the simplified analysis approach.
The document discusses transient analysis of first order differential equations that model circuits containing energy storage elements like capacitors and inductors. It explains that when the circuit conditions change, there will be a transient response before reaching the steady-state. The complete solution consists of the natural/homogeneous response and the particular/forced response. The natural response dies out over time, while the forced response depends on the external excitation. Circuits are solved using the time constant, which relates to how long it takes for the transient response to decay to the steady-state.
IC Design of Power Management Circuits (IV)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
Oscillators generate an output signal without an input signal by converting DC power to AC power. They produce periodic waveforms like sine, square, triangle, and sawtooth waves. The Wien bridge oscillator is a two-stage RC coupled amplifier circuit that is stable at its resonant frequency. It uses a feedback circuit of series and parallel RC networks to produce a phase shift. Monostable multivibrators have one stable and one quasi-stable state. They switch to the quasi-stable state when triggered externally and return to the stable state after a set time period determined by resistor-capacitor values in the circuit.
1. An inverter refers to a power electronic device that converts DC input voltages to AC output voltages at the required magnitude and frequency.
2. There are three basic types of dc-ac converters depending on their AC output waveform: square wave, modified sine wave, and pure sine wave.
3. Inverters have applications in adjustable speed AC drives, electric vehicles, induction heating, aircraft power supplies, photovoltaic systems, UPS, and air conditioning units.
The document outlines the key topics in a presentation on bipolar junction transistors, including:
- The formation of NPN and PNP junctions and the operation of NPN transistors.
- The three transistor circuit configurations - common base, common emitter, and common collector - and their current gain characteristics.
- Expressions for collector current and concepts like reverse saturation current and ICEO.
- Static characteristics like input and output characteristics are examined for each configuration.
This document describes a buck converter subsystem and current sensing techniques. It contains the following key points:
1. The objective is to efficiently step down DC voltage while reducing ripple to produce a smooth output voltage, and to measure the inductor current.
2. The subsystem includes a circuit configuration, components, design equations, and current waveforms. Techniques for current sensing include simplified and advanced methods.
3. An advanced current sensing model uses a simplified inductor model with a parasitic resistance and capacitor to determine the inductor current based on the voltage across a sensing capacitor. Assumptions are provided for component values and tolerances.
Eeg381 electronics iii chapter 2 - feedback amplifiersFiaz Khan
This document discusses feedback amplifiers and the four basic feedback topologies:
1) Series-shunt feedback for voltage amplifiers
2) Shunt-series feedback for current amplifiers
3) Series-series feedback for transconductance amplifiers
4) Shunt-shunt feedback for transresistance amplifiers
It also covers negative feedback voltage amplifiers, including calculating closed-loop gain, gain desensitivity, and bandwidth extension due to feedback. An example problem is worked through to demonstrate these concepts.
IC Design of Power Management Circuits (III)Claudia Sin
This document discusses stability and compensation techniques for switching converters. It begins by introducing feedback systems and stability criteria such as the Nyquist criterion and Bode plots. It then examines loop gain functions of different orders and their impact on stability and transient response. Several common compensation techniques are described, including type I, II, and III compensators. The document concludes by discussing stability evaluation based on line and load transients and current mode pulse width modulation with compensation ramps.
This document discusses different types of DC-DC converters, specifically focusing on buck converters. It describes how buck converters work by using a switch to chop the input voltage and an inductor and capacitor to provide steady output voltage. The duty cycle of the switch controls the output voltage. Buck converters can operate in continuous or discontinuous conduction mode depending on the inductor value and duty cycle. Design considerations include selecting components to reduce ripple voltage and ensure continuous conduction.
The document describes a new load network configuration for class F power amplifiers. The proposed network consists of parallel open and short circuited λ/8 stubs and a T-section transformer. It is designed to control harmonic impedances for high efficiency. A 10W class F power amplifier at 500MHz was designed using GaN HEMT to demonstrate the approach, simulating 84% DC-RF efficiency with 11dB gain over a 100MHz bandwidth.
A flyback converter is a type of switch mode power supply that uses a transformer to transfer energy from the input to the output. It operates by storing energy in the transformer during the on-time of the primary switch, and releasing this energy to the output during the off-time when a diode is conducting. Flyback converters provide galvanic isolation between the input and output through the use of the transformer. They can operate in discontinuous conduction mode where the transformer fully demagnetizes during each switching cycle.
This document discusses transmission line basics and provides an overview of key concepts. It introduces transmission line equivalent circuits and relevant equations. The document outlines the agenda, which includes discussing the transmission line concept, equivalent circuits, reflection diagrams, loading, termination methods, propagation delay, and simple return paths. It also discusses two viewpoints of transmission lines - steady state in the frequency domain and transient in the time domain.
Human: Thank you for the summary. Summarize the following document in 3 sentences or less:
[DOCUMENT]
Transmission Line Basics II - Class 6
Prerequisite Reading assignment: CH2
TARA SAIKUMAR
2
Real Computer Issues
A chopper, also known as a DC-DC converter, is a static device that is used to obtain a variable DC voltage from a constant DC voltage source. Choppers are widely used in applications like trolley cars, battery vehicles, motor control, and regenerative braking of DC motors. There are two types - step-down choppers that produce an output voltage lower than the input voltage, and step-up choppers that produce a higher output voltage. A step-down chopper works by using a thyristor switch to alternately connect and disconnect the load from the power supply voltage, generating a chopped output voltage waveform. Choppers are classified into different classes including Class A, B, C, D,
IC Design of Power Management Circuits (I)Claudia Sin
This document provides an overview of a tutorial on integrated circuit design of power management circuits. The tutorial covers topics such as switching converters, including fundamentals and control techniques; bandgap references; charge pumps; and low dropout regulators. It lists these topics along with brief descriptions in an agenda. It then begins discussing switching converters in more detail, covering concepts such as steady state analysis, lossless elements, buck, boost and buck-boost converter topologies, volt-second balance, continuous and discontinuous conduction modes, and efficiency calculations.
This document discusses buck converters, which are dc-to-dc converters that step down voltage from a constant dc source. It describes two modes of operation for buck converters: continuous conduction mode (CCM) and discontinuous conduction mode (DCM). CCM occurs when inductor current flows continuously, while DCM occurs when inductor current falls to zero for a period during each switching cycle. The document provides equations to calculate operating characteristics like output voltage and efficiency based on component values and switching duty cycle.
The document discusses different types of DC-DC converters, including step-down buck converters which lower voltage, step-up boost converters which raise voltage, and buck-boost converters which can lower or raise voltage. It provides information on buck converters over pages 7-9 and step-up boost converters over pages 10-12 before discussing buck-boost converters from pages 13-15.
TI’s Next Great Leap: Introducing the NexFET™ 100V Power MOSFETs!Design World
The document discusses Texas Instruments' new NexFET 100V power MOSFETs. It provides details on the technology and advantages of NexFETs, including excellent thermal performance. It then gives examples of how NexFETs can be used in applications like power supplies, motor control, and AC-DC converters. Data sheets and specifications are provided for various NexFET parts suitable for voltages ranging from 40V to 100V.
Naturally clamped zero current commutated soft-switching current-fed push–pul...LeMeniz Infotech
Naturally clamped zero current commutated soft-switching current-fed push–pull dcdc converter analysis, design, and experimental results
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
The document describes the operation of a series-resonant LLC half-bridge converter. It discusses the topology, key waveforms at different operating frequencies relative to the resonant frequency, and the operating sequence in each resonant mode through detailed circuit diagrams and explanations. Design examples are provided to illustrate the simplified analysis approach.
The document discusses transient analysis of first order differential equations that model circuits containing energy storage elements like capacitors and inductors. It explains that when the circuit conditions change, there will be a transient response before reaching the steady-state. The complete solution consists of the natural/homogeneous response and the particular/forced response. The natural response dies out over time, while the forced response depends on the external excitation. Circuits are solved using the time constant, which relates to how long it takes for the transient response to decay to the steady-state.
IC Design of Power Management Circuits (IV)Claudia Sin
by Wing-Hung Ki
Integrated Power Electronics Laboratory
ECE Dept., HKUST
Clear Water Bay, Hong Kong
www.ee.ust.hk/~eeki
International Symposium on Integrated Circuits
Singapore, Dec. 14, 2009
Oscillators generate an output signal without an input signal by converting DC power to AC power. They produce periodic waveforms like sine, square, triangle, and sawtooth waves. The Wien bridge oscillator is a two-stage RC coupled amplifier circuit that is stable at its resonant frequency. It uses a feedback circuit of series and parallel RC networks to produce a phase shift. Monostable multivibrators have one stable and one quasi-stable state. They switch to the quasi-stable state when triggered externally and return to the stable state after a set time period determined by resistor-capacitor values in the circuit.
1. An inverter refers to a power electronic device that converts DC input voltages to AC output voltages at the required magnitude and frequency.
2. There are three basic types of dc-ac converters depending on their AC output waveform: square wave, modified sine wave, and pure sine wave.
3. Inverters have applications in adjustable speed AC drives, electric vehicles, induction heating, aircraft power supplies, photovoltaic systems, UPS, and air conditioning units.
The document outlines the key topics in a presentation on bipolar junction transistors, including:
- The formation of NPN and PNP junctions and the operation of NPN transistors.
- The three transistor circuit configurations - common base, common emitter, and common collector - and their current gain characteristics.
- Expressions for collector current and concepts like reverse saturation current and ICEO.
- Static characteristics like input and output characteristics are examined for each configuration.
This document describes a buck converter subsystem and current sensing techniques. It contains the following key points:
1. The objective is to efficiently step down DC voltage while reducing ripple to produce a smooth output voltage, and to measure the inductor current.
2. The subsystem includes a circuit configuration, components, design equations, and current waveforms. Techniques for current sensing include simplified and advanced methods.
3. An advanced current sensing model uses a simplified inductor model with a parasitic resistance and capacitor to determine the inductor current based on the voltage across a sensing capacitor. Assumptions are provided for component values and tolerances.
Eeg381 electronics iii chapter 2 - feedback amplifiersFiaz Khan
This document discusses feedback amplifiers and the four basic feedback topologies:
1) Series-shunt feedback for voltage amplifiers
2) Shunt-series feedback for current amplifiers
3) Series-series feedback for transconductance amplifiers
4) Shunt-shunt feedback for transresistance amplifiers
It also covers negative feedback voltage amplifiers, including calculating closed-loop gain, gain desensitivity, and bandwidth extension due to feedback. An example problem is worked through to demonstrate these concepts.
IC Design of Power Management Circuits (III)Claudia Sin
This document discusses stability and compensation techniques for switching converters. It begins by introducing feedback systems and stability criteria such as the Nyquist criterion and Bode plots. It then examines loop gain functions of different orders and their impact on stability and transient response. Several common compensation techniques are described, including type I, II, and III compensators. The document concludes by discussing stability evaluation based on line and load transients and current mode pulse width modulation with compensation ramps.
This document discusses different types of DC-DC converters, specifically focusing on buck converters. It describes how buck converters work by using a switch to chop the input voltage and an inductor and capacitor to provide steady output voltage. The duty cycle of the switch controls the output voltage. Buck converters can operate in continuous or discontinuous conduction mode depending on the inductor value and duty cycle. Design considerations include selecting components to reduce ripple voltage and ensure continuous conduction.
The document describes a new load network configuration for class F power amplifiers. The proposed network consists of parallel open and short circuited λ/8 stubs and a T-section transformer. It is designed to control harmonic impedances for high efficiency. A 10W class F power amplifier at 500MHz was designed using GaN HEMT to demonstrate the approach, simulating 84% DC-RF efficiency with 11dB gain over a 100MHz bandwidth.
A flyback converter is a type of switch mode power supply that uses a transformer to transfer energy from the input to the output. It operates by storing energy in the transformer during the on-time of the primary switch, and releasing this energy to the output during the off-time when a diode is conducting. Flyback converters provide galvanic isolation between the input and output through the use of the transformer. They can operate in discontinuous conduction mode where the transformer fully demagnetizes during each switching cycle.
This document discusses transmission line basics and provides an overview of key concepts. It introduces transmission line equivalent circuits and relevant equations. The document outlines the agenda, which includes discussing the transmission line concept, equivalent circuits, reflection diagrams, loading, termination methods, propagation delay, and simple return paths. It also discusses two viewpoints of transmission lines - steady state in the frequency domain and transient in the time domain.
Human: Thank you for the summary. Summarize the following document in 3 sentences or less:
[DOCUMENT]
Transmission Line Basics II - Class 6
Prerequisite Reading assignment: CH2
TARA SAIKUMAR
2
Real Computer Issues
A chopper, also known as a DC-DC converter, is a static device that is used to obtain a variable DC voltage from a constant DC voltage source. Choppers are widely used in applications like trolley cars, battery vehicles, motor control, and regenerative braking of DC motors. There are two types - step-down choppers that produce an output voltage lower than the input voltage, and step-up choppers that produce a higher output voltage. A step-down chopper works by using a thyristor switch to alternately connect and disconnect the load from the power supply voltage, generating a chopped output voltage waveform. Choppers are classified into different classes including Class A, B, C, D,
IC Design of Power Management Circuits (I)Claudia Sin
This document provides an overview of a tutorial on integrated circuit design of power management circuits. The tutorial covers topics such as switching converters, including fundamentals and control techniques; bandgap references; charge pumps; and low dropout regulators. It lists these topics along with brief descriptions in an agenda. It then begins discussing switching converters in more detail, covering concepts such as steady state analysis, lossless elements, buck, boost and buck-boost converter topologies, volt-second balance, continuous and discontinuous conduction modes, and efficiency calculations.
This document discusses buck converters, which are dc-to-dc converters that step down voltage from a constant dc source. It describes two modes of operation for buck converters: continuous conduction mode (CCM) and discontinuous conduction mode (DCM). CCM occurs when inductor current flows continuously, while DCM occurs when inductor current falls to zero for a period during each switching cycle. The document provides equations to calculate operating characteristics like output voltage and efficiency based on component values and switching duty cycle.
The document discusses different types of DC-DC converters, including step-down buck converters which lower voltage, step-up boost converters which raise voltage, and buck-boost converters which can lower or raise voltage. It provides information on buck converters over pages 7-9 and step-up boost converters over pages 10-12 before discussing buck-boost converters from pages 13-15.
TI’s Next Great Leap: Introducing the NexFET™ 100V Power MOSFETs!Design World
The document discusses Texas Instruments' new NexFET 100V power MOSFETs. It provides details on the technology and advantages of NexFETs, including excellent thermal performance. It then gives examples of how NexFETs can be used in applications like power supplies, motor control, and AC-DC converters. Data sheets and specifications are provided for various NexFET parts suitable for voltages ranging from 40V to 100V.
Naturally clamped zero current commutated soft-switching current-fed push–pul...LeMeniz Infotech
Naturally clamped zero current commutated soft-switching current-fed push–pull dcdc converter analysis, design, and experimental results
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
PID Compensator Control Scheme of Synchronous Buck DC-DC Converter with ZVS L...IJRES Journal
This paper deals with PID compensator control of Synchronous Rectifier (SR) Buck Converter to improve its conversion efficiency under different load conditions with the help of a Zero Voltage Switching(ZVS)Logic Circuit. Since the freewheeling diode is replaced by a high frequency switch MOSFET in this buck configuration, the SR control technique itself will be sufficient under heavy load condition to attain better normal mode performance. However, this technique does not hold well in light load condition, due to increased switching losses. A newPID compensator control techniqueis introduced in the paper will enable synchronous buck converter to realize ZVS, while feeding light load. This is also cost effective and highly efficient simple control method without use of extra auxiliary switches and RLC components. This control technique also proved to be efficient under input voltage variations. Simulation is done for proving stabilization provided by the PID compensator with the help of ZVS logic circuit for synchronous rectifier (SR) buck converter in MATLAB Simulink.
An integrated boost resonant converter for photovoltaic applicationsAsoka Technologies
Effective photovoltaic power conditioning requires efficient power conversion and accurate maximum power point tracking to counteract the effects of panel mismatch, shading, and general variance in power output during a daily cycle. In this paper, the authors propose an integrated boost resonant converter with low component count, galvanic isolation, simple control, as well as
high efficiency across a wide input and load range. Provided is a discussion of the converter synthesis, key operational features, converter design procedure, and loss analysis, as well as experimental verification by way of a 250-W prototype with a California Energy Commission efficiency of 96.8%.
PG Embedded Systems
www.pgembeddedsystems.com
#197 B, Surandai Road
Pavoorchatram,Tenkasi
Tirunelveli
Tamil Nadu
India 627 808
Tel:04633-251200
Mob:+91-98658-62045, +91-7598462045.
General Information and Enquiries:
g12ganesh@gmail.com
The document provides information on the FL7701 LED driver IC from Fairchild Semiconductor, including its features, typical applications, and demonstration of its use in a PAR20 LED bulb. Key points:
- The FL7701 is a smart LED driver IC with digital PFC, self biasing, overcurrent protection, and analog dimming capabilities.
- Typical applications include low-power LED lamps, luminaires, decorative lighting, and dimmable desk lamps.
- A demo board was modified to drive the LEDs in a Utilitech PAR20 bulb to demonstrate the FL7701's performance, achieving 72.6% efficiency with 0.82 power factor.
- Waveforms and
LED Streetlight APEC Demo Performance_SMappus 03062013 AC 12 Mar 2013Steve Mappus
This document provides specifications and design details for a 100W LED power supply using Fairchild semiconductor components. The power supply uses a BCM PFC controller and boost follower for wide input voltage range of 80-310VAC. A 2-switch flyback converter provides constant current or constant voltage output to 1 or 4 LED channels. Control and protection ICs are also detailed to balance current across multiple LED strings.
This document provides a user guide for the FEBFAN9611_S01U300A evaluation board featuring the FAN9611 300W interleaved dual-BCM low-profile PFC controller. The evaluation board is optimized for demonstrating the FAN9611's efficiency and protection features in a 300W design with less than 18mm profile. Safety precautions are provided for testing the board, which produces lethal voltages. Key features, specifications, test procedures, schematic, BOM and test results are documented.
This document provides instructions for demonstrating a FAN7688 demo configuration at APEC 2015. The demo uses a FAN7688 evaluation board (EVB) with secondary-side SR control operating at 12.5V output from 330-410V input and up to 20A output. Diagrams and instructions explain how to connect oscilloscopes, power supplies and loads to the EVB and how to safely power up and down the demo. Contact information is provided for technical support.
This document provides a user guide for the FEBFAN7688_I00250A evaluation board, which allows testing of the FAN7688 LLC resonant controller. The evaluation board operates from 300-450V input and regulates the output to 12.5V at up to 20A. The guide describes the board features, specifications, test procedures, schematic, and test data results for startup, efficiency, regulation, and protection functions.
This document provides an overview of driving high-brightness LEDs in high-power industrial lighting fixtures. It discusses high-brightness LED characteristics, system requirements, and LED driver topologies including single-stage versus two-stage designs and LED load control using parallel LED strings. It also presents a 100W industrial LED design example, including power stage calculations and test results. Key aspects covered include high-power industrial LED applications, HB-LED electrical characteristics, CC-CV driver operation, single and two-stage driver topologies, LED string control methods, and a detailed two-stage flyback LED driver design procedure and specifications.
Wide Vin DC/DC Converters: Reliable Power for Demanding ApplicationsDesign World
The document discusses wide input voltage (wide Vin) DC-DC converters, highlighting their use in industrial, automotive, and communications systems where input voltages can vary widely and experience transients. It presents challenges faced in these applications and how Texas Instruments' wide Vin controllers and integrated modules address issues like reliability across voltage ranges, overload protection, and high power density with low EMI. Examples are given of wide Vin solutions for isolated bias supplies, boost converters, and automotive systems dealing with start-stop events and battery voltage variations.
(1) Current shaping strategies for buck power factor correction converters are discussed. (2) Sine-squared modulation is analyzed where the average inductor current is shaped to follow a sine-squared waveform to improve the power factor. (3) The K-value, which determines the conduction angle and power factor, is analyzed and its impact on the harmonic content of the input current is shown, with various harmonics either meeting or violating Class C and Class D emission standards based on the K-value.
A phase shifted semi-bridgeless boost power factor corrected converter for PHEVsMurray Edington
The document proposes a phase shifted semi-bridgeless boost power factor corrected converter for plug-in hybrid electric vehicle battery chargers. It aims to improve efficiency at light loads and low lines compared to conventional boost, bridgeless boost, and interleaved boost topologies. The proposed topology introduces two slow diodes to link the ground of the power factor correction stage to the input line while maintaining many advantages of existing solutions. Experimental results on a prototype show a power factor over 0.99 from 750W to 3.4kW, total harmonic distortion less than 5% from half to full load, and peak efficiency of 98.6% at 240V input and 1kW load, verifying the proposed topology.
Quasi-resonant Flyback Converter Simulations with Saber - APEC 2016Alan Courtay
This tutorial shows Saber applied to the modeling and simulation of a common AC/DC power converter topology. The automation available in the Saber environment allows the converter to be thoroughly verified and regression-tested over a broad range of operating conditions.
APEC 2010 ACDC Live Demo Tech SessionPresentation_Feb 19 2010Steve Mappus
The document describes a 300W AC-DC power supply design using Fairchild semiconductor components. It uses an interleaved boost PFC converter with the FAN9612 controller to regulate the output to 390VDC with over 90% efficiency. A 300W asymmetrical half-bridge DC-DC converter with the FSFA2100 controller then converts the 390VDC to a 12VDC output with over 92% total efficiency. Design waveforms and performance data are provided to show the operation and benefits of the interleaved PFC and DC-DC converter topology.
This document describes the operation and modeling of one-switch and two-switch flyback converters. It discusses the ideal and non-ideal cases, comparing the circuits with and without parasitic components. The one-switch converter has issues with resonance from leakage inductance, while the two-switch topology clamps voltages and recycles leakage energy. Simulation models of the circuits are presented, showing the effects of parasitic capacitances and inductances. Component mismatches and their impacts are also analyzed. Finally, losses including conduction, forward voltage, and switching are calculated and compared between the converter designs.
Design of DC-DC Converter for SMPS with Multiple isolated outputs.Prajwal M B Raj
This document describes the design of a DC-DC converter for a switched mode power supply (SMPS) with multiple isolated outputs. It discusses different DC-DC converter topologies including SEPIC, flyback, and forward converters. Simulation results are presented for each converter providing 12V, 5V and 3.3V outputs from a 200-400V input. A closed loop control circuit with PI controller is designed and simulated for the SEPIC converter, showing improved regulation over open loop operation.
This document provides an overview of output amplifiers, including their requirements, types, and circuit implementations. It discusses Class A amplifiers and their limitations in efficiency and distortion. Class A source followers are introduced as a way to reduce output resistance and attenuation. Push-pull amplifiers are also mentioned as being able to both sink and source current. Circuit analysis is provided for small-signal models, voltage gains, frequency responses, and output characteristics of these different amplifier configurations.
This document summarizes high speed comparators. It discusses how the speed of comparators is limited by either linear response or slew rate. Techniques to maximize speed include increasing sourcing/sinking currents, optimizing the number of stages in cascaded amplifiers, and using a preamplifier followed by a latch. An example calculates the minimum propagation delay of a comparator consisting of an amplifier cascaded with a latch. The summary maximizes essential information while keeping within 3 sentences.
The document discusses the CMOS inverter, including its basic structure and operation, transient response characteristics, voltage transfer curve, propagation delay, and design considerations for improving performance such as minimizing delay. It provides analysis of how varying factors like transistor widths, supply voltage, and load capacitance affect the inverter's switching threshold, rise/fall times, and propagation delay. The goal of the analysis is to determine the optimal transistor width ratios and device parameters needed to design a high-performance symmetric CMOS inverter with minimum total propagation delay.
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1) DC-DC converters control the output voltage by converting the unregulated DC input voltage to a regulated DC output voltage. Switching regulators have near zero power loss by rapidly opening and closing a switch to transfer power from input to output in pulses.
2) A buck converter is a type of step-down DC-DC converter that produces an output voltage lower than the input voltage. It contains a switch, diode, and inductor. The inductor current ripples between a maximum and minimum value depending on the duty cycle of the switch.
3) Key parameters in buck converter design include duty cycle, switching frequency, inductor value, and capacitor value. These are selected to achieve the desired output voltage
2. 2
Agenda
Non Isolated Converter Topologies and Their Isolated DC/DC Derivatives
• PFC Boost
• Buck
• Buck-Boost
Single Ended Converter Topologies
• Transformer Reset Techniques
• Forward Converter
• Flyback Converter
Double Ended Converter Topologies
• Push Pull
• Half Bridge
• Full Bridge
• Phase Shifted Full Bridge
Synchronous Rectification
• Current Doubler Rectifier
3. 3
DOUBLE-ENDEDSINGLE-ENDED
ACTIVE CLAMP
2-SWITCH
PUSH-PULL
HALF BRIDGE
FULL BRIDGE
LOW POWER (<100W)
MID-POWER (100W-500W)
HIGH-POWER (>500W)
HARD SWITCHED
ZVT/PHASE SHIFT
NON-ISOLATED
ISOLATED
D
V
V
i
O
=
DV
V
i
O
−
=
1
1
FORWARD
D
D
V
V
i
O
−
−=
1
SINGLE-ENDED
FLYBACK
BOOST BUCK-BOOST BUCK
ACTIVE CLAMP
2-SWITCH
LLC
Isolated Power Topology Derivatives
8 “Mainstream” Topologies
Non-Isolated
1. Boost
2. Buck-Boost
3. Buck
Isolated
4. Flyback
5. Forward
6. Push-Pull
7. Half Bridge
8. Full Bridge
4. 4
Other Topologies?
Numerous Variations Exist
• Sepic
• Cuk
• Current Fed Buck
• Tapped Inductors
• Multiple Outputs
• Interleaving
• More?
Different Ways to Operate Them
• Voltage Mode Control
• Current Mode Control
• Digital Control
• Variable Frequency
• CCM, DCM, BCM
• ZVS
• ZCS
• Synchronous Rectification
Some Practical Converter Topology Advice
• Most power conversion requirements can be met using one or more of the 8 mainstream topologies
• Save more difficult topologies for unique application requirements
• Beware of publications proclaiming the “best” topology
5. 5
AC Line
85V<VAC<265V
VDC=400V 400V to 48V Bus Converter
VPOL_1<5V
VPOL_N<5V
48V to 12V IBC (Intermediate Bus Converter)
Telecom Rectifier
Multi-Stage Topology
Typical Distributed Power System
High Power DC/DCPFC Boost
POLDCDCPFCSYS ηηηηη ×××=
%9.84%96%95%95%98 =×××=SYSη
Scalable, efficient, complex protection functions, sequencing,
redundancy, digital control, etc
Efficiency example:
POL DC/DC
7. 7
Boost Converter
Most popular topology for Power Factor Correction
• Simple power stage
• Efficient energy storage
• Continuous input current waveform
• VIN<VOUT
Operating modes
• CCM – fixed frequency, best PF and THD, Any Power Level
• BCM – variable frequency, good PF and THD, <300W
• DCM – never used intentionally but unavoidable at light load
Usually power factor correction capability is lost
AC
LINE
VB
EMI
Filter
DC/DC
VLOAD
8. 8
Boost Converter
VGS(Q)
VDS(Q)
IL
IDS(Q)
ID
VOUT
BCM
tON tOFF
TS
𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × (𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 ) = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × 𝑇𝑇𝑆𝑆 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡)
=
𝑇𝑇𝑆𝑆
𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂
=
1
1 − 𝐷𝐷
Inductor volt-second balance:
Boost transfer function:
VIN<VOUT
Most efficient at lower D
Continuous input current
High PF, low THD
CCM, BCM, DCM modes
VOUT
VAC
VIN(t)
D
IL
L
VL
Q
COUTCBYP
VOUT
VAC
VIN(t)
D
IL
L
VL
Q
COUTCBYP
〈𝑉𝑉𝐿𝐿〉 𝑇𝑇 𝑆𝑆
= 𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) × 𝑡𝑡𝑂𝑂𝑁𝑁 + ��𝑉𝑉𝐼𝐼𝐼𝐼(𝑡𝑡) − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 � × 𝑡𝑡𝑂𝑂𝐹𝐹𝐹𝐹 � = 0
10. 10
Continuous Conduction Mode (CCM) PFC
IL
Advantages
• Low Ripple current: Lower core losses
• Lower EMI : Smaller Input Filter
• Simple inductor design
• Fixed frequency operation, best PF and THD
• Can be used at any power level
• Easily interleaved for power levels up to
many KW
Disadvantages
Requires very fast boost diode with low IRR
Silicon Carbide diodes are often used
Larger Inductor
MOSFET Switching Loss (hard switching)
(1-D)TsDTs
Ts
IL
IDIsw
(Not to scale)
11. 11
Boundary Conduction Mode (BCM) PFC
IL
DTs
Ts
IDIsw
Advantages
• MOSFET turns on at zero current
• ZVS/valley switching
• No reverse recovery in boost diode
(low cost, low VF diode can be used)
• Higher efficiency compared to CCM
Disadvantages
• Larger MOSFET conduction loss
• Variable Frequency
• Inductor design can be complex
• High peak current limits practical use to
~300W (Impact on EMI filter)
(Not to scale)
12. 12
Buck Converter
VGS(Q)
VD
VDS(Q)
IL
IDS(Q)
ID
VIN
VF
VL
-VOUT
VIN-VOUT
VIN+VF
BCM
tON tOFF
TS
Inductor volt-second balance: Buck transfer function:
VIN>VOUT
Most efficient at higher D
VOUT
D
VOUT
D
IL
Q
L
VL
L
VL
Q COUT
COUT
VIN
CIN
VIN
CIN
〈𝑉𝑉𝐿𝐿〉 𝑇𝑇 𝑆𝑆
= [( 𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 ) × 𝑡𝑡𝑂𝑂𝑂𝑂 ] − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 = 0
𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × (𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 )
𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑇𝑇𝑆𝑆
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝐼𝐼𝐼𝐼
=
𝑡𝑡𝑂𝑂𝑂𝑂
𝑇𝑇𝑆𝑆
= 𝐷𝐷
13. 13
Buck-Boost Converter
Inductor volt-second balance: Buck-Boost transfer function:
VIN<VOUT or VIN>VOUT
Used for negative VOUT
〈𝑉𝑉𝐿𝐿〉 𝑇𝑇 𝑆𝑆
= 𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 + 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 = 0
𝑉𝑉𝐼𝐼𝐼𝐼 × 𝑡𝑡𝑂𝑂𝑂𝑂 = −(𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 )
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝐼𝐼𝐼𝐼
= − �
𝑡𝑡𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆
𝑡𝑡𝑂𝑂𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆
� = − �
𝑡𝑡𝑂𝑂𝑂𝑂 /𝑇𝑇𝑆𝑆
(𝑇𝑇𝑆𝑆 − 𝑡𝑡𝑂𝑂𝑂𝑂 )/𝑇𝑇𝑆𝑆
�
𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂
𝑉𝑉𝐼𝐼𝐼𝐼
= − �
𝐷𝐷
1 − 𝐷𝐷
�
VGS(Q)
VD
VDS(Q)
IL
IDS(Q)
ID
VF
VL
VIN
VIN+|-VOUT|
tON tOFF
TS
VIN+|-VOUT|
VOUT-VF
-VOUT
IL
L VL
Q COUT
D
-VOUT
VIN
IL
L VL
Q COUT
CIN
D
VIN
CIN
15. 15
Benefits of a Transformer
AC
AC DC
Output Load
(or DC)
D1
L
CO
Q1
CIN
VOVIN
D1
D2
L
CO
NP NS
CIN
Q1
VIN
VO
1. Provides primary to secondary safety isolation – subject to regulatory standards
2. Voltage conversion resolution
D
V
V
IN
O
= D
N
N
V
V
P
S
IN
O
=
Ex: For FSW=300kHz (TSW=3.33µs), NP:NS=4:1, 36V<VIN<75 and VO=5V
Buck Converter Isolated Buck (Forward) Converter
27%<D<55%
900ns<tON<1.8µs
6%<D<14%
200ns<tON<467ns
3. Multiple outputs can be regulated/quasi-regulated
16. 16
Transformer Characteristics
NP NS
VIN
VOUT
RP
RS
LP(LEAK) LS(LEAK)
CP(W)
CS(W)
NP NS
LMAGRCORE
CP-S(MUTUAL)
NP NS
VIN
VOUT
VGS
VDS
Parasitic Transformer Model
CCM Flyback
Overshoot/ringing due to
Leakage Inductance
Ideal transformer
• Perfect coupling between Np:Ns
• No energy storage
Flyback “transformer”
• Really a coupled inductor
• Primary energy stored during tON
• Power transferred during tOFF
17. 17
Single Ended Topologies Defined
∝B Vt
∝H NI
∆B
B1
B2
+BSAT
-BSAT
D1
D2
L
CO
NP NS
CIN
Q1
Reset
Circuit
TS
+VIN(max)
+VIN(min)
D=25%
D=50%
D>50%
-VRESET
-VRESET
OFFRESETONIN tVtV ×−=×+ (max)
RESETIN VV −=+ (max)
OFFON tt =
tON
tOFF
OFFON tt >
INQDS VV ×= 2)1(
INQDS VV ×> 2)1(
+VIN
-VRESET
-VIN
t
t
t
0
0
0
OFFRESETONIN tVtV ×−=×+
RESETIN VV −<+
(b) Forward Converter
Single Ended – Transformer operation limited to first quadrant
(c) Transformer Volt-Second Balance
(a) Transformer Hysteresis
18. 18
Single Ended Topologies Defined
∝B Vt
∝H NI
∆B
B1
B2
+BSAT
-BSAT
D1
D2
L
CO
NP NS
CIN
Q1
Reset
Circuit
(b) Forward Converter
Single Ended – Transformer operation limited to first quadrant
(a) Transformer Hysteresis (c) Gapped Flyback “Transformer”
D
CO
NP NS
CIN
Q1
VIN
VO
(d) Flyback Converter
∝B Vt
∝H NI
∆B
B1
B2
+BSAT
-BSAT
UNGAPPED
GAPPED
19. 19
Single Ended Transformer Reset Techniques
Reset Winding
+ Reset Energy Recycled
+ Simple Off-Line Solution
- 50% Duty Cycle Limit (1:1)
- Possible Core Saturation
- Transformer Structure
- Q1 Hard Switched
Resonant Reset
+ Reset Energy Recycled
+ Fewest Components
+ Simple Telecom Solution
- Repeatable Design Difficult
- High VDS Stress
- Not for Off-Line Power
- Not Suitable for Self-Driven SR
- Q1 Hard Switched
RCD Reset
+ Inexpensive Off-Line Solution
+ >50% Duty cycle Possible
- Reset Energy Dissipated
- Q1 Hard Switched
Active Clamp Reset
+ High Efficiency (ZVT)
+ Higher Frequency Operation
+ Lowest Vds Stress
+ Off-Line and Telecom
+ SR Gate Drive
- Q1, Q2 Gate Drive
- Higher Cost
- Limited PWM and/or Driver
Choices
NP NS
Q1
Reset
Winding
0
VIN
-VR
NP NS
Q1
RCD Reset
0
VIN
-VR
NP NS
Q1
Resonant
Reset
0
VIN
-VR
Q2
CCL
NP NS
Q1
Active Clamp
Reset
0
VIN
-VR
20. 20
Flyback Converter Derivation
-VOUT
L
Q COUT
D
VIN
CIN
-VOUT
L
Q COUT
D
VIN
CIN
1:1
-VOUT
LM
Q COUT
D
VIN
CIN
1:1
(a)
(b)
(c)
(d)
(e)
a) Non-isolated buck-boost
b) Coupled inductor buck-boost
c) Isolated buck-boost
d) Isolated flyback converter
e) D can be in return path
VOUT
LM
Q
COUT
D
VIN
CIN
n:1
VOUT
LM
Q
COUT
D
VIN
CIN
n:1
21. 21
Flyback Converter Operating Modes
Discontinuous Conduction Mode (DCM)
• Advantages (DCM): Smaller transformer, trr of output rectifiers is less of an issue since
current is zero before reverse voltage appears, single pole characteristic of the power circuit
simplifies compensation
• Disadvantages (DCM): Peak currents in the switch and diodes are considerably greater,
ripple currents in output capacitors are much greater than continuous mode
Continuous Conduction Mode (CCM)
• Advantages (CCM) = Peak currents in the switching devices are lower, ripple currents in the
output capacitors are lower
• Disadvantages (CCM) = Larger transformer is required, right half plane zero (RHPZ) shows
up in the control loop thereby complicating compensation
Boundary Conduction Mode (BCM)
• Variable frequency
22. 22
Flyback Converter
CCM Operation
D
D
N
N
V
V
P
S
IN
O
−
×=
1
(a) Flyback Converter
(b) CCM Waveforms
CCM Transfer Function
Limitations
• Q1 switching loss (hard switched)
• D2 reverse recovery loss
• Q1(VDS)>VIN
• 50% duty cycle limit
• Right half plane zero in CCM
VOUT
LM
Q
COUT
D
VIN
CIN
n:1 NSNP
0
0
0
0
0
0
PWM
VDS
VS
IQ1
ID1
IL
VOUT
-(NS/NP)VIN
VIN+(NP/NS)VOUT
23. 23
Quasi-Resonant Flyback
Conventional Valley Switching
Wide frequency variation depends on output load condition
t
t
iD
vDS
T2
Output Power [W]
fS[Hz]
vDS
iD
t
t
T1
Output load decreases
Operating frequency
increases
SOSSLossSwitching fVCP DS
2
∝
24. 24
Quasi-Resonant Flyback
Window Valley Switching Ts
max
=10.8us
tB=7.8us
tW=3.0us
fs_A=110kHz
fs_B=122kHz
fs_C=127.5kHz
fs_D=92.6kHz
(a)
(b)
(c)
(d)
vDS (100V/div)
iD (100mA/div) Time scale 2usec/div
Frequency variation depends on
output load conditions
Operating frequency is within narrow
variation (127.5 kHz ~ 92.6 kHz)
Light Load
Heavy Load
25. 25
Two-Switch, Quasi-Resonant Flyback
CC
CVFB
FAN6300H
1
2
3
4 5
6
7
8
NC
HV
VDD
GATEGND
CS
FB
DET
FAN7382
1
2
3
4 5
6
7
8
HO
VB
VS
LOCOM
LIN
HIN
VCCPBIAS
VIN
R1
R2
R3
Q1
Q2
D1
D2
D3
D4D5
ACIN
R4
C1
VA
VLED
VHS
C2
C3
(FROM PFC)
(FROM PFC)
RDY
PBIAS
26. 26
Two-Switch, Quasi-Resonant Flyback
Switching Waveforms
0V
VDS
0A
IDS
tftOFF tON
TS
0A
ID
VAVA
0V
0V
VDET
0V
VIN
PBIAS
VIN+VHS
VGS(HS)
VGS(LS)
0.7V
5µs
2.5V
VO
OVP
IDET(SOURCE)>30µA
tDELAY=200ns
VRO
2
VRO
2
VIN
2
VIN
2
Quasi-resonant, variable frequency
HS and LS MOSFETs switch synchronously
Switching period, TS=tOFF+tf+tON
Inductor current switches from 0A (ZCS) every
switching cycle
VDS
• ZVS→VOUT>2×VIN
• Valley switching→otherwise
• Window valley switching
27. 27
Two-Switch, Quasi-Resonant Flyback
Measured Waveforms
Extended Window Valley Switching
VOUT< ½ VIN
D=11%
FS=68kHz
POUT=24W
VDS Valley Switching on First Valley
• VOUT< ½ VIN
• D=42%
• FS=63kHz
• POUT=85W
28. 28
Buck Derived Transfer Functions
D1
L
CO
VOVIN
D1
L
CO
VOVIN
NP : NS
tON
tOFF
TS
D
N
N
V
V
P
S
IN
O
×=
(a) Buck Converter (b) Forward Converter (isolated buck)
S
ON
OFFON
ON
T
t
tt
t
D =
+
=Duty Cycle =
INO VDV ×=
( ) OFFOONOIN tVtVV ×=×−
D
V
V
IN
O
=
Buck Converter Transfer Function
Forward Converter Transfer Function
D
N
N
V
V
P
S
IN
O
×=
All Isolated Single Ended Buck Converters
All Isolated Double Ended Buck Converters
D
N
N
V
V
P
S
IN
O
××= 2
29. 29
Forward Converter Basics
0
0
0
PWM
VDS(Q1)
VP
VR+VIN
VIN
IMAG
0 IQ1
IL
ID1
ID2
0
0
0
0
VIN
R
P
INR
N
N
VV ×−=
D1
D2
L
CO
NP NSCIN
Q1
VIN
VO
NR
D3
(a) Forward Converter with Reset Winding
(b) DCM Waveforms (D<0.5)
Really a transformer coupled buck
Transfer function
Limitations
• Q1 switching loss (hard switched)
• D2 conduction loss
• Q1(VDS)>2VIN
• 50% duty cycle limit (NP:NR = 1:1)
D
N
N
V
V
P
S
IN
O
×=
30. 30
VIN
0
VP
IMAG
TS
DTS D2TS D3TS
t
t
R
P
IN
N
N
V ×−
Why 50% Duty Cycle Limit?
(a) Forward Converter: Transformer Voltage and Current
1. Average primary voltage must be zero over switching period
2. Solve (1) for D2
0)0()( 32 =+
−+=〉〈 D
N
N
VDVDV
R
P
ININp
132 =++ DDD
3. By definition
(1)
(2)
(3)
4. Solve (3) for D3
01 23 ≥−−= DDD (4)
P
R
N
N
DD =2
5. Sub (2) into (4)
01 ≥−−
P
R
N
N
DD (5)
6. Solve (5) for D
(6)
P
R
N
N
D
+
≤
1
1
7. For NP:NR=1:1 (common practice)
(7)
2
1
≤D
31. 31
Problems with Duty Cycle > 50%
VIN
0
VP
IMAG
TS
DTS D2TS D3TS
t
t
R
P
IN
N
N
V ×−
Equal Vxt Area
VIN
VP
IMAG
t
t
R
P
IN
N
N
V ×−
2TS 3TSTS
DTS D2TS
D=67%
D=40%
Unequal Vxt Area
Common practice is to use 1:1 bifilar
transformer winding for NP:NR
D=40%
• Converter operates in DCM
• Transformer is completely reset on every
switching cycle
D=67%
• Converter wants to operate in CCM
• Transformer can NOT reset on every
switching cycle
• IMAG increases due to volt second product
imbalance
• Transformer saturation will result
• Operation beyond D=50% requires
additional reset voltage
32. 32
Duty Cycle Greater Than 50%
VDS vs Vin
Third Winding Reset
72
84
96
108
120
132
144
156
168
180
192
204
216
36 42 48 54 60 66 72
Vin (V)
VDS(V)
Np:NR=1:1 Np:NR=1:2
NP NS
Q1
NR
VDS
VIN
VP
IMAG
t
t
R
P
IN
N
N
V ×−
2TS 3TSTS
DTS D2TS
D=67%
Equal Vxt Area
}
}
NP:NR=1:1
NP:NR=1:2
For NP:NR=1:2
VDS=3VIN
Conclusion: Reset winding technique, D>50% not practical for high VIN applications
due to additional MOSFET VDS stress
33. 33
Active Clamp Forward Converter
D1
D2
L
CO
NP NS
CIN
Q1
Q2
CCL
0
0
0
0
PWM
Q1 VDS
VP
IQ1
VIN
VRESET
VIN+VCL
0
Q2 VGS
IMAG
ICL
0
IP
Advantages
• Reduced MOSFET VDS voltage stress
• Higher efficiency through ZVS
• Use of parasitic elements
• Higher frequency operation
• Square wave transformer reset for SR applications
• Suitable for off-line (HS clamp) or DC/DC (LS clamp)
Disadvantages
• Conditional ZVS only
• Dual primary side gate drive with accurate dead-time control
and max duty cycle clamp required
• Poor transient response due to CCL
Transfer Function
D
N
N
V
V
P
S
IN
O
×=
34. 34
Active Clamp Forward Converter
Two Versions
D1
D2
L
CO
NP NS
CIN
Q1
Q2
CCL
D1
D2
L
CO
NP NS
CIN
Q1
Q2
CCL
(a) High-Side Active Clamp
(Flyback Clamp)
(b) Low-Side Active Clamp
(Boost Clamp)
INV
D
×
−1
1
INV
D
×
−1
1
INV
D
D
×
−1
INV
D
D
×
−1
INV
D
D
×
−1
INV
D
×
−1
1
PARAMETER HIGH-SIDE ACTIVE CLAMP (off-line) LOW-SIDE ACTIVE CLAMP (telecom)
VDS
VRESET
VCL
CCL
(applied voltage)
Lower voltage by VIN volts
Highest VCL occurs at DMAX
Higher voltage by VIN volts
Not practical for off-line
CCL
(cap value)
Same value as low-side for given ripple voltage Same value as high-side for given ripple voltage
Clamp MOSFET
(Q2)
N-Channel
Can be used for >500V
P-Channel
Can be used up to 500V
Gate Drive Gate drive transformer required Level shifting gate drive required
35. 35
Active Clamp Forward Converter
VDS Voltage Stress
VDS vs Vin
Active Clamp Reset
75
85
95
105
115
125
135
145
36 42 48 54 60 66 72
Vin (V)
VDS(V)
N=5 N=6 N=7
SECIN
IN
INDS
VNV
V
D
VV
×−
=
−
×=
2
1
1
Telecom Converter Example
VVV IN 7236 ≤≤
S
P
N
N
N =, where
VVO 3.3=
Optimize transformer turns ratio, N, to
minimize VDS voltage stress over entire
VIN range
For N=6
• VDS=108V at VIN(MIN) and VIN(MAX)
• VDS≤1.5VIN at VIN(MAX)
N=5
N=6
N=7
DMIN=28%DMAX=55%
IN
O
V
NV
D
×
=
IMPORTANT – Accurate max duty cycle clamp or volt-second clamp is necessary due to the
parabolic nature of VDS near DMAX
36. 36
Active Clamp Forward Converter
Clamp Capacitor
D1
D2
L
CO
NP NS
CIN
Q1
Q2
CCL
0
0
PWM
Q1 VDS
VIN+VCL
0
Q2 VGS
VCL(Ripple) = 0%
VCL(Ripple) = 50%
Clamp capacitor optimal
• VCL(RIPPLE) = 10%-20%
VCL(Ripple) = 10%
Q1 VDS Waveforms verses Clamp Capacitor Value:
Clamp capacitor too small
• VCL(RIPPLE) = 50%
• Better transient response
• Increase VDS stress
Clamp capacitor too large
• VCL(RIPPLE) = 0%
• Lowest VDS stress
• Poor transient response
Choosing Clamp Capacitor
• Capacitor needs to be large enough to approximate the clamp voltage as DC
• Initially calculate CCL according to “Rule of Thumb”
• Select CCL voltage rating according to maximum clamp voltage PLUS allowable
ripple voltage and safety margin
)(2 MAXoffCLMAG tCL >××π
( )
2
2
)2(
1
10
swMAG
MIN
CL
FL
D
C
××
−
×>
π
37. 37
Active Clamp Forward Converter
Zero Voltage Switching (ZVS)
ZVS occurs when the voltage across the MOSFET, VDS, is positioned to “zero volts” prior to
the start of the next switching cycle.
Benefits of ZVS
• Reduced switching losses
• Higher operating frequency possible (smaller passive component size)
• Higher converter efficiency
• Increased reliability
• Reduced radiated emissions (EMI)
VDS
ID
PSW=VDS x ID x FSW
(a) Hard Switching (b) “Ideal” ZVS
38. 38
Active Clamp Forward Converter
Zero Voltage Switching (ZVS)
D1
D2
L
CO
Q1
Q2
CCL
D2
CDS
D1
CDS
VDS
RP
RS
LP(LEAK) LS(LEAK)
CP(W)
CS(W)
NP NS
LMAGRCORE
CP-S(MUTUAL)
CD1
CD2
Parasitic elements can be used to benefit ZVS
Active Clamp Forward converter uses fixed frequency resonant transitions to achieve
ZVS when specific operating conditions are met
39. 39
Active Clamp Forward Converter
Zero Voltage Switching, Q1 Turn-Off
IM
+ IO
N
IC
VIN
VDS
0
VIN
VDS
IM
IO
N
VGS(Q1)
VGS(Q2)
ZVS turn-off is easy
• Magnetizing current, IM
+, and reflected secondary current
combine to fully charge the resonant capacitance, C
( )2
2
2
1
2
1
CLINDSM
O
M VVCI
N
I
L +>
+ +
NOTE: leakage inductance is neglected for this analysis
D1
D2
L
CO
NP NS
CIN
Q1
Q2
CCL
40. 40
Active Clamp Forward Converter
Zero Voltage Switching, Q1 Turn-On
IM
- IO
N
IC
VIN
VDS
, for ZVS turn-on
−
MI
0
VIN
VDS
IM
IO
N
VGS(Q1)
VGS(Q2)
N
I
I O
M >−
VDS
VGS(Q1)
1 - Non-ZVS
2 - Optimal ZVS
3 - ZVS
(2, 3) - ZVS
1 - Non-ZVS
(Miller)
ZVS turn-on is difficult
• Magnitude of IM
- must be greater than the magnitude of
the reflected secondary current during entire ZVS
window
• Must be enough resonant current to fully discharge C
• Must be enough dead time for the drain voltage to fully
resonate to near zero volts
N
I
I O
M >−
( )2
2
2
1
2
1
CLINDSM
O
M VVCI
N
I
L +>
− −
DSMRES CLt ×≥
2
π
NOTE: leakage inductance is neglected for this analysis
41. 41
Single Ended (<500W)
2 Switch Forward Converter
D1
D2
L
CO
NP NSCIN
Q1
Q2
D3D4
0
0
0
PWM
(Q1, Q2)
VDS
(Q1, Q2)
VS
VIN/NP
VIN
VIN/2
ID3, ID4
-VIN/NP
0 IQ1, IQ2
0
IL
ID1
ID2
0
0
IO
IMAG0
Advantages
Ruggedness
MOSFET voltage stress limited to VIN
Magnetizing energy recycled by D3, D4
Universal input, 150W<P<500W
Disadvantages
Limited to less than 50% duty cycle
High side gate drive required for Q2
Hard switching
Transfer Function
D
N
N
V
V
P
S
IN
O
×=
42. 42
Single Ended (>1kW)
Interleaved 2 Switch Forward Converter
D1
D2
L
CO
NP NSCIN
Q1
Q2
D3D4
D5
D6
L
NP NS
Q3
Q4
D7D8
Dn
Dn
L
NP NS
Qn
Qn
DnDn
Advantages
• Can operate multiple power stages out of
phase
• Ripple current cancellation at output
capacitor
• Reduced RMS current at input capacitor
• Multiple stages can add up to kW of power
• Smaller output inductors can improve
transient response
Disadvantages
• Design complexity
• PCB layout can be challenging
44. 44
Double Ended Topologies Defined
∝B Vt
+BSAT
∝H NI
-BSAT
∆B
B1
B2
∝B Vt
∝H NI
∆B
B1
B2
+BSAT
-BSAT
∆B
B1
B2
(RCD Reset)
(Active Clamp)
Normal
Flux Imbalance
Saturation
Primary Current
Double Ended – Transformer operation occurs in first and third quadrants
Active Clamp Forward
“Single ended” but operates slightly into the
third quadrant
Half-Bridge, Full-Bridge
Symmetrical operation between first and third
quadrants
No transformer reset circuitry required
45. 45
Double Ended (<500W)
Push Pull Converter
D1
D2
L
CO
NP
NS
Q1
NS
Q2
CIN
NP
PWM, Q1
PWM, Q2
IQ1
IQ2
VDS(Q1)
2VIN
VDS(Q2)
2VIN
ID1
ID2
ILIO
Advantages
• Lower primary current compared to HB
• Best for lower VIN, such as telecom
DC/DC of US Line Voltage
• Simple low-side gate drive
Disadvantages
• High voltage (2xVIN) on primary MOSFETs
• Transformer flux walking (VMC only)
• Center tapped transformer structure
• Hard switching
Transfer Function
D
N
N
V
V
P
S
IN
O
××= 2
46. 46
Double Ended (<500W)
Half Bridge Converter (Symmetrical)
D1
D2
L
CO
NP
NS
Q1
NS
Q2
CIN
C1
C2
VP
VDS(Q1, Q3)
VIN
VDS(Q2, Q4)
VIN
ID1
ID2
IL
IO
VP
IP
VIN/2
PWM, Q1
PWM, Q2
-VIN/2
Advantages
• Better transformer utilization
• MOSFET voltage stress limited to VIN
• Best for high VIN off line applications up to 500W
• Single winding primary
• Transformer balanced by C1 and C2
• Asymmetric and resonant versions can ZVS
Disadvantages
• Totem pole primary gate drive
• High primary current
• Possible cross conduction between Q1 and Q2
• Hard switching
Transfer Function
D
N
N
V
V
P
S
IN
O
××= 2
47. 47
Asymmetrical Half Bridge Converter
+
Vp
-
+
Vd
-
+
Vp
-
1 : 1
0
Asymmetric square waveform
Symmetric square waveform
Vd
Vd
0
CB
+
Vp
-
+
Vd
-
+ VCB -
Same area
VCB
+
Vp
-
1 : 1
0
0
What if an asymmetric square wave were introduced to the transformer?
Transformer will be saturated
What if an asymmetric square wave were introduced to the transformer in series with a DC
blocking capacitor?
Not saturated due to the voltage of the blocking capacitor, CB
48. 48
Asymmetrical Half Bridge Converter
VP
IP
Q2 (D)
Q1 (D)
VIN/2
-VIN/2
D=0.46 D=0.23
VIN/2
-VIN/2
VP
IP
Q2 (D)
Q1 (1-D)
VIN-VCB
VCB VCB
D=0.46 D=0.23
Equal
Area
VIN-VCB
(a) Symmetrical HB waveforms
(b) Asymmetrical HB waveforms
Asymmetrical Gate Drive
• Q2 modulated by D
• Q1 driven by 1-D
• Fixed dead time between Q1 and Q2
• Dead time optimized for ZVS and anti cross conduction
• Fixed frequency ZVS PWM operation
• Near D=0.5, operation is same as symmetrical HB
BUT, excessive voltage stress is applied to secondary
rectifier at VIN(MAX)
( )DD
N
N
V
V
P
S
IN
O
−×××= 12
D1
D2
L
CO
NP
NS
Q1
NS
Q2
CIN
CB
VP
49. 49
Asymmetrical Half Bridge
VD vs D
50
75
100
125
150
175
200
225
250
0.20 0.23 0.26 0.29 0.32 0.35 0.38 0.41 0.44 0.47 0.50
Duty Cycle
DiodeVoltageStress(V)
VD1 VD2
Asymmetrical Half Bridge Converter
Secondary Rectifier Voltage Stress
Reverse recovery and parasitic ringing
Wide DD Range requires use of high
voltage rectifiers
Converter operates best at D=0.5
D
V
V O
D
−
=
1
1 OD VDV ×=2
50. 50
Asymmetrical Half Bridge Converter
Advantages
• Fixed frequency ZVS
• Constant power transfer (D and 1-D) reduces output ripple
• Power stage can be controlled using any active clamp PWM controller
Disadvantages
• High voltage stress on secondary rectifier
• Loss of ZVS at some min load current – extending ZVS range is difficult
• Poor transient response due to blocking capacitor, CB
51. 51
LLC Resonant Half Bridge Converter
Square wave generator: produces a square wave voltage, Vd by driving switches, Q1 and
Q2 with alternating 50% duty cycle for each switch.
Resonant network: consists of Llkp, Llks, Lm and Cr. The current lags the voltage applied to
the resonant network which allows the MOSFET’s to be turned on with zero voltage.
Rectifier network: produces DC voltage by rectifying AC current
Ip
Ids2
Vd
(Vds2)
Vgs2
Im
Vin
ID
Vgs1
+
VO
-
Ro
Q1
Q2
n:1
Ip
Llkp
Lm
Cr
Ids2
Vd
Llks
Im
ID
Vin
Square wave generator
resonant network Rectifier network
Io
52. 52
LLC Topology Variations
VIN
Lr
Lm
Cr
Q1
Q2
VIN
Lr
Lm
Cr
Q1
Q2
VIN
Lr
Lm
½ Cr
Q1
Q2
½ Cr
VIN
Lr
Lm
½ Cr
Q1
Q2
½ Cr
+
VO
-
Ro
+
VO
-
Ro
+
VO
-
Ro
+
VO
-
Ro
Primary Side Variation Secondary Side Variation
Transformer across the
high side MOSFET
Transformer across the low
side MOSFET
Split resonant capacitor with
clamping diode
Split resonant capacitor
Full bridge rectifier with
single winding
2 Rectifier diode with center
tab winding
Voltage doubler rectifier
with single winding
Synchronous rectifier with
center tab winding
53. 53
LLC Resonant Half Bridge Converter
Advantages of the LLC resonant converter
• Narrow frequency variation range over wide load range
• Zero voltage switching even at no load condition
• Reduced switching loss through ZVS Improved efficiency and EMI
• When the two magnetic components are implemented with a single core (use the leakage inductance
as the resonant inductor), one component can be saved
54. 54
LLC Resonant Half Bridge Converter
Disadvantages of the LLC resonant converter
• Can optimize performance at one operating point, but not with wide range of input voltage and load
variations (too wide frequency range)
• Difficult to regulate the output at no load condition
• Significant current may circulate through the resonant network, even at the no load condition
• Quasi-sinusoidal waveforms exhibit higher peak values than equivalent rectangular waveforms
• High output current ripple
55. 55
Double Ended (<500W)
Push Pull Converter
D1
D2
L
CO
NP
NS
Q1
NS
Q2
CIN
NP
PWM, Q1
PWM, Q2
IQ1
IQ2
VDS(Q1)
2VIN
VDS(Q2)
2VIN
ID1
ID2
ILIO
Advantages
• Lower primary current compared to HB
• Best for lower VIN, such as telecom DC/DC of
US Line Voltage
• Simple low-side gate drive
Disadvantages
• High voltage (2xVIN) on primary MOSFETs
• Transformer flux walking (VMC only)
• Center tapped transformer structure
• Hard switching
Transfer Function
D
N
N
V
V
P
S
IN
O
××= 2
56. 56
Double Ended (>500W)
Full Bridge Converter (PWM)
D1
D2
L
CO
NP
NS
Q3
NS
Q4
CIN
Q1
Q2
Gate, Q1
Gate, Q2
VDS(Q1, Q4)
VIN
VDS(Q2, Q3)
VIN
ID1
ID2
IL
IO
Gate, Q3
Gate, Q4
VP
IP
VIN
-VIN
Advantages
• MOSFET voltage stress limited to VIN
• Twice the power compared to half bridge
• Single winding primary
Disadvantages
• Dual, totem pole primary gate drive
• Hard switching (Non-ZVT)
• Parasitics degrade circuit performance
• Circuit complexity
Transfer Function
D
N
N
V
V
P
S
IN
O
××= 2
57. 57
Double Ended (>500W)
Phase Shifted Full Bridge Converter
D1
D2
L
CO
NP
NS
Q3
NS
Q4
CIN
Q1
Q2
Gate, Q1
Gate, Q2
VDS(Q2, Q3)
VDS(Q1, Q4)
ID1
ID2
IL
IO
Gate, Q3
Gate, Q4
VP
IP
VIN
-VIN
VIN
Freewheel
Power
Freewheel
Power
VIN
Advantages
• High Efficiency ZVS
• Highest single stage processing power
• MOSFET voltage stress limited to VIN
• Twice the power compared to half bridge
• Full wave rectified secondary
• Excellent choice for EU line voltage (PFC pre-
regulator) with output power >1kW
Disadvantages
• Dual, high side primary gate drive
• Circuit complexity
• High circulating primary current for ZVS
• Loss of ZVS at light load current
Transfer Function D
N
N
V
V
P
S
IN
O
××= 2
59. 59
Phase Shift Control vs ZVT PWM Control
A
B
C
D
VPRI
IPRI
UL(A)
LL(B)
UR(C)
LR(D)
VPRI
IPRI
UR(C)
LR(D)
UL(A)
LL(B)
ZVT PWM Control
• Upper bridge FETs are fixed at 50% D
• Lower bridge FETs are trailing edge PWM
• Resonant delay set on lower FET leading edge
Freewheel period
• Both SRs are ON
• Reduces reflected secondary current since current
only flows through both SRs
• Less available ZVS current
Phase Shift Control
• All bridge FETs are fixed at 50% D
• A and B are synced to clock
• C and D are phase shift modulated
• Resonant delay set between AB and CD
Freewheel period
• Secondary-side load current freewheels through
transformer and is reflected to primary
• Reflected current aids ZVS
• Higher conduction losses at higher power
60. 60
Phase Shift Control vs ZVT PWM Control
ZVT PWM Control
• Current freewheels through one high-side active
FET and body-diode of other high-side FET during
each FW period
Phase Shift Control
• Current freewheels through two active high-side
FETs for first FW period then through two active
low-side FETs for second FW period
Freewheel
ResonantFreewheel
Resonant
( )ONDSFWDISS RIP _
2
2 ××= ( )ONDSFWFWFSWBDDISS RIIVFtP _
2
×+×××=
61. 61
ZVT PWM Control
Upper Bridge MOSFET Body-Diode Conduction
Freewheel (FW) Period
• For 36V<VIN<72V
• Body-diode conduction is 970ns at VIN=72V
Minimize body-diode conduction in upper MOSFETs
• Pre-regulate input voltage (PFC)
Still have to deal with brown-out and hold-up
• Operate converter at lowest frequency possible
VVF 1=
AI FW 2=
nstBD 970=
kHzFSW 265=
Ω= mR ONDS 25_
mWVAkHznsPBD 51412265970 =×××=
mWmAP ONRDS 100252 2
)( =Ω×=
Measured Values
Calculated Body-Diode Conduction Loss in each Upper FET
Calculated Channel Conduction Loss in each Upper FET
Total Conduction Loss for each FW period (ZVT PWM Control)
Total Conduction Loss for each FW period (PSFB Control)
Comparison of FW MOSFET Conduction Losses for
Telecom DC/DC App
VVIN 72=
AIOUT 10=
*Assume switching, gate charge, Coss losses
are same for each control method
mWmWmWP ZVTPWMFW 614100514)(1 =+=
mWmWmWP ZVTPWMFW 614100514)(2 =+=
mWmWP PSFBFW 2001002)(1 =×=
mWmWP PSFBFW 2001002)(2 =×=
(25%)
(UL and UR)
(UL and UR)
(A and B)
(C and D)
62. 62
High Power Topology Summary
D1
1
VIN
−
×
Topology Transformer Primary
Switches
VDS “Ideal” Application
CCM Boost Inductor
(non-isolated)
1 VOUT High power PFC >300W
Interleaved PFC >Several kW
BCM Boost Inductor
(non-isolated)
1 VOUT PFC <300W
Interleaved PFC <1kW
Forward Single-end 1 2xVIN <200W, universal off-line or telecom
Active Clamp Single-end 2 <500W, universal off-line or telecom, highest
efficiency required
2-Switch Forward Single-end 2 VIN <500W, universal off-line, PFC pre-regulator
Half Bridge Double-end 2 VIN <500W, EU off-line, Intermediate Bus Converters
Push Pull Double-end 2 2xVIN <500W, telecom or low VIN (<200V)
Full Bridge Double-end 4 VIN >500W, universal off-line
Phase Shifted FB Double-end 4 VIN >1kW, universal off-line or telecom, highest
efficiency required
Current Doubler Double-end NA NA Any double-ended topology, low VOUT, high IOUT
most benefit
63. 63
LLC vs AHB Comparison
LLC resonant converter Asymmetric Half-bridge
Control method Variable frequency with fixed duty cycle (50%) PWM with fixed frequency
Practically input
voltage range
Vmax
/Vmin
=1.2~1.4 Vmax
/Vmin
=1.2~1.3
Primary side MOSFET
voltage
Clamped to the input voltage Clamped to the input voltage
Secondary side rectifier
voltage stress
2 times the output voltage (for center tapped
transformer)
Usually about 3 to 6 times the output voltage for powering and
freewheeling diodes, respectively (for center tapped transformer)
Output capacitor current
ripple
Almost twice the output current (peak-to-peak) Several tens % of output current (peak-to-peak)
ZVS condition ZVS is easily achieved from full load to no load
condition using the energy in the magnetizing inductance
ZVS is difficult to achieve at light load condition
ZVS at full load condition is relatively easy
Other features No simple power limit capability such as pulse-by-
pulse current limit in PWM operation
Requires tight tolerance of resonant components (L,C)
Relatively large circulating current
Tight tolerance is not required for the resonant components (L,C)
+
VO
-
Ro
Q2
Q1
Vin
Io
Lr
Lm
CB
+
VO
-
Ro
Q1
Q2
Vin
Io
Lr
Lm
Cr
65. 65
Synchronous Rectification (SR)
D1
D2
L
CO
NP NS
CIN
Q1
Reset
Circuit
Efficiency vs Output Voltage
Vf=0.4V, Vf=1V
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.5 1.7 2.8 4.0 5.1 6.3 7.4 8.6 9.7 10.9 12.0
Output Voltage (V)
Efficiency
Vf=0.4V Vf=1V
Q2
Q3
L
CO
NP NS
CIN
Q1
Reset
Circuit
What is Synchronous Rectification?
• Replacing secondary side discrete rectifiers
(D1, D2) with MOSFETs (Q2, Q3)
Benefits of SR
• Parallel MOSFETs
• Increase efficiency
Lower output voltage and higher current
applications benefit most
How do we drive them?
OUT
FOUTFOUTOUT
OUTOUT
IN
OUT
V
VIVIV
IV
P
P
+
=
×+×
×
==
1
1
η
66. 66
Single Ended Synchronous Rectification
SR Gate Drive Options
Q3
Q4
L
CO
NP NS
CIN
Q1
Q2
CCL
Q3
Q4
L
CO
NP NS
CIN
Q1
Q2
CCL
SR Gate Drive
Self-Driven SR
SR gate drive derived from transformer (as
shown) or output inductor
Advantages
• Simple – no timing issues
• High efficiency for few components
Disadvantages
• SR gate drive not regulated
• Difficult when VIN > 2:1
• No control of secondary during start-up
• Not compatible with all reset techniques
Control-Driven SR
SR gate drive comes from PWM control signal
Advantages
• SR gate drive is regulated
• Can be used for wide VIN applications
• Secondary is controlled by primary
Disadvantages
• Primary to secondary timing
67. 67
Q3
Q4
L
CO
SR Gate Drive
Reset
Circuit
NP NS
CIN
Q1
D
1-D
Single Ended “Hybrid” SR
SR Gate Drive Options
Hybrid-Driven SR
• Combination of control driven and self driven
• Forward SR (Q3) self driven by D
• Free wheeling SR (Q4) driven by PWM inverted (1-D)
Applications
• Forward converter operating in DCM
• RCD, Resonant and Third Winding Reset
68. 68
NP
Q3
Q4
CIN
Q1
Q2
Q5
L1
CO
NS
L2
Q6
SR Gate Drive
T1
Double Ended Synchronous Rectification
(>1kW)
(a) Full Bridge with Current Doubler SR Secondary
SR applications typically greater than 12V output
Highest efficiency
• Minimize body-diode conduction
• Use Secondary sensing for best timing
SR driver solution is strongly related to control scheme
• Primary side PWM control
Need signal and timing from pri-to-sec for good SR control
Difficult to adapt over line/load changes
• Secondary side PWM control
Allows sensing key nodes for timing optimization
Cross boundary with timing to communicate with primary
Direct drive between PWM and SR
Needs startup bias supply
Double ended control driven SR drive is the more difficult SR problem to solve
69. 69
Double Ended (All)
Current Doubler Rectifier
D1
D2
L
CO
NP
NS
NS
VO
D1
D2
L CO
NP
NS
NS
VO
D1
D2
CO
VO
V
I
V
D1
D2
CO
VO
V
I
I
What is it? - A full wave alternative rectification technique compatible with all
double ended converter topologies
D1
D2
CO
VO
L2
L1
NP
NS
NP
NS
D1
D2
L1
CO
L2
VO
NP
Q1
L1
CO
NS
L2
Q2
VO
OR
Current Doubler
Derivation of Current Doubler
(a) (b) (c) (d)
(e)
(f) (g)
70. 70
Double Ended (All)
Current Doubler Rectifier Operation
t3 t4
Q3
Q4
CIN
Q1
Q2
D1
D2
L1
CO
L2
Q3
Q4
CIN
Q1
Q2
D1
D2
L1
CO
L2 t2 t3
Q3
Q4
CIN
Q1
Q2
D1
D2
L1
CO
L2 t1 t2
Gate, Q1
Gate, Q2
IO=IL1+IL2
Gate, Q3
Gate, Q4
VP
IP
IL1
IL2
VL2
VL1
t0 t1
t2 t3 t4
Q3
Q4
CIN
Q1
Q2
D1
D2
L1
CO
L2 t0 t1
Current Doubler Timing Diagram (PSFB Application)
Current doubler benefits:
• Better thermal distribution for
higher current outputs
• Each inductor carries half the load
current at half the switching
frequency
• Ripple currents cancel as a
function of D
• Single winding secondary
71. 71
Choosing the “best” topology:
• Is the output voltage higher or lower than the input voltage range?
• Are there isolation requirements?
• Are multiple outputs required?
• AC input – PFC/THD requirements?
• Output power?
• What is the maximum input/output voltage?
• What is the maximum input/output current?
Fine tune topology choice by trading off:
• Efficiency
• Performance
• Cost
• Size
Q&A?
Summary