APEC 2010 ACDC Live Demo Tech SessionPresentation_Feb 19 2010

www.fairchildsemi.com
Designing AC-DC Power Supplies for
High Efficiency

www.fairchildsemi.com2
300W High Efficiency AC-DC Converter
340W Interleaved BCM PFC
300W AHB DC-DC with Current Doubler Rectifier

Total Measured AC-DC System Efficiency
100%=300W
 >90% for POUT > 38% (114W)
 91% Peak for 120VAC, 92% Peak for 230VAC
70%
75%
80%
85%
90%
95%
100%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Efficiency(%)
Output Power (%)
120 Vac
230 Vac

300W AC-DC Board Dimensions
Power Density Calculation
231 mm
158 mm
18 mm
Board Profile:
18 mm
(0.7 in)
Board Area:
36,498 mm2
(56.55 in2)
Volume:
657 cm3
(39.6 in3)
Power Density:
0.456 W/cm3
(7.5 W/in3)

300W AC-DC Power Partitioning
EMI Filter and Bridge Rectifier 340W Interleaved BCM PFC
(FAN9612+SupreMOS™ FCP22N60N)
(FSFA2100+FAN3224T+PowerTrench™ FDP047N08+ PowerTrench™ FDP025N06)

Interleaved PFC Section
EMI Filter and Bridge Rectifier

Interleaved BCM/CRM PFC
 No reverse recovery
 Less expensive diode can be used
 Less switching loss, Less EMI
 Smaller inductor than single CCM PFC (Overall
inductor size is reduced)
 Phase management can improve light-load
efficiency
 Reduced ripple current in the output capacitor
IL1
IL2
IL1 + IL2
iL
(1-D)TsDTs
Ts
IL
ID
Isw
iL
DTs
Ts
ID
Isw
BCM
CCM
IL1
IL2
IL1 + IL2

FAN9611/12
Interleaved Dual BCM PFC Controller
 Efficiency
 Interleaved  Lower Turn-off Losses
 Phase Management
 Valley Switching  Minimize COSS losses
 Strong gate drive  reduce switching losses
 Adjust Bulk Output Voltage at Light Load
 Boost-follower (“tracking boost”) Possible
 Protection
 Closed-loop soft-start w/ Prog. Ramp Time
 Power and Current Limit per Channel
 Input Voltage Feed-forward
 Secondary Latched OVP
 Input Brown-out Protection
 Internal maximum fSW clamp limit
 Ease of Design & Solution Size
 Easy Valley Detection Implementation
 Easy Loop Compensation (constant BW and
PWM Gain)
 Integrated +2.0A/-1.0A Gate Drivers
 Works with DC, 50Hz to 400Hz AC Inputs
VOUT
385 VDC
D2
D1
FAN9612
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
CS2
CS1
VDD
DRV1
DRV2
PGND
VIN
OVPFB
COMP
SS
AGND
MOT
5VB
ZCD2
ZCD1
L2
AC IN
85-265 VAC
L1
M2
R1 R2
CBULK
M1
BIAS
Bold = Key Advantages
FAN9611: UVLO (10.0 V / 7.5 V)
FAN9612: UVLO (12.5 V / 7.5 V)

Asymmetrical Half-Bridge (AHB) Section

Asymmetrical Half-Bridge Converter
 Advantages
 Fixed frequency ZVS
 Constant power transfer (D and 1-D) reduces output ripple
 Power stage can be controlled using any active clamp PWM controller
 Easy implementation of self-driven synchronous rectification
 Disadvantages
 High voltage stress on secondary rectifier
 Loss of ZVS at some min load current – extending ZVS range is difficult
 Poor transient response due to DC blocking capacitors
 Increased magnetizing current at DMIN can push transformer toward saturation -
Transformer design is critical

FSFA2100
Features
 Internal 600V SuperFETTM
MOSFETs with fast recovery body
diodes (tRR=120ns) to
improve reliability and efficiency
when operating out of ZVS mode
 Protection functions: Over
Voltage Protection (OVP), Over
Load Protection (OLP),
Abnormal Over Current Protection
(AOCP), Internal Thermal
Shutdown (TSD)
 Up to 300kHz operating frequency
with fixed dead time (200ns)
 Applicable to AHB and active
clamp flybacks etc.
Rsense
Control
ICCDL
Vcc VDLLVcc
RT
VFB
CS
SG PG
VCTR
HVcc
Cr
Llk
Lm
Ns
Vo
D1
D2
RFCF
Np Ns
KA431
Vin
Rsense
Control
ICCDL
Vcc VDLLVcc
RT
VFB
CS
SG PG
VCTR
HVcc
Cr
Llk
Lm Vo
D1
RFCF
Np
Ns
KA431
Vin

 Dual channel Low side gate drivers
are good solution for self driven SR
 Gate drive signal is easily obtained
from the transformer voltage
 Enable pin can be used to disable
SR until the output is built up during
startup
Self driven SR using Low side drivers
DTS (1-D)TS
Dloss1TS
VGS S1 S2 S1
ipri
vT2
iLo1
iLo2
iSR2iSR1
t0 t1 t2 t3 t4
(Vin-VCb)/Lm -VCb/Lm
(Vin-VCb)/n
-VCb/n
-VO/LO1
-VO/LO2
(VCb/n-VO)/LO2
((Vin-VCb)/n-VO)/
LO1
diLo1+diLo2 diLo1+diLo2
im
t
t
t
t
t
Dloss2TS
Vo
Ns
L201
L202
Low side drivers
Qdr1
Qdr2
N3
N4
FAN3224
INA
INB OUTA
OUTB
ENA
ENB

FAN3223/4/5 Dual 4A Drivers
 20V Abs Max (18V Max
Operation)
 3x3mm MLP-8 and SOIC-8
 Dual 5A-peak sink & source
(4.3A sink/2.8A src. at Vdd/2)
 CMOS or TTL input thresholds
 10ns fall time with 2.2nF load
 Prop delays < 20ns
 Under-Voltage Lockout
 Industry standard pin-outs
 Dual Inverting & dual Non-
Inverting with dual Enable
 Dual-Input version
 Enable defaults to “ON”
 Fail-Safe Inputs: Output held
low if no input signal
6 VDD
7 OUTA
VDD_OK
5 OUTB
Inverting
(FAN3223)
INA 2
100k
ENA 1
GND 3
VDD
Smart
Start-up
100k
8
VDD
ENB
Inverting
(FAN3223)
INB 4
100k
100k
100k
100k
100k
100k
Non-Inverting
(FAN3224)
Non-Inverting
(FAN3224)
UVLO
Part of the family of
High-Performance
Low-side Gate
Drivers from
Fairchild

Design Methodology
AC-DC 300W POWER SUPPLY DESIGN SPECIFICATIONS
Interleaved BCM PFC Section
MIN TYP MAX
VIN_AC 90V 120V 265V
FVIN_AC 50Hz 60Hz 65Hz
VOUT_PFC 389.5V 390V 391.25V
VOUT_PFC_RIPPLE 10V 11V
POUT_PFC 340W 350W
FSW_PFC 18kHz 300kHz
tHOLD_UP 20ms
tSOFT_START 250ms 300ms
tON_OVERSHOOT 10V
η_PFC_120V 97% 97.5%
η_PFC_230V 98% 98.6%
PF_120V 0.990
PF_230V 0.983
DC-DC Converter Section
VOUT_AHB 12.22 12.2V 12.25
VOUT_AHB_RIPPLE 0.12VPP 0.13VPP
VOUT_AHB_REGULATION 0.12% 0.16%
POUT_AHB 310W
IOUT_AHB 0A 25A
FSW_AHB 120kHz
η_AHB 92% 93.3%
η_TOTAL 90% 92%
Mechanical and Thermal
Height 18mm
θJC 60⁰C
 Primary Design Goals:
1. Maximize Wide Range Efficiency
2. Lowest Possible Design Profile
3. Minimize Heat Sinks
4. Conventional Design Methods

Interleaved PFC Section
EMI Filter and Bridge Rectifier

FAN9612 Interleaved BCM PFC Schematic

FAN9612 PFC Steady State VGS and VDS
 120VAC Input, IOUT=12.5ADC
 Always ZVS
 No Coss turn-on loss
 230VAC Input, IOUT=12.5ADC
 ZVS when VIN < ½ VOUT
 No Coss turn-on loss
 Valley Switching for VIN > ½ VOUT
 Minimizes Coss turn-on loss
VGS1
VGS2
VDS1
VDS1
Valley SwitchingZVS

FAN9612 230VAC Switching, VGS and VDS
 230VAC Input, IOUT=25ADC
 VIN > ½ VOUT
 Valley Switching Shown
 Minimizes Coss turn-on loss
VGS1
VDS1
IL1
 VIN < ½ VOUT
 ZVS Shown
 Eliminates Coss turn-on loss

FAN9612 PFC Current Waveforms
IIN
IL1
IL2
IL1+IL2

FAN9612 Interleaved PFC Current Waveforms
 230VAC Input, IOUT=25ADC 120VAC Input, IOUT=25ADC
IL1
IL2
IL1+IL2

FAN9612 Interleaved Current Waveforms
 3Ap Inductor Ripple Current
 1.4App Cancellation Current
 53% Ripple Current Reduction
 5Ap Inductor Ripple Current
 1.6App Cancellation Current
 68% Ripple Current Reduction
IL1
IL2
IL1+IL2
IL1
IL2
IL1+IL2

FAN9612 Phase Management Waveforms
 120VAC, 390VDC, IOUT_PFC=0.107ADC
 POUT_MAX=340W
 2 Phase to 1 Phase at 41.75W
 12% (default) Phase Threshold
 POUT_MAX=340W
VGS1
VGS2
IL1
IL2

FAN9612 Phase Management Waveforms
1 Phase to 2 Phase
 POUT_MAX=340W
 POUT_MAX=340W
VGS1
VGS2
IL1
IL2

FAN9612 PFC VOUT Start-Up Waveforms
 Closed Loop Soft-Start
 0V Overshoot
 <10V Overshoot
 <2.5% for 390V Output
VGS1
VOUT
IL1
IIN

FAN9612 PFC VOUT Start-Up Waveforms
 0V Overshoot
 <10V Overshoot
 <2.5% for 390V Output
VGS1
VOUT
IL1
IIN

FAN9612 120VAC Input Current and FFT
 120VAC, VOUT=12VDC, IOUT=25ADC
 100% Load
 PF=0.991
 FSW_AHB=120kHz
 35kHz<FSW_PFC<300kHz
 20% Load
 PF=0.952
 FSW_AHB=120kHz
VIN
IIN
IIN_FFT

FAN9612 230VAC Input Current FFT
 100% Load
 PF=0.983
 FSW_AHB=120kHz
 20% Load
 PF=0.879
 FSW_AHB=120kHz
VIN
IIN
IIN_FFT

FAN9612 Interleaved BCM PFC Efficiency
100%=340W
70%
75%
80%
85%
90%
95%
100%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Efficiency(%)
Output Power (%)
FAN9612 Interleaved BCM PFC Measured Efficiency
120 Vac 230 Vac
 >97% for 20%<POUT<100%, 120VAC Input, 97.5% peak
 >98% for POUT>40%, 230Vac Input, 98.6% peak

100%=300W
 >90% for POUT > 38% (114W)
 91% Peak for 120VAC, 92% Peak for 230VAC
70%
75%
80%
85%
90%
95%
100%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Efficiency(%)
Output Power (%)
120 Vac
230 Vac

FAN9612 Interleaved BCM PFC
AC-DC System Power Factor
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
PowerFactor
Output Power (%)
FAN9612 AC-DC Measured Power Factor
120 Vac 230 Vac
 PF>0.9 for 20%<POUT<100%, 120VAC<VIN<230VAC

Asymmetrical Half-Bridge (AHB) Section

FSFA2100 AHB DC-DC Schematic

FSFA2100 AHB Primary ZVS Waveforms
No Load
 VIN=390VDC, VOUT=12VDC, IOUT=0ADC
 ZVS Turn-On down to 0% Load
 Soft Commutation of Current
 AHB Limits VDS to VIN
 ZVS Turn-On down to 0 Load
VDS(High)
(200X Probe)
ID
ZVS
390V

FSFA2100 AHB Primary ZVS Waveforms
Full Load
 ZVS Turn-On at 100% Load
 AHB Limits VDS to VIN
VDS(High)
(200X Probe)
ID
ZVS
390V

FSFA2100 AHB Current Doubler Rectifier
 Asymmetrical Voltage Stress
 VDS_SR1 = 60V spike
 D = 38%
 Self Driven SR (FAN3224T)
 Asymmetrical Voltage Stress
 D = 33%
VDS_SR1
VGS_SR1
VDS_SR2
VGS_SR2
20V
43V

No Load SR Dead Time
 Falling Edge SR Dead Time
 VGS_SR1_R to VGS_SR2_F = 30ns
 Rising Edge SR Dead Time
 VGS_SR1_F to VGS_SR2_R = 27ns
VDS_SR1
VGS_SR1
VDS_SR2
VGS_SR2
VDS_SR1
VGS_SR1
VDS_SR2
VGS_SR2

Full Load SR Dead Time
 Falling Edge SR Dead Time
 VGS_SR1_R to VGS_SR2_F = 380ns
 12:1 Variation verses Load
 Rising Edge SR Dead Time
 VGS_SR1_F to VGS_SR2_R = 260ns
 10:1 Variation verses Load
 Total SR Body-Diode Conduction Loss
 PBDC_SR1=1.54W, PBDC_SR2=0.86W
 0.8% Total Overall Efficiency Penalty
VDS_SR1
VGS_SR1
VDS_SR2
VGS_SR2
VDS_SR1
VGS_SR1
VDS_SR2
VGS_SR2

Output Ripple Current Cancellation
 Asymmetrical Current Distribution
 IL_SR1 = 6.4APP, 11.10ARMS
 IL_SR2 = 8.6APP, 14.07ARMS
 Ripple Current Cancellation
 IL_SUM = 5.4APP, 25ARMS
 37% reduction eases filter cap
 Asymmetrical Current Distribution
 IL_SR1 = 4APP, 0.89ARMS
 IL_SR2 = 8.2APP, 2.13ARMS
 Ripple Current Cancellation
 IL_SUM = 5.8APP, 1.28ARMS
 29% Reduction
IL_SR1
VGS_SR1
VGS_SR2
IL_SR2
IL_TOTAL(MATH FUNCTION)
NOTE: Additional Ringing Due to Current Doubler Loops Installed for Measurement
IL_SUM(MATH FUNCTION)
IL_SUM(MATH FUNCTION)

FSFA2100 AHB Output Ripple Voltage
 VIN=390VDC, VOUT=12.2VDC, IOUT=25ADC
 VOUT Capacitor Ripple Voltage
 VOUT_AC = 120mVPP
 0.98% of 12.2V
 VIN=390VDC, VOUT=12.2VDC, IOUT=0ADC
 VOUT Capacitor Ripple Voltage
 VOUT_AC = 130mVPP
 1.06% of 12.2V
VGS_SR1
VGS_SR2
VOUT_AC
NOTE: Additional Ringing Due to Current Doubler Loops Installed for Measurement

FSFA2100 AHB DC-DC Efficiency
100%=300W
 93% at Full Load (12V, 25A)
 93.3% Peak at 50% Load
70%
75%
80%
85%
90%
95%
100%
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Efficiency(%)
Output Power (%)
FSFA2100 AHB DC-DC Efficiency

Output Voltage Regulation
12.10
12.12
12.14
12.16
12.18
12.20
12.22
12.24
12.26
12.28
12.30
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
VOUT(VDC)
Output Power (%)
Output Voltage Regulation for AC-DC System
120 Vac
230 Vac
 0.16% for Full Load Range at 120VAC
 0.11% for Full Load Range at 230VAC

www.fairchildsemi.com
RELATED MATERIALS
Appendix
42

Single Phase CCM PFC
IL (1-D)TsDTs
Ts
IL
IDIsw
(Not to scale)
 Benefits
 Peak to RMS ratio lower
 Lower I2R losses
 Lower ripple current
 Lower core loss
 Lower EMI
 Smaller input filter
 Can be used at any power level
 Easily interleaved for power levels to many
KW’s.
 Challenges
 Requires very fast boost diode with low
IRR
 Silicon carbide diodes are often used
 Large inductor
 MOSFET switching loss (hard switching)

Single Phase BCM PFC
(Not to scale)
IL
DTs
Ts
IDIsw
 Benefits
 Simple to design, well understood control
technique
 Lower I2R losses
 MOSFET turns on at zero current and
minimum voltage
 Lower core loss
 No reverse recovery in boost diode
 Low cost fast recovery diode can be used
 Lower current sensing loss compared to CCM
 Challenges
 Higher MOSFET conduction losses
 Variable frequency
 High peak current limits practical use to 300W
 Impact on EMI filter size

Asymmetrical Half-Bridge (AHB) Converter
Square wave generator
 produces a square wave voltage (Vd) by driving switches Q1 and Q2 complementarily
Energy transfer network
 removes DC offset of the square wave voltage (Vd) using DC blocking capacitor (CB)
 transfers a pure AC square wave voltage to the secondary through the transformer
 Causes Ip to lag Vpr to provide ZVS condition for Q1 and Q2
Rectifier network
 produces a DC voltage by rectifying the AC voltage with rectifier diodes and a low-pass
LC filter
+
VO
-
Ro
Q1
Q2
n:1
Ip
Llkp
LmCB
Ids2
Im
ILO
Vin
Io
+
Vd
-
Square wave generator
Energy transfer network Rectifier network
VCB
+
Vpr
-
+
Vrec
-
Ids1
C2
C1
1-D
D

Asymmetrical Half-Bridge Converter
D1
D2
L
CO
NP
NS
Q1
NS
Q2
CIN
C1
C2
VP
VP
IP
Q2 (D)
Q1 (D)
VIN/2
-VIN/2
D=0.46 D=0.23
VIN/2
-VIN/2
VP
IP
Q2 (D)
Q1 (1-D)
VC1
VC2
VC1
VC2
D=0.46 D=0.23
Equal
Area
(a) Symmetrical HB waveforms
(b) Asymmetrical HB waveforms
 Asymmetrical Gate Drive
 Q2 modulated by D
 Q1 driven by 1-D
 Fixed dead time between Q1 and Q2
 Dead time optimized for ZVS and anti cross
conduction
 Fixed frequency ZVS PWM operation
 Near D=0.5, operation is same as symmetrical HB
INC VDV 1
  INC VDV  12
 DD
N
N
V
V
P
S
IN
O
 12

Current Doubler Rectifier
D1
D2
L
CO
NP
NS
NS
VO
D1
D2
L CO
NP
NS
NS
VO
D1
D2
CO
VO
V
I
V
What is it? - A full wave alternative rectification technique compatible
with all double ended converter topologies
D1
D2
CO
VO
V
I
I
D1
D2
CO
VO
L2
L1
NP
NS
NP
NS
D1
D2
L1
CO
L2
VO
NP
Q1
L1
CO
NS
L2
Q2
VO
OR
Current Doubler
Derivation of Current Doubler
(a) (b) (c) (d)
(e)
(f) (g)

Synchronous Rectification (SR)
D1
D2
L
CO
NP NS
CIN
Q1
Reset
Circuit
Efficiency vs Output Voltage
Vf=0.4V, Vf=1V
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.5 1.7 2.8 4.0 5.1 6.3 7.4 8.6 9.7 10.9 12.0
Output Voltage (V)
Efficiency
Vf=0.4V Vf=1V
Q2
Q3
L
CO
NP NS
CIN
Q1
Reset
Circuit
 What is Synchronous Rectification?
 Replacing secondary side discrete
rectifiers (D1, D2) with MOSFETs (Q2, Q3)
 Benefits of SR
 Parallel MOSFETs
 Increase efficiency
 Lower output voltage and higher
current applications benefit most
 How do we drive them?
OUT
FOUTFOUTOUT
OUTOUT
IN
OUT
V
VIVIV
IV
P
P





1
1


APEC 2010 ACDC Live Demo Tech SessionPresentation_Feb 19 2010

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