We propose a phase-locked loop (PLL) architecture, which reduces the double frequency ripple without increasing the order of loop filter. Proposed architecture uses quadrature numerically–controlled oscillator (NCO) to provide two output signals with phase difference of π/2. One of them is subtracted from the input signal before multiplying with the other output of NCO. The system also provides stability in case the input signal has noise in amplitude or phase. The proposed structure is implemented using field programmable gate array (FPGA), which dissipates 15.44mw and works at clock frequency of 155.8 MHz.
Frequency and Power Estimator for Digital Receivers in Doppler Shift Environm...CSCJournals
A frequency estimator well suited for digital receivers is proposed. Accurate estimates of unknown frequency and power of input sinusoidal signal, in the presence of additive white Gaussian noise (AWGN), are provided. The proposed structure solve the problems of traditional phase locked loop (PLL) such as, narrow tracking range, overshoot, long settle time, double frequency ripples in the loop and stability. Proposed method can estimate frequencies up to half the sampling frequency irrespective of the input signal power. Furthermore, it provides stability and allows fast tracking for any changes in input frequency. The estimator is also implemented using field programmable gate array (FPGA), consumes 127 mW and works at a frequency of 225 MHz. Proposed method can estimate the fluctuation in frequency of transmitter’s oscillator, can be used as a frequency shift keying receiver and can also be applied as a digital receiver in Doppler shift environment.
A Simple Design to Mitigate Problems of Conventional Digital Phase Locked LoopCSCJournals
This paper presents a method which can estimate frequency, phase and power of received signal corrupted with additive white Gaussian noise (AWGN) in large frequency offset environment. Proposed method consists of two loops, each loop is similar to a phase–locked loop (PLL) structure. The proposed structure solves the problems of conventional PLL such as limited estimation range, long settling time, overshoot, high frequency ripples and instability. Traditional inability of PLL to synchronize signals with large frequency offset is also removed in this method. Furthermore, proposed architecture along with providing stability, ensures fast tracking of any changes in input frequency. Proposed method is also implemented using field programmable gate array (FPGA), it consumes 201 mW and works at 197 MHz.
A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Os...CSCJournals
The objective of this paper is to explore the analysis and design of second order digital phase-locked loop (DPLL), and present low power architecture for DPLL. The proposed architecture aims to reduce the high power consumption of DPLL, which results from using a read only memory (ROM) in implementation of the numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, in which no ROM is used. DPLL is deigned and implemented using FPGA, consumed 237 mw, which saves more than 25% of power consumption, and works at faster clock frequency compared to traditional architecture.
This document provides an overview of angle modulation techniques including frequency modulation (FM) and phase modulation (PM). It defines PM and FM mathematically. For PM, the phase deviation is a linear function of the baseband message signal. For FM, the instantaneous frequency deviation is a linear function of the message signal. The key advantages of FM and PM over amplitude modulation are constant envelope and better noise immunity. However, FM and PM require increased bandwidth compared to amplitude modulation. The document derives expressions for the pre-envelope and spectrum of an FM signal and discusses bandwidth requirements of FM.
This chapter discusses sampling and signal reconstruction from samples. It introduces the sampling theorem which states that a signal must be sampled at a rate at least twice its highest frequency component to avoid aliasing. It describes how to reconstruct the original signal from its samples using an interpolation formula. It also discusses the effects of undersampling and oversampling, and how aliasing can occur if the sampling rate is too low.
This document discusses concepts related to signals and systems. It begins by defining a signal as a time-varying quantity of information and a system as an entity that processes input signals to produce output signals. It then covers signal classification including continuous vs discrete time, analog vs digital, periodic vs aperiodic, deterministic vs random, and causal vs non-causal signals. Signal operations like time shifting, scaling, and inversion are described. Key concepts discussed in detail include signal size using energy and power, signal components and orthogonality, correlation as a measure of signal similarity, and trigonometric Fourier series. Worked examples are provided to illustrate various topics.
Ch6 digital transmission of analog signal pg 99Prateek Omer
This document discusses digital transmission of analog signals using techniques like Pulse Code Modulation (PCM), Differential Pulse Code Modulation (DPCM), and Delta Modulation (DM).
It begins by introducing the benefits of digital transmission over analog transmission, such as regeneration of signals to eliminate distortion and noise, easy storage and forwarding of messages, and multiplexing of signals.
It then describes the basic operations in PCM - time discretization through sampling and amplitude discretization through quantization. A PCM system samples an analog signal, quantizes the samples, encodes the quantized values into binary code words, transmits the code words digitally, decodes and reconstructs the analog signal from the samples.
This document contains a summary of key concepts from a chapter on Fourier transforms and their properties. It begins with an overview of the motivation for Fourier transforms as an extension of Fourier series to allow representation of aperiodic signals. It then provides examples of Fourier transforms for common functions like a rectangular pulse and exponential. The remainder summarizes important properties of Fourier transforms including: time-frequency duality, symmetry of direct and inverse transforms, scaling which relates time/bandwidth compression, time-shifting which causes phase change, and frequency-shifting which translates the spectrum.
Frequency and Power Estimator for Digital Receivers in Doppler Shift Environm...CSCJournals
A frequency estimator well suited for digital receivers is proposed. Accurate estimates of unknown frequency and power of input sinusoidal signal, in the presence of additive white Gaussian noise (AWGN), are provided. The proposed structure solve the problems of traditional phase locked loop (PLL) such as, narrow tracking range, overshoot, long settle time, double frequency ripples in the loop and stability. Proposed method can estimate frequencies up to half the sampling frequency irrespective of the input signal power. Furthermore, it provides stability and allows fast tracking for any changes in input frequency. The estimator is also implemented using field programmable gate array (FPGA), consumes 127 mW and works at a frequency of 225 MHz. Proposed method can estimate the fluctuation in frequency of transmitter’s oscillator, can be used as a frequency shift keying receiver and can also be applied as a digital receiver in Doppler shift environment.
A Simple Design to Mitigate Problems of Conventional Digital Phase Locked LoopCSCJournals
This paper presents a method which can estimate frequency, phase and power of received signal corrupted with additive white Gaussian noise (AWGN) in large frequency offset environment. Proposed method consists of two loops, each loop is similar to a phase–locked loop (PLL) structure. The proposed structure solves the problems of conventional PLL such as limited estimation range, long settling time, overshoot, high frequency ripples and instability. Traditional inability of PLL to synchronize signals with large frequency offset is also removed in this method. Furthermore, proposed architecture along with providing stability, ensures fast tracking of any changes in input frequency. Proposed method is also implemented using field programmable gate array (FPGA), it consumes 201 mW and works at 197 MHz.
A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Os...CSCJournals
The objective of this paper is to explore the analysis and design of second order digital phase-locked loop (DPLL), and present low power architecture for DPLL. The proposed architecture aims to reduce the high power consumption of DPLL, which results from using a read only memory (ROM) in implementation of the numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, in which no ROM is used. DPLL is deigned and implemented using FPGA, consumed 237 mw, which saves more than 25% of power consumption, and works at faster clock frequency compared to traditional architecture.
This document provides an overview of angle modulation techniques including frequency modulation (FM) and phase modulation (PM). It defines PM and FM mathematically. For PM, the phase deviation is a linear function of the baseband message signal. For FM, the instantaneous frequency deviation is a linear function of the message signal. The key advantages of FM and PM over amplitude modulation are constant envelope and better noise immunity. However, FM and PM require increased bandwidth compared to amplitude modulation. The document derives expressions for the pre-envelope and spectrum of an FM signal and discusses bandwidth requirements of FM.
This chapter discusses sampling and signal reconstruction from samples. It introduces the sampling theorem which states that a signal must be sampled at a rate at least twice its highest frequency component to avoid aliasing. It describes how to reconstruct the original signal from its samples using an interpolation formula. It also discusses the effects of undersampling and oversampling, and how aliasing can occur if the sampling rate is too low.
This document discusses concepts related to signals and systems. It begins by defining a signal as a time-varying quantity of information and a system as an entity that processes input signals to produce output signals. It then covers signal classification including continuous vs discrete time, analog vs digital, periodic vs aperiodic, deterministic vs random, and causal vs non-causal signals. Signal operations like time shifting, scaling, and inversion are described. Key concepts discussed in detail include signal size using energy and power, signal components and orthogonality, correlation as a measure of signal similarity, and trigonometric Fourier series. Worked examples are provided to illustrate various topics.
Ch6 digital transmission of analog signal pg 99Prateek Omer
This document discusses digital transmission of analog signals using techniques like Pulse Code Modulation (PCM), Differential Pulse Code Modulation (DPCM), and Delta Modulation (DM).
It begins by introducing the benefits of digital transmission over analog transmission, such as regeneration of signals to eliminate distortion and noise, easy storage and forwarding of messages, and multiplexing of signals.
It then describes the basic operations in PCM - time discretization through sampling and amplitude discretization through quantization. A PCM system samples an analog signal, quantizes the samples, encodes the quantized values into binary code words, transmits the code words digitally, decodes and reconstructs the analog signal from the samples.
This document contains a summary of key concepts from a chapter on Fourier transforms and their properties. It begins with an overview of the motivation for Fourier transforms as an extension of Fourier series to allow representation of aperiodic signals. It then provides examples of Fourier transforms for common functions like a rectangular pulse and exponential. The remainder summarizes important properties of Fourier transforms including: time-frequency duality, symmetry of direct and inverse transforms, scaling which relates time/bandwidth compression, time-shifting which causes phase change, and frequency-shifting which translates the spectrum.
Ch7 noise variation of different modulation scheme pg 63Prateek Omer
This document summarizes the noise performance of various modulation schemes. It begins by introducing a receiver model and defining figures of merit used to evaluate performance. It then analyzes the noise performance of coherent demodulation for DSB-SC and SSB modulation. The following key points are made:
1) Coherent detection of DSB-SC signals results in signal and noise being additive at both the input and output of the detector. The detector completely rejects the quadrature noise component.
2) For DSB-SC, the output SNR and reference SNR are equal, resulting in a figure of merit of 1.
3) Analysis of SSB modulation shows it achieves a 3 dB improvement in output SNR over
Detection of Power Line Disturbances using DSP TechniquesKashishVerma18
This document summarizes Kashish Verma's presentation on detecting power line disturbances using digital signal processing techniques. It discusses using Simulink models to simulate normal and disturbed power systems. Various DSP techniques for frequency estimation like Prony analysis, FFT, SVD, MUSIC, and ESPIRIT are described along with their advantages and drawbacks. Detection of faults during power swings using methods like Prony analysis, wavelet transform, and ANFIS is also summarized. Overall, the document provides an overview of modeling power systems and applying DSP for fault detection and frequency estimation.
This document discusses correlative-level coding and its applications in baseband pulse transmission systems. Correlative-level coding introduces controlled intersymbol interference to increase signaling rate. It allows partial response signaling and maximum likelihood detection at the receiver. Specific techniques discussed include duobinary signaling and modified duobinary signaling. The document also covers tapped-delay line equalization using adaptive algorithms like least mean square to compensate for channel distortion. Decision feedback equalization and its implementation are summarized as well. Eye patterns are described as a tool to evaluate signal quality in such systems.
The document discusses intersymbol interference (ISI) in baseband data transmission. ISI arises from deviations in a communication channel's frequency response from ideal, causing received pulses to be affected by neighboring pulses. This can be mitigated by matched filtering to maximize signal-to-noise ratio or by controlling the received pulse shape when noise is negligible. ISI causes the sampled output to depend on neighboring transmitted bits. Distortionless transmission requires designing transmit and receive filters such that only the desired bit contributes to the sampled output.
Nyquist criterion for distortion less baseband binary channelPriyangaKR1
binary transmission system
From design point of view – frequency response of the channel and transmitted pulse shape are specified; the frequency response of the transmit and receive filters has to be determined so as to reconstruct [bk]
This document provides an introduction to signals and systems. It begins by classifying different types of signals as continuous-time/discrete-time, analog/digital, deterministic/random, periodic/aperiodic, power/energy. It then discusses representations of signals in the time and frequency domains, including the Fourier series representation of periodic signals. Key concepts covered include the unit step, rectangular, triangular and sinc functions, as well as signal operations like time shifting, scaling and inversion. The document concludes by introducing Parseval's theorem relating the power of a signal to the power of its Fourier coefficients.
This lecture covers signal and systems analysis, including:
1) Definitions of signals, systems, and their properties like time-invariance, linearity, stability, causality, and memory.
2) Classification of signals as continuous-time vs discrete-time, analog vs digital, deterministic vs random, periodic vs aperiodic.
3) Concepts of orthogonality, correlation, autocorrelation as they relate to signal comparison.
4) Review of the Fourier series and Fourier transform as tools to represent signals in the frequency domain.
The document discusses sampling theory and analog-to-digital conversion. It begins by explaining that most real-world signals are analog but must be converted to digital for processing. There are three steps: sampling, quantization, and coding. Sampling converts a continuous-time signal to a discrete-time signal by taking samples at regular intervals. The sampling theorem states that the sampling frequency must be at least twice the highest frequency of the sampled signal to avoid aliasing. Finally, it provides an example showing how to calculate the minimum sampling rate, or Nyquist rate, given the highest frequency of a signal.
The document discusses Fast Fourier Transform (FFT) analysis. It begins by explaining what Fourier Transform and Discrete Fourier Transform (DFT) are and how they convert signals from the time domain to the frequency domain. It then states that FFT is an efficient algorithm for performing DFT, allowing it to be done much faster on computers. The document proceeds to describe different types of FFT algorithms like Cooley-Tukey, Prime Factor, Bruun's, and Rader's algorithms. It concludes by discussing characteristics of FFT like approximation, accuracy, and complexity bounds, as well as applications and how FFT can be used to analyze vibration signals in the frequency domain.
The document defines and classifies different types of signals including:
- Continuous-time and discrete-time signals
- Analog and digital signals
- Real and complex signals
- Deterministic and random signals
- Periodic and non-periodic signals
It also introduces important signal properties and functions including the unit-step function, unit-impulse (Dirac delta) function, and complex exponential and sinusoidal signals. Graphical representations and mathematical definitions are provided for key signals and functions.
DSP_2018_FOEHU - Lec 06 - FIR Filter DesignAmr E. Mohamed
This lecture discusses the design of finite impulse response (FIR) filters. It introduces the window method for FIR filter design, which involves truncating the ideal impulse response with a window function to obtain a causal FIR filter. Common window functions are presented such as rectangular, triangular, Hanning, Hamming, and Blackman windows. These windows trade off main lobe width and side lobe levels. The document provides an example design of a low-pass FIR filter using the Hamming window to meet given passband and stopband specifications.
fast-Fourier-transform-presentation and Fourier transform for wave
in
signal possessing for
physics and
geophysics
spectra analysis
periodic and non periodic wave
data sampling
The Nyquist frequency
This document provides an overview of signals and systems. It defines key terms like signal, system, continuous and discrete time signals, analog and digital signals, periodic and aperiodic signals. It also discusses different types of signals like deterministic and probabilistic signals, energy and power signals. The document then classifies systems as linear/nonlinear, time-invariant/variant, causal/non-causal, and with/without memory. It provides examples of different signals and properties of signals like magnitude scaling, time shifting, reflection and scaling. Overall, the document introduces fundamental concepts in signals and systems.
Dsp 2018 foehu - lec 10 - multi-rate digital signal processingAmr E. Mohamed
This document discusses multi-rate digital signal processing and concepts related to sampling continuous-time signals. It begins by introducing discrete-time processing of continuous signals using an ideal continuous-to-discrete converter. It then covers the Nyquist sampling theorem and relationships between continuous and discrete Fourier transforms. It discusses ideal and practical reconstruction using zero-order hold and anti-imaging filters. Finally, it introduces the concepts of downsampling and upsampling in multi-rate digital signal processing systems.
DSP_2018_FOEHU - Lec 02 - Sampling of Continuous Time SignalsAmr E. Mohamed
The document discusses sampling of continuous-time signals. It defines different types of signals and sampling methods. Ideal sampling involves multiplying the signal by a train of impulse functions to select sample values at regular intervals. For practical sampling, a train of rectangular pulses is used to approximate ideal sampling. Flat-top sampling is achieved by convolving the ideally sampled signal with a rectangular pulse, resulting in samples held at a constant height for the sample period. The Nyquist sampling theorem states that a signal must be sampled at least twice its maximum frequency to avoid aliasing when reconstructing the original signal from samples. An anti-aliasing filter can be used before sampling to prevent aliasing from high frequencies above half the sampling rate.
The document discusses sampling of continuous-time signals to create discrete-time signals. It explains that for perfect reconstruction, the sampling frequency must be greater than twice the maximum frequency of the original continuous-time signal, as specified by the Nyquist rate. A common method for sampling is to use an impulse train, and then reconstruct the signal by passing it through a low-pass filter. Often a zero-order hold is used to sample and communicate the signal, which simply holds each value until the next sample, and this provides a sufficiently accurate reconstructed continuous-time signal.
The discrete Fourier transform has many applications in science and engineering. For example, it is often used in digital signal processing applications such as voice recognition and image processing.
The document analyzes a method for comparing two audio files to detect human errors using fast Fourier transforms (FFT). It describes using FFT to convert audio files from the time domain to the frequency domain. It then calculates the mean squared error (MSE) between the normalized spectral densities of the two files. A low MSE would indicate the files are identical, while a higher MSE shows a difference. The document provides the steps and flowchart used, and includes examples of Matlab and Labview code implementing the comparison method on identical and non-identical audio files.
Ch7 noise variation of different modulation scheme pg 63Prateek Omer
This document summarizes the noise performance of various modulation schemes. It begins by introducing a receiver model and defining figures of merit used to evaluate performance. It then analyzes the noise performance of coherent demodulation for DSB-SC and SSB modulation. The following key points are made:
1) Coherent detection of DSB-SC signals results in signal and noise being additive at both the input and output of the detector. The detector completely rejects the quadrature noise component.
2) For DSB-SC, the output SNR and reference SNR are equal, resulting in a figure of merit of 1.
3) Analysis of SSB modulation shows it achieves a 3 dB improvement in output SNR over
Detection of Power Line Disturbances using DSP TechniquesKashishVerma18
This document summarizes Kashish Verma's presentation on detecting power line disturbances using digital signal processing techniques. It discusses using Simulink models to simulate normal and disturbed power systems. Various DSP techniques for frequency estimation like Prony analysis, FFT, SVD, MUSIC, and ESPIRIT are described along with their advantages and drawbacks. Detection of faults during power swings using methods like Prony analysis, wavelet transform, and ANFIS is also summarized. Overall, the document provides an overview of modeling power systems and applying DSP for fault detection and frequency estimation.
This document discusses correlative-level coding and its applications in baseband pulse transmission systems. Correlative-level coding introduces controlled intersymbol interference to increase signaling rate. It allows partial response signaling and maximum likelihood detection at the receiver. Specific techniques discussed include duobinary signaling and modified duobinary signaling. The document also covers tapped-delay line equalization using adaptive algorithms like least mean square to compensate for channel distortion. Decision feedback equalization and its implementation are summarized as well. Eye patterns are described as a tool to evaluate signal quality in such systems.
The document discusses intersymbol interference (ISI) in baseband data transmission. ISI arises from deviations in a communication channel's frequency response from ideal, causing received pulses to be affected by neighboring pulses. This can be mitigated by matched filtering to maximize signal-to-noise ratio or by controlling the received pulse shape when noise is negligible. ISI causes the sampled output to depend on neighboring transmitted bits. Distortionless transmission requires designing transmit and receive filters such that only the desired bit contributes to the sampled output.
Nyquist criterion for distortion less baseband binary channelPriyangaKR1
binary transmission system
From design point of view – frequency response of the channel and transmitted pulse shape are specified; the frequency response of the transmit and receive filters has to be determined so as to reconstruct [bk]
This document provides an introduction to signals and systems. It begins by classifying different types of signals as continuous-time/discrete-time, analog/digital, deterministic/random, periodic/aperiodic, power/energy. It then discusses representations of signals in the time and frequency domains, including the Fourier series representation of periodic signals. Key concepts covered include the unit step, rectangular, triangular and sinc functions, as well as signal operations like time shifting, scaling and inversion. The document concludes by introducing Parseval's theorem relating the power of a signal to the power of its Fourier coefficients.
This lecture covers signal and systems analysis, including:
1) Definitions of signals, systems, and their properties like time-invariance, linearity, stability, causality, and memory.
2) Classification of signals as continuous-time vs discrete-time, analog vs digital, deterministic vs random, periodic vs aperiodic.
3) Concepts of orthogonality, correlation, autocorrelation as they relate to signal comparison.
4) Review of the Fourier series and Fourier transform as tools to represent signals in the frequency domain.
The document discusses sampling theory and analog-to-digital conversion. It begins by explaining that most real-world signals are analog but must be converted to digital for processing. There are three steps: sampling, quantization, and coding. Sampling converts a continuous-time signal to a discrete-time signal by taking samples at regular intervals. The sampling theorem states that the sampling frequency must be at least twice the highest frequency of the sampled signal to avoid aliasing. Finally, it provides an example showing how to calculate the minimum sampling rate, or Nyquist rate, given the highest frequency of a signal.
The document discusses Fast Fourier Transform (FFT) analysis. It begins by explaining what Fourier Transform and Discrete Fourier Transform (DFT) are and how they convert signals from the time domain to the frequency domain. It then states that FFT is an efficient algorithm for performing DFT, allowing it to be done much faster on computers. The document proceeds to describe different types of FFT algorithms like Cooley-Tukey, Prime Factor, Bruun's, and Rader's algorithms. It concludes by discussing characteristics of FFT like approximation, accuracy, and complexity bounds, as well as applications and how FFT can be used to analyze vibration signals in the frequency domain.
The document defines and classifies different types of signals including:
- Continuous-time and discrete-time signals
- Analog and digital signals
- Real and complex signals
- Deterministic and random signals
- Periodic and non-periodic signals
It also introduces important signal properties and functions including the unit-step function, unit-impulse (Dirac delta) function, and complex exponential and sinusoidal signals. Graphical representations and mathematical definitions are provided for key signals and functions.
DSP_2018_FOEHU - Lec 06 - FIR Filter DesignAmr E. Mohamed
This lecture discusses the design of finite impulse response (FIR) filters. It introduces the window method for FIR filter design, which involves truncating the ideal impulse response with a window function to obtain a causal FIR filter. Common window functions are presented such as rectangular, triangular, Hanning, Hamming, and Blackman windows. These windows trade off main lobe width and side lobe levels. The document provides an example design of a low-pass FIR filter using the Hamming window to meet given passband and stopband specifications.
fast-Fourier-transform-presentation and Fourier transform for wave
in
signal possessing for
physics and
geophysics
spectra analysis
periodic and non periodic wave
data sampling
The Nyquist frequency
This document provides an overview of signals and systems. It defines key terms like signal, system, continuous and discrete time signals, analog and digital signals, periodic and aperiodic signals. It also discusses different types of signals like deterministic and probabilistic signals, energy and power signals. The document then classifies systems as linear/nonlinear, time-invariant/variant, causal/non-causal, and with/without memory. It provides examples of different signals and properties of signals like magnitude scaling, time shifting, reflection and scaling. Overall, the document introduces fundamental concepts in signals and systems.
Dsp 2018 foehu - lec 10 - multi-rate digital signal processingAmr E. Mohamed
This document discusses multi-rate digital signal processing and concepts related to sampling continuous-time signals. It begins by introducing discrete-time processing of continuous signals using an ideal continuous-to-discrete converter. It then covers the Nyquist sampling theorem and relationships between continuous and discrete Fourier transforms. It discusses ideal and practical reconstruction using zero-order hold and anti-imaging filters. Finally, it introduces the concepts of downsampling and upsampling in multi-rate digital signal processing systems.
DSP_2018_FOEHU - Lec 02 - Sampling of Continuous Time SignalsAmr E. Mohamed
The document discusses sampling of continuous-time signals. It defines different types of signals and sampling methods. Ideal sampling involves multiplying the signal by a train of impulse functions to select sample values at regular intervals. For practical sampling, a train of rectangular pulses is used to approximate ideal sampling. Flat-top sampling is achieved by convolving the ideally sampled signal with a rectangular pulse, resulting in samples held at a constant height for the sample period. The Nyquist sampling theorem states that a signal must be sampled at least twice its maximum frequency to avoid aliasing when reconstructing the original signal from samples. An anti-aliasing filter can be used before sampling to prevent aliasing from high frequencies above half the sampling rate.
The document discusses sampling of continuous-time signals to create discrete-time signals. It explains that for perfect reconstruction, the sampling frequency must be greater than twice the maximum frequency of the original continuous-time signal, as specified by the Nyquist rate. A common method for sampling is to use an impulse train, and then reconstruct the signal by passing it through a low-pass filter. Often a zero-order hold is used to sample and communicate the signal, which simply holds each value until the next sample, and this provides a sufficiently accurate reconstructed continuous-time signal.
The discrete Fourier transform has many applications in science and engineering. For example, it is often used in digital signal processing applications such as voice recognition and image processing.
The document analyzes a method for comparing two audio files to detect human errors using fast Fourier transforms (FFT). It describes using FFT to convert audio files from the time domain to the frequency domain. It then calculates the mean squared error (MSE) between the normalized spectral densities of the two files. A low MSE would indicate the files are identical, while a higher MSE shows a difference. The document provides the steps and flowchart used, and includes examples of Matlab and Labview code implementing the comparison method on identical and non-identical audio files.
Gonzalo Guerrero appears to be a student taking an economics class in 4th year or grade. The single word "Economía" suggests the document is related to economics. The short document provides little other contextual information to summarize further in 3 sentences or less.
Bhushan S. Bhapkar is a manufacturing engineer with over 9 years of experience in industrial engineering, process engineering, and project management. He has a Bachelor's degree in Mechanical Engineering and is proficient in various engineering software. Bhushan has worked for companies like Alstom Transport India, JCB India, Mahindra & Mahindra, Kirloskar Brothers, and UMAS implementing lean manufacturing techniques to improve productivity, capacity, and reduce costs. His achievements include increasing production capacity by 30% and saving over 1 crore rupees in labor costs. Currently he works as a Process Engineer at Alstom Transport India.
Danny Gaethofs is an expert in designing and implementing electronic business integration solutions with over 20 years of experience. He advises companies on strategies for electronic ordering, invoicing, and collaboration with trading partners. Danny founded the Electronic Business community and developed the concept of an electronic business highway to enable widespread information exchange across industries using open standards.
Nabil Sultan. The disruptive and democratizing credentials of cloud computingCBOD ANR project U-PSUD
The disruptive and democratizing credentials of cloud computing
Nabil Sultan
International conference on
“DATA, DIGITAL BUSINESS MODELS, CLOUD COMPUTING AND ORGANIZATIONAL DESIGN”
24-25 November 2014 ,
Université Paris –Sud
El documento habla sobre el noviazgo y el embarazo en la adolescencia. Explica que el noviazgo es una etapa de enamoramiento con pensamientos frecuentes en la persona amada. También describe el embarazo adolescente y sus consecuencias, incluyendo un mayor riesgo de complicaciones médicas para la madre y el bebé, como bajo peso al nacer o mortalidad materna. Finalmente, señala que el embarazo adolescente puede traer consecuencias psicológicas y sociales como dejar la escuela de manera premat
Nothing Happens Until Someone Sells Something: Enabling Your Sales Channel t...CompellingPM
Too often, those of us in the product marketing role are not doing enough to help our sales team or sales channel be successful. Our typical approach to helping is to provide a new salesperson with some marketing collateral and a product presentation and then wish them luck as they look for prospects and try to close deals with anyone that listens. This approach is sufficient for the star salespeople as they intuitively know how to talk with the right potential buyers about their problems and then show these buyers how to solve these problems with their products or services. But unfortunately, this only represents about 20% of salespeople. The other 80% of sales people need more training and coaching to be successful and we as product marketers need to help them be successful. This is the process of “Sales Enablement”.
What happens when we don’t engage in the sales enablement process? Sales people pursue opportunities that don’t fit well with your solution, speak with the prospects that aren’t really decision makers, sell solutions that you don’t really have and the list can go on. But the overall resulting impact is wasted time and effort in pursuing the wrong opportunities, confusion in the market place and poor sales results.
In this webinar, you’ll learn how to create a Sales Enablement program that will make your sales channel significantly more productive and close better deals faster for your products.
In this webinar, you’ll learn:
Why the typical approach to enabling sales doesn’t work.
The key goals of a successful Sales Enablement program.
The core tools you need to develop to effectively enable your sales channel.
Best practices to make sure the Sales Enablement program is effectively implemented.
Factors affecting the adoption of cloud computing
Lorraine Morgan, Lero, National University of Ireland Galway
-session 6-
International conference on
“DATA, DIGITAL BUSINESS MODELS, CLOUD COMPUTING AND ORGANIZATIONAL DESIGN”
24-25 November 2014,
Université Paris–Sud
Implications of Employers in Conducting Background Checks after the 9/11 Terr...Identity Pi
Employers are willing to show information about potential employees are harmful to employers who are hiring at the moment. One would expect a true converse: employers will be able to find information about their potential employees so they will accept applicants that will be the most qualified candidates who will not harm their fellow employees' customers and clients and will not pose any other risk to the company and their new employer.
Software PLL for PLI synchronization, design, modeling and simulation , sozopoldpdobrev
Power-line interference is a common disturbing
factor in almost all two-electrode biosignal acquisition
applications. Many filtering procedures for mains
interference elimination are available, but all of them are
maximally effective when the filter notches are positioned
exactly at the power-line harmonics, i. e. when the sampling rate is synchronous with the power-line frequency. Moreover, various lock-in techniques, su ch as automatic common mode input impedance balance, require precise in-phase and quadrature phase references, synchronous with the power-line interference. This paper describes in depth a design procedure of software PLL, generating synchronous reference to the common mode power-line interference, and achieved from its analog prototype using s to z backward difference transformation. The main advantage of th e presented
approach is that the synchronization is done in software, so it has no production cost. The presented PLL is intended for use in ECG signal processing, but it can be used after easy adaptation in various digital si gnal processing applications, where frequency synchronization is needed.
Noise and Bandwidth Consideration in Designing Op-Amp Based Transimpedance Am...journalBEEI
In a visible light communication (VLC) system, there are many modules involved. One of the important modules is Transimpedance Amplifier (TIA) that resides in the analog front-end receiver (Rx-AFE). TIA is responsible for performing signal conversion from current signal, which is provided from the photodiode (PD) to voltage signal. It is the reason why the TIA should be operating in low noise condition and wide bandwidth of frequency. These will enable a flexible coverage of the VLC system in performing its signal processing. Hence, in this research, we provide considerations of the noise and frequency bandwidth analysis in designing TIA to cope with the required design specification of a VLC system.
On The Fundamental Aspects of DemodulationCSCJournals
When the instantaneous amplitude, phase and frequency of a carrier wave are modulated with the information signal for transmission, it is known that the receiver works on the basis of the received signal and a knowledge of the carrier frequency. The question is: If the receiver does not have the a priori information about the carrier frequency, is it possible to carry out the demodulation process? This tutorial lecture answers this question by looking into the very fundamental process by which the modulated wave is generated. It critically looks into the energy separation algorithm for signal analysis and suggests modification for distortionless demodulation of an FM signal, and recovery of sub-carrier signals
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An analysis of digital Phase-modulated signals is performed based on frequency spectrum which consists of a continuous and a number of discrete components at multiples of clock frequencies. The analysis shows that these components depend on the pulse shape function of multi-level digital signals to be phase modulated. In this paper, the effect of duty cycle, rise and fall times of these multi-level digital signals, on the frequency spectrum is studied. It is observed that the duty cycle variation of 10% results 30 dB increase in undesired component and the 10% increase in rise & fall times increase the power of undesired component by 12 dB. The theoretical observations of the effects are applied on the Binary Offset Carrier (BOC) modulated signals as a case study, to discuss their effects in Global Navigation Satellite Systems (GNSS).
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Spur Reduction Of MB-OFDM UWB System using CMOS Frequency SynthesizerIDES Editor
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Chapter wise All Notes of First year Basic Civil Engineering.pptxDenish Jangid
Chapter wise All Notes of First year Basic Civil Engineering
Syllabus
Chapter-1
Introduction to objective, scope and outcome the subject
Chapter 2
Introduction: Scope and Specialization of Civil Engineering, Role of civil Engineer in Society, Impact of infrastructural development on economy of country.
Chapter 3
Surveying: Object Principles & Types of Surveying; Site Plans, Plans & Maps; Scales & Unit of different Measurements.
Linear Measurements: Instruments used. Linear Measurement by Tape, Ranging out Survey Lines and overcoming Obstructions; Measurements on sloping ground; Tape corrections, conventional symbols. Angular Measurements: Instruments used; Introduction to Compass Surveying, Bearings and Longitude & Latitude of a Line, Introduction to total station.
Levelling: Instrument used Object of levelling, Methods of levelling in brief, and Contour maps.
Chapter 4
Buildings: Selection of site for Buildings, Layout of Building Plan, Types of buildings, Plinth area, carpet area, floor space index, Introduction to building byelaws, concept of sun light & ventilation. Components of Buildings & their functions, Basic concept of R.C.C., Introduction to types of foundation
Chapter 5
Transportation: Introduction to Transportation Engineering; Traffic and Road Safety: Types and Characteristics of Various Modes of Transportation; Various Road Traffic Signs, Causes of Accidents and Road Safety Measures.
Chapter 6
Environmental Engineering: Environmental Pollution, Environmental Acts and Regulations, Functional Concepts of Ecology, Basics of Species, Biodiversity, Ecosystem, Hydrological Cycle; Chemical Cycles: Carbon, Nitrogen & Phosphorus; Energy Flow in Ecosystems.
Water Pollution: Water Quality standards, Introduction to Treatment & Disposal of Waste Water. Reuse and Saving of Water, Rain Water Harvesting. Solid Waste Management: Classification of Solid Waste, Collection, Transportation and Disposal of Solid. Recycling of Solid Waste: Energy Recovery, Sanitary Landfill, On-Site Sanitation. Air & Noise Pollution: Primary and Secondary air pollutants, Harmful effects of Air Pollution, Control of Air Pollution. . Noise Pollution Harmful Effects of noise pollution, control of noise pollution, Global warming & Climate Change, Ozone depletion, Greenhouse effect
Text Books:
1. Palancharmy, Basic Civil Engineering, McGraw Hill publishers.
2. Satheesh Gopi, Basic Civil Engineering, Pearson Publishers.
3. Ketki Rangwala Dalal, Essentials of Civil Engineering, Charotar Publishing House.
4. BCP, Surveying volume 1
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(𝐓𝐋𝐄 𝟏𝟎𝟎) (𝐋𝐞𝐬𝐬𝐨𝐧 𝟏)-𝐏𝐫𝐞𝐥𝐢𝐦𝐬
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ISO/IEC 27001, ISO/IEC 42001, and GDPR: Best Practices for Implementation and...PECB
Denis is a dynamic and results-driven Chief Information Officer (CIO) with a distinguished career spanning information systems analysis and technical project management. With a proven track record of spearheading the design and delivery of cutting-edge Information Management solutions, he has consistently elevated business operations, streamlined reporting functions, and maximized process efficiency.
Certified as an ISO/IEC 27001: Information Security Management Systems (ISMS) Lead Implementer, Data Protection Officer, and Cyber Risks Analyst, Denis brings a heightened focus on data security, privacy, and cyber resilience to every endeavor.
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Date: May 29, 2024
Tags: Information Security, ISO/IEC 27001, ISO/IEC 42001, Artificial Intelligence, GDPR
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Main Java[All of the Base Concepts}.docxadhitya5119
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Healing is the body’s response to injury in an attempt to restore normal structure and functions.
Healing can occur in two ways: Regeneration and Repair
There are 4 phases of wound healing: hemostasis, inflammation, proliferation, and remodeling. This document also describes the mechanism of wound healing. Factors that affect healing include infection, uncontrolled diabetes, poor nutrition, age, anemia, the presence of foreign bodies, etc.
Complications of wound healing like infection, hyperpigmentation of scar, contractures, and keloid formation.
Pengantar Penggunaan Flutter - Dart programming language1.pptx
Design and Implementation of Low Ripple Low Power Digital Phase-Locked Loop
1. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 304
Design and Implementation of Low Ripple Low Power Digital
Phase-Locked Loop
M. Saber mohsaber@kairo.csce.kyushu-u.ac.jp
Department of Informatics
Kyushu University 744 Motooka,
Nishi-ku, Fukuoka-shi, 89-0395, Japan
Y. Jitsumatsu jitsumatsu@inf.kyushu-u.ac.jp
Department of Informatics
Kyushu University 744 Motooka,
Nishi-ku, Fukuoka-shi, 89-0395, Japan
M. T. A. Khan tahir@apu.ac.jp
Ritsumeikan Asia Pacific University, College of Asia pacific Studies
1-1 Jumonjibaru, Beppu, Oita, 874-8577, Japan
Abstract
We propose a phase-locked loop (PLL) architecture which reduces double
frequency ripple without increasing the order of loop filter. Proposed architecture
uses quadrature numerically–controlled oscillator (NCO) to provide two output
signals with phase difference of π / 2 . One of them is subtracted from the input
signal before multiplying with the other output of NCO. The system also provides
stability in case the input signal has noise in amplitude or phase. The proposed
structure is implemented using field programmable gate array (FPGA) which
dissipates 15.44 mW and works at clock frequency of 155.8 MHz.
Keywords: Digital Phase-Locked Loop (DPLL), Field Programmable Gate Array (FPGA), Numerically-
controlled Oscillator (NCO), Read Only Memory (ROM), Look-Up Table (LUT).
1. INTRODUCTION
A PLL is a closed-loop feedback system that sets fixed phase relationship between its output
phase and the phase of a reference input. It tracks the phase changes that are within its
bandwidth. Tasks performed by PLL include carrier recovery, clock recovery, tracking filters,
frequency and phase demodulation, phase modulation, frequency synthesis and clock
synchronization. PLLs are also used in radio, television, every type of communications (wireless,
telecom, datacom), all types of storage devices and noise cancellers [1].
A PLL block diagram is shown in Fig 1. It has three main components which are, phase detector
(PD), a low pass filter (LPF) called as the loop filter and a voltage controlled oscillator (VCO). PLL
operates as a negative feedback loop. VCO generates a signal at center frequency, multiplied by
the input signal in PD and the resultant is passed through LPF to eliminate double frequency
ripple. The filter output is fed back to VCO to adjust its generated frequency and phase. This
process continues until no phase or frequency difference exists and the PLL is said to be
“frequency locked”.
2. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 305
FIGURE 1: Phase Locked Loop
PLL behaves as a narrow band tracking filter and its LPF output has a characteristics of
frequency discriminator. The linearity of VCO affects the overall linearity of PLL in case of analog
implementation [2]. Hence, digital PLLs can solve some of the limitations of analog ones. In
addition, the digital tangent method can compute frequency from the ratio of in-phase and
quadrature (I-Q) signals [3,4,5]. Some other problems associated with the analog loops like
sensitivity to d.c. drifts and the need for initial calibration and periodic adjustments can also be
alleviated using DPLL. Nonuniform sampling DPLLs are the most ones because they are simple
to implement and easy to model [6]. Digital tanlock loop (DTL), proposed in [7], has introduced
several advantages over other nonuniform sampling digital phase locked loops. It allows a wider
locking range of the first-order loop and a reduced sensitivity of the locking conditions to the
variation of input signal power [7].
Noise is an extremely important issue in the field of PLL applications and is of two main types.
Most common is the additive white Gaussian noise (AWGN) which is added to the signal at every
component of communication system. Fig. 2 shows an input sinusoidal signal with AWGN at 35
dB signal to noise ratio (SNR). Second type of noise in PLL is called as the double frequency
ripple, which is generated by phase detector. Since phase detector multiplies two sinusoidal
signals, its output will be two terms, one is at low frequency and the other is at higher frequency
( ω2 ). The situation will be critical when the two noise sources are involved with the feedback
loop. This will affect the operation of PLL especially when it is used as a synthesizer, as the
generated frequencies will have much noise or jitter.
0 5 10 15
-1.5
-1
-0.5
0
0.5
1
1.5
Time (s)
Amplitude
FIGURE 2: Input signal with AWGN at 35dB SNR
LPF in the loop is used to eliminate double frequency terms resulting from multiplying the input
signal with generated signal from VCO. In practical circuits, there is no ideal LPF and a residual
noise will be present at the output of phase detector. Using higher order loop filters offer better
noise cancellation. However, in this case generally the PLL becomes unstable since its order is
always higher by 1 than that of loop filter. Noise cancellation performance can also be improved
Input signal
ω θis (t) ,,
θ − θfs , ˆ
Generated signal
ω θvcos (t) ˆˆ,,
Loop filterPhase detector
VCO
3. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 306
by lowering cut-off frequency of first order LPF. This will cause lower bandwidth and lower
damping of the PLL and will also have a negative impact on its locking ability.
This paper presents an improved PLL which helps in suppressing noise without increasing the
order of LPF. Computer simulations performed using Matlab show significant performance
improvements over conventional PLL. Furthermore, the system is also modeled in VHDL and
implemented using FPGA. This hardware implementation further confirms the results obtained
through computer simulations.
2. Mathematical Analysis of PLL
In this section we’ll perform mathematical analysis of a conventional PLL shown in Fig. 1. We
assume an input sinusoidal signal
ω + θ = ψ=i i its (t) A sin( ) A s( ) int (t) , (1)
where ω is the angular frequency and (t)θ is the unknown phase of input signal. The signal
generated by VCO is
ω += =θ ψivco o
ˆˆ ˆt (t)s (t) A cos( ) A cos (t) , (2)
where ˆω is the estimation of angular frequency of VCO and ˆ (t)θ is the estimated phase of VCO.
There are several designs and construction methods for phase detector. For the present
discussion, we assume that PD is a multiplier. Input signal is multiplied by the VCO output, then
×
ω− ω + θ − θ + ω+ ω + θ + θ
=
=
d m i vco
i o m
s
ˆ ˆˆ ˆ)t (t) (t)) sin
s (t)
(( )t
k s (t
(t
) (t)
A A k
[si ) (n((
2
t))]
= ψ − ψ ψ+ + ψd ˆ ˆk (t) (t) (t)[sin( ) sin( (t))], (3)
where mk is the gain of phase detector with dimension [1/V] , = i o m
d
A A k
k .
2
In the simplest case we assume that low-pass filter removes the upper sideband with frequency
ω+ ωˆ but passes the lower sideband ω− ωˆ . VCO’s tuning voltage will be
f d d eˆ(t) (ts (t) k sin( ) sin (k t) ),ψ − ψ = ψ= (4)
where ψe(t) is the phase difference between input and output VCO signals
e ˆ(t) (tt ).( )ψ ψ − ψ= (5)
This difference will be used to control the frequency and phase generated by VCO. If the error
signal is zero, VCO produces just its free running frequency ( ωc , center frequency). If the error
signal is other than zero, then VCO responds by changing its operating frequency.
+ω = ωc o fˆ (t) k s (t), (6)
where the constant ok is the gain of VCO in units ( π2 Hz / V ). After integration of the above
equation and substituting into (5), the phase difference is
e c
t
o f(t) k s(t) .( ) d
−∞
ψ ψ − ω τ τ= − ∫ (7)
4. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 307
This can be rearranged as follows:
−∞
ψ ω − ω ψ τ τ= − ∫e c o d e
t
(t) t k k sin ( ) .dt (8)
Differentiating (8) w.r.t. ‘t’ gives
e e
d
(t) (t)
d
n
t
K siψ ∆ω− ψ= (9)
where ∆ω = ω− ωc and = o dK k k is the gain of PLL having units [ π2 Hz ].
The PLL continues to vary the phase of VCO ωˆ until locked, that is, frequency and phase of the
input signal are the same as those generated by VCO. After getting locked, PLL follows the
changes in frequency and phase of input signal [9,10].
It can be concluded from the above analysis that the phase lock arrangement is described by the
nonlinear equation (9). Solution of this equation is not known for arbitrary values ∆ω, andk .
Without an aperiodic solution, the feedback system (PLL) cannot achieve phase stability, i.e.,
output frequency of VCO ωˆ will never be equal to input frequency( )ω . Simplifications are needed
to solve the equation. One solution is the linear solution, in which we assume that, for small
values of ψe (t)
≈ψ ψe esin (t) (t) (10)
Substituting in (9)
e e
d
(t K) (t)
dt
ψ ∆ω− ψ= (11)
If θ =(
d
t
t)
d
0 , solution of this differential equation is
Kt
e e0(t) e ( )
K K
− ∆ω ∆ω
ψ ψ= − + (12)
where ψ ψ θ= −= θe0 e
ˆ(0)(0) (0) .
For steady state, that is, for → ∞t , the left hand side of (11) is equal to zero, with the result that
e .
K
∞ψ =
∆ω
(13)
In the above analysis we assumed that LPF completely suppressed the high frequency term in
(3). This operation is not easy for a first order low pass filter and requires a higher order.
However, the LPF is part of a feedback control system and instability of the system will increase
in this case. Our proposed improvement of PLL aims to reduce noise inside the loop without
using higher order LPF.
5. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 308
3. Proposed PLL
We propose modification in conventional PLL to suppress noise without increasing the order of
LPF (first order LPF). Fig. 3 shows the block diagram of our suggested architecture. It uses a
quadrature numerically controlled oscillator (NCO) to generate two signals ˆˆ tsin t)( )(ω + θ
and ˆˆ tcos t)( )(ω + θ . The phase detector subtracts ˆˆ tsin t)( )(ω + θ from the input signal and
multiplies the resultant by ˆˆ tco )t)s( (ω + θ before passing on its output to LPF.
FIGURE 3: Block diagram of proposed PLL
This operation eliminates almost the entire high frequency term and if there is some residual, the
first order LPF can remove it easily. Following equations describe the operation of proposed PLL
in time domain.
Output signal from the phase detector is
d d ˆ ˆ(t) sin (ts (t) k [sin ]c) t)os (= ψ − ψ ψ
dk [sin( ) sˆ ˆ ˆ(t) (t) (t) (t) (t)]in( ) sin(2ψ − ψ ψ + ψ−ψ= + (14)
A comparison of (3) and (14) clearly establishes that in the proposed structure, the high
frequency term ψ + ψˆ(t)sin( (t)) is subtracted by the term ψˆsin(2 (t)) before passing on the
resultant to LPF. Thus even a first order LPF can suppress the noise easily. In conventional PLL,
LPF is responsible for removing the term ψ + ψˆ(t)sin( (t)). First order filter cannot suppress all
this term and its output will have large residual high frequency component.
Proposed modification will not have any negative impact on the PLL’s locking performance. The
term d ek sin (t)ψ is passed to VCO and the process continues like a conventional PLL.
4. Simulation Results
In this section we compare the performances of proposed and conventional PLL’s using computer
simulations. Two types of simulations are done. In the first group of simulations, we use a first
order LPF in both architectures. Both architectures receive a signal with frequency difference
(results shown in Fig. 4), phase difference, or both frequency and phase are changed (results
shown in Fig. 6). In the second group of simulations, proposed PLL uses a first order LPF, while
conventional PLL uses a second order LPF and performances of the two are compared.
LPF
NCO
Phase detector
ω + θ(t)sin( (t))
ω + θˆˆ (t)sin( (t)) ω + θˆˆ (t)cos( (t))
ds (t)
= θf d ds (t) k
6. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 309
4.1 Proposed versus Conventional PLL (Using first order LPF)
The parameters for both PLLs are:
1 5 4
m o s vcok 1 v , k 1500 rad / v.s, f 1.0 Hz, f =1.0 Hz10 1 .0−
= = = × ×
LPF: first order with cut-off frequency =1000 Hz,
VCO generates = πvco vcos (t) cos( f2 t)
First of all we perform comparison of the two PLL structures in case of input signal having
frequency difference. For ω = π×2 10100 rad/s and θ =(t) 0 in (1), Fig. 4 shows the response of
both PLLs for the input signal. It can be seen that the proposed PLL suppresses much more
noise than the conventional one. In Fig. 4 the response of proposed PLL converges to the mean
value 0.0389 with variance −
× 4
1.3926 10 . While the conventional PLL has the mean value 0.0389
with a high variance of −
× 4
4.4758 10 .
0 0.5 1 1.5 2 2.5 3 3.5
x 10
-3
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
Time(s)
PLLResponse
Conventional PLL
Proposed PLL
FIGURE 4: Response in case of frequency difference
Fig. 5 shows amplitude spectrum of output signals from each phase detector and each LPF for
the two architectures. As can be seen in Fig. 5(a) the proposed architecture attenuates the high
frequency term at ×= 4
f 2 10 Hz to an amplitude of 0.05 V before passing signal to the LPF which
eliminates this term completely as shown in Fig. 5(b). While in conventional PLL the amplitude of
high frequency term is 10 V which is almost equal to the amplitude of low frequency term. After
passing signal through LPF high frequency component residual noise still has amplitude of 0.025
V as shown in Fig. 5(d).
7. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 310
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10
4
0
0.02
0.04
0.06
0.08
0.1
Frequency
(a)
Amplitude
0 1 2 3 4 5
x 10
4
0
0.005
0.01
0.015
0.02
Frequency
(b)
Amplitude
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10
4
0
0.5
1
1.5
2
2.5
Frequency
(c)
Amplitude
0 1 2 3 4 5
x 10
4
0
0.005
0.01
0.015
0.02
0.025
Frequency
(d)
Amplitude
FIGURE 5: Amplitude spectrum of the output signal of (a) PD in proposed PLL, (b) LPF in proposed
PLL, (c) PD in conventional PLL, (d) LPF in conventional PLL.
We also performed comparison in case of input signal having both frequency and phase
difference. Fig. 6 illustrates the response of both architectures at ω = π×2 10100 rad/s and
θ = π(t) / 2 in (1).
0 0.5 1 1.5 2 2.5 3 3.5
x 10
-3
-0.1
0
0.1
0.2
0.3
0.4
Time (s)
PLLResponse
Conventional PLL
Proposed PLL
FIGURE 6: Response in case of phase difference
8. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 311
We also performed comparison of the two structures in the presence of AWGN. When the input
signal is combined with AWGN at 35 dB SNR, the response of both PLLs is plotted in Fig. 7.
0 0.5 1 1.5 2 2.5 3 3.5
x 10
-3
-0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
Time (s)
PLLResponse
Conventional PLL
Proposed PLL
FIGURE 7: Response in the presence of AWGN at 35 dB SNR
4.2 Proposed PLL versus Higher Order Conventional PLL
In this group of simulations, we have used a first order LPF in the proposed PLL while second
order LPF is used in conventional one. Fig. 8 shows both responses when the frequency of input
signal is changed and the phase stays fixed, i.e, ω = π×2 10100 rad/s and (t) 0θ = .
Proposed PLL locked to the input signal while conventional PLL did not achieve locking although
noise level is reduced. As mentioned before, increasing the order of LPF in the loop increases
instability of the system. Therefore, the parameters of conventional PLL must be adjusted
carefully to control the location of poles and zeros to achieve stability of higher order PLLs.
0 1 2 3 4 5
x 10
-3
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
Time (s)
PLLResponse
conventional PLL
Proposed PLL
FIGURE 8: Response when conventional PLL has higher order LPF than proposed one
The above simulations clarify and explain operation of the proposed architecture through a
comparison with conventional one in different cases such as a frequency difference or phase
difference in the input signal as shown in both Fig. 4 and Fig. 6. Furthermore simulations show us
the signals’ amplitudes in different stages inside both architectures as in Fig. 5. The situation in
case the received signal has AWGN is clarified in Fig. 7. In case the order of LPF in conventional
PLL is increased, Fig. 8 shows that the noise is suppressed while the PLL loses stability and
9. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 312
unlocked the input signal while proposed one is stable. All previous simulations clearly
demonstrate that the proposed PLL has low ripple and is more stable than the conventional one.
5. Hardware Implementation of Proposed PLL
Since Digital Phase Locked Loops (DPLL) find applications in most of the state of the art
equipment, we discuss hardware implementation of the digital version of our proposed
architecture in this section. Hardware modeling is performed using VHDL language [11,12]. In
Fig. 3, the input signal is 8 bits-length, comes from Analog to digital converter (ADC) and
generates 8 bits as an output of DPLL architecture. The following sub blocks describe the
operation of each part:
5.1 Phase detector (PD)
The Phase Detector detects the phase error between input signal and generated signal from
NCO. This operation is done using a multiplier and a register as shown in Fig. 9. In the VHDL
model, Booth’s multiplication algorithm [13] is used to achieve smaller area and higher speed of
multiplication.
FIGURE 9: Phase Detector module
5.2 Loop Filter
The loop filter is a digital filter responsible for eliminating high frequency term from the output of
phase detector unit. The filter is a first order IIR low pass filter. In designing filter it is important to
choose the pole, which controls cut-off frequency, to be inside the unit circle to provide stability to
the filter. It cannot be equal to 1 because the filter in this case becomes an integrator [14,15]. The
transfer function of the filter in z-domain for an input d ss (nT ) and output f ss (nT ) is
1
f
1
d
s (z) kz
H(z)
s (z) 1 pz
−
−
= =
−
(15)
where k, and p are coefficients of the filter. The structure of digital filter is illustrated in Fig. 10.
FIGURE 10: First order digital low pass filter
f ss (nT )
Clock
d sv (nT )-
DQ
+ω θs
ˆˆ nTsin( )
+ω θs
ˆˆnTcos( )
ω θ+sns Tin( )
Delay
Delay
d ss (nT )
p
k
10. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 313
5.3 Quadrature NCO
NCO is an important component in DPLL because it determines power consumption of the entire
system. The generation of analog sinusoidal waveform in digital domain requires storing the
amplitudes of analog waveform in a read only memory (ROM). The structure of ROM in digital
implementation causes high power consumption and slow operation of the circuit. These
drawbacks of ROM block limit the use of DPLL in portable applications which require low power
consumption [16].
Since it is desirable to have a large number of bits to achieve fine frequency tuning, several
techniques have been invented to limit the ROM size while maintaining sufficient performance.
One method exploits the quarter wave symmetry of the sine function to reduce by four the
number of angles for which a sine amplitude is required. Truncating the phase accumulator
output (eliminating a number of most significant bits (MSB) of the output) is another common
method, although it introduces spurious harmonics in the generated waveform [17].
Various angular methods have been proposed to reduce memory size [18-19]. They consist of
splitting the ROM into a number of smaller units each addressed by a portion of the truncated
phase accumulator output bits. Data retrieved from each small ROM is added to yield a sinusoidal
approximation.
In this paper instead of using ROM in the quadrature NCO, piecewise linear approximation for the
first quarter of the sine waveform is employed. From the first quarter of sine wave a complete
waveform for sine and cosine can be generated due to symmetry of both functions. The first
quarter of sine waveform which lies between (0, )/ 2π is represented by eight linear equations.
Slopes and constants for these linear equations are chosen according to minimum mean square
error (MMSE) criterion between the approximated and ideal sine wave.
i i
i 1
t , i = 0,1...
i
sin(t) a t b , .7
16 61
+
π ≤ < π≈ + (16)
where ia is segment slope and ib is segment constant.
The quadrature NCO block diagram is shown in Fig.11. It consists of 3 blocks, the first one is the
accumulator, which receives input signal f s
s (nT ) corresponding to phase difference between θ
and ˆθ . The accumulator width is 16 bits.
FIGURE 11: Structure of modified NCO
The accumulator works as a circular counter, a complete rotation of accumulator represents one
cycle of output waveform. All bits leaving accumulator are directed to Quarter calculation block.
The first three MSBs are used to choose between slopes and constants for every linear segment.
After calculation of first quarter, the results are directed to waveform block. This block forms
Accumulator
(n bits)
Quarter
Calculation Waveform
Clock
2
nd
MSB
3
rd
MSB
1
st
MSB
ψ s
ˆ(s n( nTi ))
ψ s
ˆ (c s( nTo ))
f ss (nT )
11. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 314
complete sine and cosine waveforms according to the 1st
MSB and 2nd
MSB of accumulator block.
The frequency of generated waveforms ncof is
f c
nco clkn
s
f ( ) ,
2
f
ω
×
+
= (17)
where ncof is the generated frequency, fs are the input binary bits to the NCO, ωc is a constant
value which represents the free running frequency of NCO, n is number of bits or width of
accumulator which is 16 bits and clkf is the clock frequency which is 50 MHz. When input signal
fs is zero, the architecture generates free running frequency.
Spurious free dynamic range (SFDR) is a measure of spectral purity of the waveform generated
by NCO. It represents the ratio between amplitude of the fundamental generated frequency and
the amplitude of the largest spur in the dynamic range of NCO (0 : sf / 2 ) [20,21]. For our
proposed NCO, SFDR is 60 dBc which is sufficient not to introduce ripples to DPLL.
Fig. 12 shows the output spectrum for input word of value 1317 representing fv (n) , at a clock
frequency of 50 MHz, ωc =1317 and accumulator width n = 16. The fundamental frequency is
approximately 2 MHz with -30.057 dB and the spurious appears at 14.46 MHz with -89.925 dB,
so SFDR = 59.868 dBc.
0 5 10 15 20 25
-90
-80
-70
-60
-50
-40
-30
-20
Frequency (MHz)
Power(dB)
FIGURE 12: SFDR in dBc of fundamental frequency 2 MHz
6. FPGA Implementation Results
The proposed DPLL architecture is written in VHDL and simulated using Modelsim program. The
simulation is done at clock frequency 50 MHz, the input is sinusoidal waveform of frequency 1
MHz. Fig. 13 shows the simulation waveforms for proposed PLL. The input signal is multiplied by
the modified NCO signal after subtracting the other sinusoidal output from NCO and the resultant
is subjected to digital filter. The final output shows that digital simulation agrees with the expected
waveform. Fig. 14 shows the response of conventional PLL for the same input signal. It is clear
that the proposed PLL suppresses noise more effectively than the conventional one.
12. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 315
FIGURE 13: Proposed DPLL waveforms for input sinusoidal of 1 MHz
FIGURE 14: Conventional DPLL waveforms for input sinusoidal of 1 MHz
A comparison between conventional DPLL (in which the phase detector is only a multiplier and
NCO uses ROM) and proposed DPLL is done by implementing both architectures on the same
FPGA device (cyclone II, EP2C35F67C). The result is illustrated in TABLE 1. It is clear that the
proposed PLL saves area, reduces power consumption and works at higher frequency than the
conventional one.
Architecture Conventional DPLL Proposed DPLL
Total logic elements 762 655
Logic registers 106 78
Memory bits 2048 0
Maximum clock 115.02 MHz 155.8 MHz
Core dynamic power
consumption(100 MHz)
19.54 mW 15.44 mW
TABLE 1: DPLL implementation comparison
7. CONSLUSION
An improved PLL design was presented. The signal estimated by the VCO was subtracted from
the signal input to the PLL, before passing the resultant to the phase detector. This resulted in
13. M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An international journal, (SPIJ), Volume (4): Issue (6) 316
eliminating the noise present because of the double frequency ripple, without increasing order of
the LPF. Computer simulations performed using Matlab showed significant performance
improvements in the case of changing frequency, phase and both frequency and phase. A digital
version of the improved PLL was also proposed using VHDL and then implemented through
FPGA. High power consumption and low operation speed in conventional DPLL results because
of the NCO in which the generation of sinusoidal waveform depends on ROM. As accuracy of the
generated signal increases, the size of ROM is increased. Proposed structure replaces the
traditional NCO with another one, which depends on piecewise linear approximation to the sine
function thus ROM is not needed in this case. The proposed architecture reduces noise, power
consumption, area consumption and works at higher frequency than the conventional DPLL.
8. Acknowledgement
This work was supported in part by Grand-in-Aid for Young Scientists of the Ministry of Education,
Culture, Sports, Science and Technology (MEXT), no. 20700210 and the Japan Society for the
Promotion of Science (JSPS) grant no. 20560381.
.
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