The document outlines the physical design aspects of ASIC design, covering topics such as implementation styles, design flow, floor planning, power planning, placement, and timing analysis. It details various methodologies for converting gate-level netlists into physical layouts, including the importance of optimization in routing and clock tree synthesis. Additionally, it discusses verification processes and energy calculations to ensure efficient functioning of the ASIC design.

1. Physical Design
ASIC Design

2. IL2200 , ASIC Design Slide 2
Lecture Outline
 Physical Implementation Styles
 ASIC Design Flow
 Floor and Power planning
 Placement
 Clock Tree Synthesis
 Routing
 Timing Analysis
 Verification and Energy Calculation

3. Physical Implementation
Styles
Semi Custom
ASICs/FPGAs
Full Custom
Older Intel
Standard Cells Macro Cells
Cell Based Array Based
Pre Diffused
Gate Arrays
Pre Wired
FPGAs
AMD
Newer Intel
Structured ASICs !
Coarse Grain
Reconfigurable
Architecture

4. cells
ro u tin g a rea
r
o
u
ti
n
g
a
r
e
a
feed th ro u g h
cell
w a s ted
sp a ce
Standard Cell Layout
Cells are of same height but different width. The layout is organised as rows of
cells seperated by channels used for routing. The routing channels are not fixed in
their height. This is dependent on the routing density in it. This is one important
reason why standard cell layout is more flexible compared to array based designs
where the routing channels have a fixed capacity. Cells in the same row or adjacent
rows can be connected by running wires through the adjacent channel. To connect
cells in non-adjacent rows, vertical routing space on the sides is used or special
feed through cells are instantiated as shown in
It is possible that in some rows, some space may be left unused, as either no cell
would fit there or routing considerations dictate placing cells elsewhere.
Cells may have the same height but can differ in complexity from simple gates to
cells as complex as full adders. Complex cells use the width to spread out the
necessary logic. As the logic can be spread out only horizontally, the
interconnection delay is typically larger compared to cells design without the fixed
height constraint.
As the same std. cell is supposed to work correctly in a variety of circuit
conditions, the transistors are typically larger than in a custom layout. Some
libraries may provide two varieties: low and high power. Technology mapping tools
will select one based on estimation.
Rat’s nest are a good way to judge wire congestion and long nets.

5. IL2200 , ASIC Design Slide 5
Standard Cells
P-Type
Transistor
Diff Spacing
N-Type
Transistor
VSS Bus
VDD Bus
Standard
Cell
Height
4-input AND
2-input AND

6. IL2200 , ASIC Design Slide 6
Design Flow
Design Specification
Synthesis
Functional Verification
RTL Development
Thing you
already
learned in
IL2204
Gate Level Net list
VHDL Code
Logical Design
No
Yes
Simulation
learned in
IL2200 till now

7. Physical Design
 Converting gate-level netlist to physical
layout
IL2200 , ASIC Design Slide 7

8. IL2200 , ASIC Design Slide 8
Physical Design Flow
Synthesis
Post Route Verification
Placement
Floor and Power Planning
Thing to
Learn in this
lecture
Gate Level Net list
Physical Design
Sign Off
Floor Planning
Verification
Routing
STA
CTS
Routing

9. Before Physical Design…..
 You must have synthesized gate level netlist.
 Please verify that this netlist is working
properly by doing gate level simulation in
NCSim/ModelSim
 Also Generate Standard delay constraint file
.sdc.
IL2200 , ASIC Design Slide 9

10. SoC Encounter
10
 We use Cadence SoC Encounter 8.1 for
Layout.

11. IL2200 , ASIC Design Slide 11
Design Import
 Before starting the Physical Design We first have to
import the design and associated libraries
 .LEF File
 Contains layer, via and macro definition
 .LIB File (.TLF)
 This file has timing information e.g delay and capacitance
 Verilog Netlist
 Netlist file generated by Synthesis Tool
 .SDC File (Synopsys Design Constraints Format)
 Constraint file generated by synthesis tool
 .DEF File
 Design exchange format to output the design so it is
readable by other modules.

12. IL2200 , ASIC Design Slide 12
Design Import
Toplevel of the design
Veriglog Netlist File
.Lib .TLF Files
.LEF File
.SDC File
 Design Import Design

13. Design Import
 Advance  Power
IL2200 , ASIC Design Slide 13

14. IL2200 , ASIC Design Slide 14
Floor Planning
 Results in Efficient Design Implementation
 Two styles of Implementation
 Flat
 Small to Medium ASIC
 Better Area Usage Since no reserve space around
each sub-design for power/ground
 Hierarchical
 For very large design
 When sub-systems are design individually
 Possible only if a design hierarchy exist.

15. IL2200 , ASIC Design Slide 15
#/* Translate to target independent structure (GTECH) */
analyze -format vhdl -lib WORK {"./SOURCE/mics.vhd"}
analyze -format vhdl -lib WORK {"./SOURCE/SRAM.vhd"}
……………………………………………………………………..
elaborate FIR_Toplevel -lib WORK -update -param "width = 4" -param "filter_taps=5"
ungroup –all
Link
uniquify
set_wire_load_mode segmented
set_wire_load_model -name "TSMC8K_Lowk_Conservative"
#T=-40, V=1.1
set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA
set_operating_conditions LTCOM
#/* Specify clock constraint */
create_clock clk -period 4
set_false_path -from rst_n
compile -map_effort medium -boundary_optimization
write -hierarchy -format verilog -output /home/ali/ASICLABS/LAB2/LAB2_FIRToplevel.v
write_sdc /home/ali/ASICLABS/LAB2/MAPPED/constraints.sdc

16. Floor Planning
IL2200 , ASIC Design Slide 16
 Automatic Floor Planning
 Seed Selection:
 USB controllers
 PCI controllers
 Hierarchical modules
 Automatic Floorplan Synthesis
analyzes the data flow between
seeds (design blocks) based on
their connectivity and their location

17. Floor Planning
 Relative Floor Planning
 Capture and define the placement relationship of
floorplan objects independently from the actual
coordinates in a floorplan
 flexible way to place objects, such as modules, blocks,
groups, blockages, pin guides, pre-routed wires, and
power domains
 I/O pins can be used as reference objects but
they cannot be relative objects
IL2200 , ASIC Design Slide 17

18. Floor Planning
IL2200 , ASIC Design Slide 18
Orientation Keys for Relative Floor Planning

19. IL2200 , ASIC Design Slide 19
Pre-route example:
S1 and S2 are relative to
the object I2 and the
Core_Boundary
Floor Planning

20. Floor Planning
IL2200 , ASIC Design Slide 20
Manually Floor Planed DRRA Fabric

21. IL2200 , ASIC Design Slide 21
Floor Planning
 Aspect Ratio
 Height/Width
 Core Utilization
 Area of Stand. Cell/Area of Core
 Core to IO Boundary
 Distance from IO Boundary
 Core to Die Boundary
 Distance from Die Boundary

22. IL2200 , ASIC Design Slide 22
Floor Planning
0um every row 10um every row
10um every second row
 Adjustable Routing Channel Width

23. IL2200 , ASIC Design Slide 23
Floor Planning
 Cutting with Rectilinear Tool
Clusters
Rectilinear Tool
Move Tool Blockage tools

24. IL2200 , ASIC Design Slide 24
Partitioning
 Part of Floor Planning
 Standard Cells are in Floating States before
placement.
 Have not been assigned a fixed location in Core
 Time to define clusters and regions
 To keep time critical component close
 Soft Regions
 Boundary can change during standard cell
placement
 Hard Regions
 Prevent Standard cell crossing boundaries

25. IL2200 , ASIC Design Slide 25
Partitioning
 Exclusive Regions
 Allow standard cells assigned to the region to be
placed within the region
 Non Exclusive Regions
 Allow standard cells that do not belong to the
region to be placed within the region

26. IL2200 , ASIC Design Slide 26
Power Planning
 Deal with Power Distribution Network
 Three levels of Power Distribution
 Rings
 Carries VDD and VSS around the chip
 Stripes
 Carries VDD and VSS from Rings across the chip
 Rails
 Connect VDD and VSS to the standard cell VDD and
VSS

27. IL2200 , ASIC Design Slide 27
Power Planning
VDD
VSS
Rings Stripes (vertical or horizontal)
Rails
Special Route
Power Distribution Network

28. Power Planning
28
 Add Rings, Stripes & do a special route

29. IL2200 , ASIC Design Slide 29
Power Distribution network
Example
Power Distribution Network in DRRA

30. IL2200 , ASIC Design Slide 30
Placement
 Global Placement algorithm are partitioned
based
 Two Associated Cost functions
 Reduce Total wiring or routing length
 Distribute standard cell instances homogeneously
in ASIC Core such that optimal equilibrium among
vertical and horizontal routing is achieved

31. IL2200 , ASIC Design Slide 31
Detailed Placement
 After global placement
 To Refine placement based on congestion, timing and
power
 Congestion Driven Placement
 To distance standard cell instances from each other such
that more routing tracks are created between them
 Timing Driven Placement
 To optimize large sets of path delays
 Net Based
 Try to control the delay on signal path by imposing an
upper bound delay or weight to net

32. IL2200 , ASIC Design Slide 34
Clock Tree Synthesis
 Automatic insertion of buffers/inverters along
the clock path to balance the clock delay to
all the clock inputs.
Why balancing clock delay?
Clock Skew?

33. Clock Distribution: How?
IL2200 , ASIC Design Slide 35
Source: MIT 6.375 Complex Digital System

34. IL2200 , ASIC Design Slide 36
Clock Tree Synthesis
R1
Vin
C1
R2
C2
Ri-1
Ci-1
Ri
Ci
RN
CN
)
...
(
... 2
1
2
1
2
1
1
1
1
N
N
DN
N
j
N
i
DN
R
R
R
C
R
R
C
R
C
T
Rj
Ci
T
 Delay of a wire
 Elmore Delay

35. IL2200 , ASIC Design Slide 37
Clock Tree Synthesis
 Optimizing Wire Delay
 Divide the wire into N identical segments with length L/N
 Resistance= rL/N. Capacitance= cL/N
2
2
2
1
2
1
...
2
2
2
2
2
rcL
RC
T
N
N
RC
T
N
N
L
rc
T
Nrc
rc
rc
N
L
T
DN
DN
DN
DN
N

36. IL2200 , ASIC Design Slide 38
Clock Tree Synthesis
 Equation shows that the wire delay depends on RC
effect.
 One method to reduce RC is to insert intermediate
buffers.
 Most Popular technique to reduce propagation delay
 Making a line m times shorter reduces its propagation
delay quadratically
R/M R/M R/M R/M
Vin Vout
C/M C/M C/M C/M

37. IL2200 , ASIC Design Slide 39
Clock Tree Synthesis
 For optimal propagation delay, buffer size increases
in their drive strength d by a factor a for each level
of clock tree path
a0d a1d a2d aNd
Clock Source
 If clock buffers are not selected correctly they may
cause the clock pulse width to degrade as the clock
propagates through them
d d d d

38. IL2200 , ASIC Design Slide 40
Skew and Jitter
D
Q
D
Q
Combinational
Logic
clk
t2
t1
Period A != Period B
Clock Jitter
Clock Skew = t2 - t1
•Positive skew occurs when
the transmitting register
receives the clock earlier than
the receiving register.
•Negative skew is the
opposite: the receiving
register gets the clock earlier
than the sending register

39. Why minimizing Skew and
Jitter is hard?
IL2200 , ASIC Design Slide 41
Source: MIT 6.375 Complex Digital System

40. Clock Distribution
IL2200 , ASIC Design Slide 42
Source: MIT 6.375 Complex Digital System

41. Clock Distribution
IL2200 , ASIC Design Slide 43
Source: MIT 6.375 Complex Digital System

42. IL2200 , ASIC Design Slide 44
Clock Tree Synthesis
D Q D Q
Combinational
Logic
clk
D Q D Q
Combinational
Logic
clk
Without On-Chip Variation Awareness
With On-Chip Variation Awareness

43. Clock Tree Synthesis in SoC
Encounter
IL2200 , ASIC Design Slide 45
Fish Bone Routing Style

44. Clock Tree Synthesis in SoC
Encounter
IL2200 , ASIC Design Slide 46
 The color Difference tells us about clock
skew

45. IL2200 , ASIC Design Slide 47
Electromigration
 Electromigration (EM) is the movement or
molecular transfer of metal from one area to
another area that is caused by an excessive
electrical current in the direction of electron
flow.
 EM currents exceeding recommended
guidelines can result in premature ASIC
device failure

46. IL2200 , ASIC Design Slide 48
Routing
 Global Routing
 Decomposes ASIC design interconnection into net
segments
 Assign these segments to regions
 Detail Routing
 Follows global routing
 Performs actually physical interconnection of ASIC design
 Places actual wire segments in the region defined by the
global router to complete the connections between the
ports

47. IL2200 , ASIC Design Slide 49
Power Analysis
 Power analysis
 Reduces risk of IR voltage drops in power nets
 Ground bounce on the ground nets
 Reduces Electromigration effects due to high current
 Resistance of power and ground net extracted
 Average current of each transistor connected to
power net is calculated
 Average currents are distributed throughout the
power net
 Calculate node voltages and branch currents
 Design goal violations shown

48. IL2200 , ASIC Design Slide 50
RC Extraction
 RC extraction is the calculation of all the
routed net capacitances and resistances
 Used for
 Delay calculation
 Static Timing Analysis
 Circuit Simulation
 Signal Integrity Analysis

49. IL2200 , ASIC Design Slide 51
Verification
 The complete placed and routed design is verified
before fabrication
 Functional Verification
 Verification is performed against behavioral RTL pre-layout
and post-layout structural description (netlist) for the design
validation.
 Rule Based
 Assertion based verification
 Assertions macros are expressions that, if false, indicate
and error
 Instantiated in RTL Code

50. Energy Calculation
 Save your design as a Verilog Netlist
 Simulate the Design in NCSim/ModelSim
 Create a VCD File
 Restore the Design in encounter
 Read the VCD Activity file
 Report Power to get the average power
 Energy= Pave * Tperiod * No of Cycles
IL2200 , ASIC Design Slide 52

51. VCD File Script
run -timepoint 0 ns -absolute
database -open /media/disk-1/mdpu/ADD2/MAC_0.vcd -
vcd -default -timescale us
probe -create :mTile -vcd -all -depth all
run -timepoint 100 us -absolute
database -close /media/disk-1/mdpu/ADD2/MAC_0.vcd
IL2200 , ASIC Design Slide 53

52. Power Calculation in
Encounter
restoreDesign
/home/ali/PhysicalDesign/ICAD2/mdpu/Tile_final.enc.dat Tile
extractRC -outfile file.cap
read_activity_file -format VCD -vcd_scope Tile_tb/mTile
/media/disk-1/mdpu/ADD2/MAC_0.vcd
reportPower -noRailAnalysis -outfile /media/disk-
1/mdpu/ADD2/reports/powenc_0.rep
exit
IL2200 , ASIC Design Slide 54