The document discusses power consumption in microprocessors and techniques for power reduction. It notes that dynamic power, which scales with the square of the supply voltage and operating frequency, makes up the majority of total power consumption. Clock circuitry alone can account for 15-45% of total power. Clock gating and data gating are introduced as approaches to reduce unnecessary switching activity and clock distribution by powering down unused modules. An example of applying clock gating at the architectural level is given to turn off parts of a processor's decode, execute, and load/store units to achieve considerable power reduction of up to 25%.

2. Power Consumption Primitives Characteristics of Power Consumption in Microprocessors Clock Gating and Power Reduction Similar Approaches Power Reduction Example

3. P (total) = P (static) + P (dynamic) Static Power Currently Negligible But Considerable in Future Dynamic Power P (dynamic) = C L V dd 2 . A .F Major Part of Total Power (e.g. 95%)

4. Clock Circuitry Power Consumption 15 to 45% of Total P (clock circuitry) ~ Frequency Activity of Functional Units A (units) < 50% in Execution Time

5. Clock tree consume more than 50 % of dynamic power. The components of this power are: Power consumed by combinatorial logic whose values are changing on each clock edge 2) Power consumed by flip-flops and 3) The power consumed by the clock buffer tree in the design. Clock Gating and Power Reduction

6. There are two types of clock gating styles available. They are: Latch-based clock gating 2) Latch-free clock gating.

7. Latch free clock gating

8. Latch based clock gating

9. Main Idea Clock Circuitry Partitioning Shutting down Unused Partitions Implementation Creating Local Clocks Buffers or Flip-Flops with enable signal Net Effects Reduction of Unnecessary Switching Switched Capacitance Reduction of Clock Circuitry Power Consumption Reduction

10. How to determine unused modules? Dynamically in Decode Stage Statically with Compiler Assistance Disadvantages Additional Circuitry More Complicated Timing Analysis, Design, Test and Verification Possible High L x di/dt Noise

11. Data Gating Effective in Wide Modules Like ALUs Complicated Design Possible Increase of Critical Path Delay Powering Down Unused Modules Possible Long Wake-up Times Need of Compiler and/or OS Support Using Asynchronous Systems Unnecessary Activity Elimination Harder Design

12. Components - flip-flops, latches, ALU, adder, and shifter Functions - decode, execute, and load store unit Power Reduction Example

13. Clock Gating as an Architectural Technique Turning Unused Parts of Circuit Off High P(dynamic)/P (total) Ratio Decrease of Activity to Reduce Power Considerable Power Reduction (up to 25%) Highly Used Technique Summary