The document discusses floor planning and power planning in chip design, emphasizing their critical roles in achieving optimal design implementation. It outlines key concepts of floor planning, including definitions of macros and core elements, as well as steps in the process such as macro placement and routing. Additionally, it covers power planning principles, objectives, distribution architectures, and methods to manage power dissipation and noise in the design.

1. FLOOR PLANNING
&
POWER PLANNING

2. CONTENTS
❑Floor planning
❑Power planning
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3. FLOORPLAN
❑ WHAT IS FLOORPLAN?
• Find approximate locations of a set of modules that need to be placed on a
layout surface.
• Floorplan is one the critical & important steps in Physical design.
• Quality of the Chip / Design implementation depends on how good is the
Floorplan.
• A good floorplan can make implementation process (place, cts, route) easy.
• On the other side a bad floorplan can create all kind of issues in the design
(congestion, timing, noise, routing issues).
❑ OBJECTIVE:
• Minimize area
• To reduce wire length
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4. FEW DEFINITIONS IN FLOOR PLAN
1. Macro:-
• These are special memory elements used to store the data
efficiently these memory cells are called macros.
• All memories are macros but all macros are not memories.
2. Hard macro:-
• The circuit is fixed and we don't know which type of gates using
inside.
• We can only access its pin only.
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5. FEW DEFINITIONS IN FLOOR PLAN
3. Soft macro:-
• The circuit is not fixed and we know which
type of gates are used inside.
4. Core:-
• It is defined as the inner block which
contains the standard cells and macro.
5. Die:-
• It is the block around the core which
contains i/o ports.
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6. FEW DEFINITIONS IN FLOOR PLAN
6. Halo:-
• It is the region around the boundary of fixed macros in design in
which no other macros or standard cells can be placed.
• If macros moves, halo will also move.
7. Blockage:-
• Blockages are specific locations where placing of cells are prevented
or blocked.
• If we move the block, blockage will not move.
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7. FLOORPLAN CONTROL PARAMETER
❑ Aspect Ratio:
• Aspect ratio will decide the size and shape of the chip.
• AR = Height of the core
Weight of the core
❑ Core Utilization:
• Utilization define the area occupied by the standard cells,macros and
other cells.
• Core Utilization = (Standard Cell Area + Macro Area)
Total Core Area
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8. SLICING AND NON-SLICING FLOORPLAN
❑ One that can be obtained by
repetitively subdividing
rectangles horizontally or
vertically.
❑One that may not be obtained
by repetitively subdividing
alone.
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9. FLOORPLAN STEPS
1. Size & shape of the block
2. Voltage area creation (Power domains)
3. IO placement
4. Creating standard cell rows
5. Macro-placement
6. Adding routing & placement blockages (as required)
7. Adding physical cells (Well Taps, End Caps,etc)
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10. FLOORPLAN STEPS
1. Size & shape of the block
❑ In most of the case, block size & shape is decided in floorplan.
❑ Rectangle/Square shape is best in terms of floorplan & further
design closure.
❑ But in many case, floorplan can be of rectilinear shape with many
notches.
2. Voltage area creation (Power domains)
❑ In multi-voltage & multi power domain designs, voltage areas are
required to guide the tool to understand different domains.
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11. FLOORPLAN STEPS
3. IO placement
❑ I/O pads are placed at the boundaries.
❑ In block level these i/o pins are placed at input and output side of the block
to interact with other blocks and transfer the signals.
❑ After that logical cell placement blockage is created in die area to prevent
the logical cell placement.The die area is only for the i/o pins.
4. Creating standard cell rows
❑ The standard cells in the design are placed in rows.
❑ All the rows have equal height and spacing between them. The width of the
rows can vary.
❑ The standard cells in the rows get the power and ground connection from
VDD and VSS rails which are placed on either side of the cell rows.
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12. FLOORPLAN STEPS
5. Macro-placement
❑ Macros are placed at boundaries
❑ Understanding of pins & orientation requirements of macros
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13. FLOORPLAN STEPS
❑ Spacing between macros
❑ All the pins of the Macros should point towards the core logic
❑ Channels b/w macros should be big enough to accommodate all
routing requires & should get a minimum of one pair VDD & VSS
power grids in the channel
❑ Avoid crisscross connections of macros
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14. FLOORPLAN STEPS
6. Adding routing & placement blockages (as required)
❑ Placement blockage is applied in the floor plan stage to prevent standard
cell placement.
❑ If we don't apply the placement blockage there is a chance to overlap the
standard cells on macros.
❑ We applied this at macros area so there is no chance to overlap the
standard cells on macros.
• Blockages are of following types:
1. Soft Blockage
2. Hard Blockage
3. Partial Blockage
4. Routing Blockage 14

15. INPUT FILES OF FLOORPLAN
1.Netlist(.v)
2.Technology file(techlef)
3.Timing Library files(.lib)
4.Physical library (.lef)
5.Synopsys design constraints(.sdc)
6.Tlu+
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16. OUTPUTS OF FLOORPLAN
1.Die/Block area
2.I/O pad placed
3.Macro placed
4.Power grid design
5.Standard cell placement areas
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17. POWER PLANNING
❑Power planning is done to provide uniform supply voltages to all
cells in the design.
❑Primary objective is to ensure all on chip components have adequate
power and ground connection.
❑Three levels of Power distribution:
1. Rings: carries VDD and VSS around the chip
2. Stripes: carries VDD and VSS from the rings across the chip
3. Rails: connect VDD and VSS to the standard cell’s VDD & VSS.
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18. Power planning terminology
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19. Power Planning Management
❑There are two types of Power Plan Management:
1. Core cell Power Management:
• In this power rings are formed around the core
• If any macro/IP is power critical then create separate power ring for
particular macro/IP.
• Number of power stripes are created based on the power requirement.
2. IO Power Management : In this power rings are formed for I/O cells
and trunks are created between core and power rings and power
pads.
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20. Inputs of Power Plan
❑Netlist (.v)
❑SDC
❑Physical and logical libraries (.lef & .lib)
❑TLU+
❑UPF (Unified Power Format)
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21. UPF
❑UPF is an industry wide power format specification to implement low
power techniques in a design flow.
❑UPF is designed to reflect the power intent of a design at a relatively
high level.
❑UPF contents:
– Power intend specification
– Power distribution architecture
– Power strategy
– Special cells usage
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22. Power plan Involvements and Requirements
❑Power planning involves:
– Calculating number of power pins required
– Number of rings, stripes
– Width of rings and stripes
– IR drop
❑Properties of ideal power distribution network:
– Maintain a stable voltage with little noise
– Avoids wear out from EM and self-heating
– Consume little chip area and wiring
– Easy to layout
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23. Power Reduction Techniques
❑Power Gating
❑Clock Gating
❑Voltage & Frequency Scaling
– Changes voltage & clock freq to meet performance
❑Substrate Biasing
– It changes Vt to reduce leakage current
❑Multi Threshold Voltage
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24. Types of Power Dissipation
1. Static Power Dissipation
– In this class, power will be dissipated irrespective of frequency and switching
of the system. It is continuous and has become more dominant at lower node
technologies.
– Reasons for power dissipation:
• Sub threshold current
• Gate oxide leakage
• Diode Reverse bias current
• Gate induced leakage
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25. Types of Power Dissipation
2. Dynamic Power Dissipation
– There are two reasons of dynamic power dissipation: Switching of the device
and Short circuit path from supply (VDD) to ground (VSS). This occurs during
operation of the device.
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26. Power Supply Noises
❑ IR Drop:
The metal layers have their finite amount of resistance. When
voltage is applied the current starts flowing through these metal
layers and some voltage is dropped due to that resistance of a metal
wire and current. This drop is called IR drop.
– Static IR drop
– Dynamic IR drop
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27. ❑ Electromigration:
– When a high density of current is flowing through metal layers, electrons in
the metal layers are displaced from their original position. That causes open
and shorts in the metal layers.
– Heating also accelerates EM.
– Clock nets are more prone to EM because they have high switching activity.
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28. Methods to solve EM
❏ Increase the width of the wire
❏ Buffer insertion
❏ Switch the net to higher metal layer
❏ Adding more vias
❏ Keep the wire length short
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29. Checklist after power planning
❑ All power/ground supplies defined properly?
❑ Is IR drop acceptable?
❑ Is the power supply is uniform?
❑ Are special cells added?
❑ Any power related shorts/opens are present in the design?
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