This webinar explores the acquisition and analysis of PAM4 waveforms. We will show PAM4 Test Configurations, Compliance Measurements and Debug Techniques.
This document discusses test generation for digital circuits. It covers fault detection and location in digital systems, as well as various test generation methods for combinational and sequential logic circuits. For combinational circuits, it describes path sensitization and Boolean difference methods. For sequential circuits, it discusses converting the circuit to combinational form and verifying the state table. The document also discusses design for testability, including testability measures and techniques like LSSD. Reed-Muller expansion is presented as a method to derive and implement logic functions.
PAM4 Analysis and Measurement Webinar Slidedeckteledynelecroy
In this Teledyne LeCroy webinar we explore the acquisition and analysis of PAM4 waveforms. We will cover PAM4 test configurations, compliance measurements and debug techniques.
The document provides an overview of the LPC214x microcontroller family from NXP Semiconductors, which features an ARM7 processor, on-chip flash memory, RAM, analog and digital peripherals like USB, SPI, I2C, and GPIO. It describes the memory architecture and maps as well as the system control block and various peripherals included in the MCU, such as timers, serial interfaces, and an ADC. The document also outlines programming and debugging tools available for the LPC214x family like in-system programming, an embeddedICE logic for debugging, and a trace macrocell for instruction tracing.
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
This document provides an overview of low-density parity-check (LDPC) codes. It discusses Shannon's coding theorem and the evolution of coding technology. LDPC codes were invented by Gallager in 1963 and have simple decoding algorithms that allow them to achieve performance close to the Shannon limit. The document defines regular and irregular LDPC codes using parity check matrices and Tanner graphs. It also discusses code construction, applications of LDPC codes in wireless communications standards, and concludes that LDPC codes are becoming the mainstream in coding technology.
The document discusses event-driven simulation using VHDL. It explains that event-driven simulation only considers signals that are actively changing, making it more efficient than other approaches. The key aspects are:
1) Changes in input and output signals occur at specific simulation times as events are processed from a time-sorted queue.
2) Gates are evaluated when input signals change, with the simulator scheduling new output change events using timing models.
3) An example simulation is shown step-by-step to illustrate how events are processed and new times are scheduled as the model progresses.
This document provides an overview and technical details regarding beamforming and sounding reference signal optimization for LTE. It discusses sector beamforming for common channels using weighted factors. It compares RL15 single-stream beamforming (TM7) to RL25 dual-stream beamforming (TM8), describing their implementations. The document also covers sounding reference signal configurations, including hopping patterns and parameters. Performance results and configuration parameters for beamforming are presented.
CAN (Controller Area Network) is a vehicle bus standard that allows microcontrollers and devices in a vehicle to communicate. It uses a multi-master serial bus topology and CSMA/CD with arbitration on message priority. CAN was introduced in 1986 and standardized in 1993. It supports data transmission rates up to 1Mbps over cables up to 40 meters long, connecting up to 2032 nodes. The document discusses the CAN standards, applications, layered structure, network components, frame types, and advantages/limitations.
This document discusses test generation for digital circuits. It covers fault detection and location in digital systems, as well as various test generation methods for combinational and sequential logic circuits. For combinational circuits, it describes path sensitization and Boolean difference methods. For sequential circuits, it discusses converting the circuit to combinational form and verifying the state table. The document also discusses design for testability, including testability measures and techniques like LSSD. Reed-Muller expansion is presented as a method to derive and implement logic functions.
PAM4 Analysis and Measurement Webinar Slidedeckteledynelecroy
In this Teledyne LeCroy webinar we explore the acquisition and analysis of PAM4 waveforms. We will cover PAM4 test configurations, compliance measurements and debug techniques.
The document provides an overview of the LPC214x microcontroller family from NXP Semiconductors, which features an ARM7 processor, on-chip flash memory, RAM, analog and digital peripherals like USB, SPI, I2C, and GPIO. It describes the memory architecture and maps as well as the system control block and various peripherals included in the MCU, such as timers, serial interfaces, and an ADC. The document also outlines programming and debugging tools available for the LPC214x family like in-system programming, an embeddedICE logic for debugging, and a trace macrocell for instruction tracing.
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
This document provides an overview of low-density parity-check (LDPC) codes. It discusses Shannon's coding theorem and the evolution of coding technology. LDPC codes were invented by Gallager in 1963 and have simple decoding algorithms that allow them to achieve performance close to the Shannon limit. The document defines regular and irregular LDPC codes using parity check matrices and Tanner graphs. It also discusses code construction, applications of LDPC codes in wireless communications standards, and concludes that LDPC codes are becoming the mainstream in coding technology.
The document discusses event-driven simulation using VHDL. It explains that event-driven simulation only considers signals that are actively changing, making it more efficient than other approaches. The key aspects are:
1) Changes in input and output signals occur at specific simulation times as events are processed from a time-sorted queue.
2) Gates are evaluated when input signals change, with the simulator scheduling new output change events using timing models.
3) An example simulation is shown step-by-step to illustrate how events are processed and new times are scheduled as the model progresses.
This document provides an overview and technical details regarding beamforming and sounding reference signal optimization for LTE. It discusses sector beamforming for common channels using weighted factors. It compares RL15 single-stream beamforming (TM7) to RL25 dual-stream beamforming (TM8), describing their implementations. The document also covers sounding reference signal configurations, including hopping patterns and parameters. Performance results and configuration parameters for beamforming are presented.
CAN (Controller Area Network) is a vehicle bus standard that allows microcontrollers and devices in a vehicle to communicate. It uses a multi-master serial bus topology and CSMA/CD with arbitration on message priority. CAN was introduced in 1986 and standardized in 1993. It supports data transmission rates up to 1Mbps over cables up to 40 meters long, connecting up to 2032 nodes. The document discusses the CAN standards, applications, layered structure, network components, frame types, and advantages/limitations.
OPAL-RT Distributed Multi-User LaboratoriesDarcy La Ronde
Learn more about OPAL-RT's high-performance distributed multi-user real-time HIL laboratories, part of our Academic and Research offering, optimized to conduct several HIL projects in parallel.
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
Clock jitter refers to the timing variations of signal edges from their ideal positions. It is typically caused by noise or disturbances in a system. The main sources of jitter include thermal noise, power supply variations, loading conditions, device noise, and interference. Jitter can be measured and expressed in terms of RMS, spectral density, picoseconds, or Unit Intervals. There are different types of jitter including period jitter, cycle-to-cycle jitter, long-term jitter, phase jitter, and time interval error.
This document proposes an efficient memory design for error tolerant applications using built-in self-repair (BISR). It uses built-in self-test (BIST) to test memories for faults and sends that information to built-in redundancy analysis (BIRA) to determine repair solutions. Memories are serially tested and repaired to reduce testing time and switching activities. The proposed approach uses multiple single input change (MSIC) vectors to test memories concurrently, reducing area and performance overhead compared to traditional BISR systems.
Automatic Test Pattern Generation (Testing of VLSI Design)Usha Mehta
The document discusses various methods for automatic test pattern generation (ATPG) in testing VLSI circuits, including:
1) Exhaustive and pseudo-exhaustive methods that test all possible patterns but are infeasible for large circuits.
2) Random and weighted random methods that provide confidence in detecting faults but quality depends on the circuit.
3) Deterministic methods like Boolean difference that compute test vectors to detect specific faults more efficiently than examining all vectors.
4) ATPG uses a two-phase approach - random pattern generation and fault simulation initially to detect many faults easily, followed by targeted deterministic pattern generation to detect remaining faults.
multiple access techniques used in wireless communicationSajid ali
This document discusses multiple access techniques for wireless communication. It describes frequency division duplexing (FDD) and time division duplexing (TDD) for sharing radio spectrum. The main multiple access techniques are described as frequency division multiple access (FDMA), time division multiple access (TDMA), and code division multiple access (CDMA). FDMA allocates different frequency bands to each user, TDMA divides the available time into time slots and allocates one slot per user, and CDMA uses pseudo-random codes to distinguish users transmitting simultaneously on the same frequency. Common cellular systems like AMPS, GSM, and IS-95 are cited as examples.
Contamination delay (tcd) refers to the amount of time needed for a change in a logic input to result in an initial change at an output of combinational logic. It guarantees that the output will not change in response to an input change within tcd time units. For sequential logic, tcd indicates the time needed for a change in the flip-flop clock input to result in an initial change at the flip-flop output. Ensuring inputs are stable for the specified setup time before and hold time after the clock prevents metastability in flip-flops. The determination of a circuit's tcd requires identifying the shortest path of contamination delays from input to output.
A closer view on the hierarchical modulation, going further with the penalty analysis performed in a research paper regarding that subject.
These slides were developed with my dear friend, "Abdulmoeam Ali".
Enjoy .. :)
Orthogonal Frequency Division Multiplexing, OFDM uses a large number of narrow sub-carriers for multi-carrier transmission to overcome the effect of multi path fading problem. LTE uses OFDM for the downlink, from base station to terminal to transmit the data over many narrow band careers of 180 KHz each instead of spreading one signal over the complete 5MHz career bandwidth. OFDM meets the LTE requirement for spectrum flexibility and enables cost-efficient solutions for very wide carriers with high peak rates.
The primary advantage of OFDM over single-carrier schemes is its ability to cope with severe channel conditions. Channel equalization is simplified. The low symbol rate makes the use of a guard interval between symbols affordable, making it possible to eliminate inter symbol interference (ISI).
This document provides an overview of wireless communications and mobile technologies. It discusses early wireless technologies from the 1860s through the development of 1G analog cellular networks in the 1980s using technologies like AMPS. 2G digital cellular networks from the 1990s are described that used standards like GSM, CDMA, and TDMA. 2.5G technologies from the early 2000s like GPRS that added packet data capabilities to GSM networks are also summarized. The document covers wireless characteristics, degrees of mobility, wireless network architectures, and comparisons of standards and their data rates.
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
Flip-flops can enter a metastable state where the output oscillates between 0 and 1 if setup and hold times are violated, such as with asynchronous signals, skewed clocks between domains, or changing inputs in the critical timing window. To resolve metastability, the flip-flop output will eventually settle to a stable 0 or 1 state, though the time to resolve can vary by technology. Cascading multiple flip-flops can help avoid metastable states.
In this project, we are implementing a tool for calculating number of base stations required to meet LTE network coverage and capacity requirement. Coverage planning includes link budget analysis for calculating MAPL and then determining cell radius using RF propagation models. Capacity planning cares about service models and traffic models for calculating required throughput in the network, In addition, it is concerned with calculating cell throughput.
This document outlines how to build a career in physical ASIC design. It discusses the ASIC design flow, job description, required skills set, topics to study, and resources. The conclusion recommends knowing more about the VLSI field, analyzing the job description, strengthening technical and personal skills, and applying. FAQs address whether the field is stressful, which subjects to focus on in college, VLSI companies in Egypt and salaries, and how to enter the field through study, projects, internships, courses and networking.
Logic synthesis is the process of converting a high-level design description into an optimized gate-level representation using a standard cell library and design constraints. The process involves translating the RTL description into an unoptimized internal representation, optimizing the logic, technology mapping, and producing an optimized gate-level netlist. An example logic synthesis flow is described for a 4-bit magnitude comparator design from RTL to optimized gates.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
Synthesis in VLSI is the process of converting your code (program) into a circuit. In terms of logic gates, synthesis is the process of translating an abstract design into a properly implemented chip. Hardware Description Languages (HDLs) are specific programming languages that are used to explain the hardware of a circuit, and the computer subsequently builds the circuit depending on the programme you provided. A “Gate Level Netlist” is what you get once you finish synthesising. This is how your circuit will appear. It demonstrates how everything is interconnected. You can alter it if you like; the computer just synthesizes this netlist based on its best judgement. The synthesizer generates better netlists as the abilities improve and they become more proficient at creating HDL programmes.
The document contains 20 questions and answers related to GSM interview questions. Some key points:
1) The channel used to transmit random access signals is the BCCH (Broadcast Control Channel).
2) The combination of channels that make up the main BCCH is FCH+SCH+BCH+CCCH (Frequency Correction Channel + Synchronization Channel + Broadcast Control Channel + Common Control Channel).
3) The value range for the Timing Advance (TA) parameter in GSM is 0-63.
3 sentences.
The document contains 20 questions and answers related to GSM interview questions. Some key points covered include:
1) The channel used to transmit random access signals is the CCCH.
2) The combination of channels that make up the main BCCH is FCH+SCH+BCH+CCCH.
3) The value range of the Timing Advance in GSM is 0-63.
4) With one paging message using IMSI, 2 MS can be paged.
5) Directed Retry handover refers to a handover from SDCCH to TCH.
OPAL-RT Distributed Multi-User LaboratoriesDarcy La Ronde
Learn more about OPAL-RT's high-performance distributed multi-user real-time HIL laboratories, part of our Academic and Research offering, optimized to conduct several HIL projects in parallel.
VLSI stands for Very Large Scale integration is the art of integrating millions of transistors on a Silicon Chip. Researchers are working to incorporate large scale integration of electronic devices on a single silica chip “Integrated Circuit or IC” to fulfill the market demand. Here, in this presentation we will learn introduction and history of VLSI, VLSI Design Style and Flow, VLSI Design Approaches, CPLD, FPGA, Programmable Logic Arrays, Xilinx vs. Altera Design tools, flow and files.
Clock jitter refers to the timing variations of signal edges from their ideal positions. It is typically caused by noise or disturbances in a system. The main sources of jitter include thermal noise, power supply variations, loading conditions, device noise, and interference. Jitter can be measured and expressed in terms of RMS, spectral density, picoseconds, or Unit Intervals. There are different types of jitter including period jitter, cycle-to-cycle jitter, long-term jitter, phase jitter, and time interval error.
This document proposes an efficient memory design for error tolerant applications using built-in self-repair (BISR). It uses built-in self-test (BIST) to test memories for faults and sends that information to built-in redundancy analysis (BIRA) to determine repair solutions. Memories are serially tested and repaired to reduce testing time and switching activities. The proposed approach uses multiple single input change (MSIC) vectors to test memories concurrently, reducing area and performance overhead compared to traditional BISR systems.
Automatic Test Pattern Generation (Testing of VLSI Design)Usha Mehta
The document discusses various methods for automatic test pattern generation (ATPG) in testing VLSI circuits, including:
1) Exhaustive and pseudo-exhaustive methods that test all possible patterns but are infeasible for large circuits.
2) Random and weighted random methods that provide confidence in detecting faults but quality depends on the circuit.
3) Deterministic methods like Boolean difference that compute test vectors to detect specific faults more efficiently than examining all vectors.
4) ATPG uses a two-phase approach - random pattern generation and fault simulation initially to detect many faults easily, followed by targeted deterministic pattern generation to detect remaining faults.
multiple access techniques used in wireless communicationSajid ali
This document discusses multiple access techniques for wireless communication. It describes frequency division duplexing (FDD) and time division duplexing (TDD) for sharing radio spectrum. The main multiple access techniques are described as frequency division multiple access (FDMA), time division multiple access (TDMA), and code division multiple access (CDMA). FDMA allocates different frequency bands to each user, TDMA divides the available time into time slots and allocates one slot per user, and CDMA uses pseudo-random codes to distinguish users transmitting simultaneously on the same frequency. Common cellular systems like AMPS, GSM, and IS-95 are cited as examples.
Contamination delay (tcd) refers to the amount of time needed for a change in a logic input to result in an initial change at an output of combinational logic. It guarantees that the output will not change in response to an input change within tcd time units. For sequential logic, tcd indicates the time needed for a change in the flip-flop clock input to result in an initial change at the flip-flop output. Ensuring inputs are stable for the specified setup time before and hold time after the clock prevents metastability in flip-flops. The determination of a circuit's tcd requires identifying the shortest path of contamination delays from input to output.
A closer view on the hierarchical modulation, going further with the penalty analysis performed in a research paper regarding that subject.
These slides were developed with my dear friend, "Abdulmoeam Ali".
Enjoy .. :)
Orthogonal Frequency Division Multiplexing, OFDM uses a large number of narrow sub-carriers for multi-carrier transmission to overcome the effect of multi path fading problem. LTE uses OFDM for the downlink, from base station to terminal to transmit the data over many narrow band careers of 180 KHz each instead of spreading one signal over the complete 5MHz career bandwidth. OFDM meets the LTE requirement for spectrum flexibility and enables cost-efficient solutions for very wide carriers with high peak rates.
The primary advantage of OFDM over single-carrier schemes is its ability to cope with severe channel conditions. Channel equalization is simplified. The low symbol rate makes the use of a guard interval between symbols affordable, making it possible to eliminate inter symbol interference (ISI).
This document provides an overview of wireless communications and mobile technologies. It discusses early wireless technologies from the 1860s through the development of 1G analog cellular networks in the 1980s using technologies like AMPS. 2G digital cellular networks from the 1990s are described that used standards like GSM, CDMA, and TDMA. 2.5G technologies from the early 2000s like GPRS that added packet data capabilities to GSM networks are also summarized. The document covers wireless characteristics, degrees of mobility, wireless network architectures, and comparisons of standards and their data rates.
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
Flip-flops can enter a metastable state where the output oscillates between 0 and 1 if setup and hold times are violated, such as with asynchronous signals, skewed clocks between domains, or changing inputs in the critical timing window. To resolve metastability, the flip-flop output will eventually settle to a stable 0 or 1 state, though the time to resolve can vary by technology. Cascading multiple flip-flops can help avoid metastable states.
In this project, we are implementing a tool for calculating number of base stations required to meet LTE network coverage and capacity requirement. Coverage planning includes link budget analysis for calculating MAPL and then determining cell radius using RF propagation models. Capacity planning cares about service models and traffic models for calculating required throughput in the network, In addition, it is concerned with calculating cell throughput.
This document outlines how to build a career in physical ASIC design. It discusses the ASIC design flow, job description, required skills set, topics to study, and resources. The conclusion recommends knowing more about the VLSI field, analyzing the job description, strengthening technical and personal skills, and applying. FAQs address whether the field is stressful, which subjects to focus on in college, VLSI companies in Egypt and salaries, and how to enter the field through study, projects, internships, courses and networking.
Logic synthesis is the process of converting a high-level design description into an optimized gate-level representation using a standard cell library and design constraints. The process involves translating the RTL description into an unoptimized internal representation, optimizing the logic, technology mapping, and producing an optimized gate-level netlist. An example logic synthesis flow is described for a 4-bit magnitude comparator design from RTL to optimized gates.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
Synthesis in VLSI is the process of converting your code (program) into a circuit. In terms of logic gates, synthesis is the process of translating an abstract design into a properly implemented chip. Hardware Description Languages (HDLs) are specific programming languages that are used to explain the hardware of a circuit, and the computer subsequently builds the circuit depending on the programme you provided. A “Gate Level Netlist” is what you get once you finish synthesising. This is how your circuit will appear. It demonstrates how everything is interconnected. You can alter it if you like; the computer just synthesizes this netlist based on its best judgement. The synthesizer generates better netlists as the abilities improve and they become more proficient at creating HDL programmes.
The document contains 20 questions and answers related to GSM interview questions. Some key points:
1) The channel used to transmit random access signals is the BCCH (Broadcast Control Channel).
2) The combination of channels that make up the main BCCH is FCH+SCH+BCH+CCCH (Frequency Correction Channel + Synchronization Channel + Broadcast Control Channel + Common Control Channel).
3) The value range for the Timing Advance (TA) parameter in GSM is 0-63.
3 sentences.
The document contains 20 questions and answers related to GSM interview questions. Some key points covered include:
1) The channel used to transmit random access signals is the CCCH.
2) The combination of channels that make up the main BCCH is FCH+SCH+BCH+CCCH.
3) The value range of the Timing Advance in GSM is 0-63.
4) With one paging message using IMSI, 2 MS can be paged.
5) Directed Retry handover refers to a handover from SDCCH to TCH.
The document provides an overview of ZigBee/IEEE 802.15.4 wireless technology. It discusses the need for low-power, low-cost wireless connectivity for applications like home automation, medical devices, and industrial sensors. It describes the ZigBee Alliance's role in developing networking and application standards on top of the IEEE 802.15.4 physical radio specification. Key features of ZigBee networks include low power consumption, large network capacity, low data rates, and flexibility for many applications.
This document presents the design of a high performance folded cascade OTA and sample and hold circuit. The OTA is designed to achieve 10-bit resolution while operating at a 28 MHz sampling frequency. Simulation results show the OTA achieves a high open loop gain of 72 dB and bandwidth of 112 MHz, with a phase margin of 73 degrees. A low resistance transmission gate switch is designed to reduce charge injection and clock feedthrough effects during sampling. The circuit is implemented in a 130 nm CMOS technology.
The document describes experiments performed on time division multiplexing, pulse code modulation, differential pulse code modulation, delta modulation, frequency shift keying, and differential phase shift keying. The experiments aim to study the principles and characteristics of these digital communication techniques by using equipment like multiplexing/demultiplexing trainer kits, PCM modulator and demodulator kits, and oscilloscopes. The procedures involve applying input signals, observing the output waveforms on oscilloscopes, and analyzing the effects of varying signal parameters.
Cross-Layer Design of Raptor Codes for Video Multicast over 802.11n MIMO Chan...Berna Bulut
This document summarizes a study on using Raptor codes in a cross-layer design for transmitting video over 802.11n MIMO channels. It presented a methodology to select the optimal transmission scheme (SM or STBC), modulation and coding scheme, and Raptor code rate based on channel conditions to minimize transmission time while maintaining low packet error rates. Simulation results showed that Raptor codes can improve performance by enabling higher order modulation at lower SNRs and reducing transmission times, especially in high spatial correlation conditions.
The DS2460Q is a multi-functional cable network testing instrument that supports both digital QAM and analog signals. It provides comprehensive spectrum analysis from 5-1220 MHz, digital TV tests including MER, BER, and constellation diagrams, and analog TV measurements for level, hum, and C/N ratio. Additional features include data logging, auto-generated channel plans, optical power measurement, and a visual fault locator. The DS2460Q is designed for installation, maintenance, and troubleshooting of cable networks.
The document provides an overview of LTE and its evolution from previous cellular standards. It discusses the targets of LTE including high data rates up to 100 Mbps, low latency, high spectral efficiency, and flexibility in spectrum and bandwidth. It also describes the EPS architecture with E-UTRAN, EPC, and the air interface structure of LTE including OFDMA in the downlink and SC-FDMA in the uplink. Key layers like the PHY, MAC, and RLC layers are also summarized.
The document contains questions and answers related to GSM and LTE drive test parameters. It discusses key topics like reference signal receive power (RSRP), reference signal receive quality (RSRQ), signal to noise ratio (SINR), received signal strength indicator (RSSI), physical cell ID (PCI), channel quality indicator (CQI), block error rate (BLER), downlink and uplink throughput, and WCDMA/3G questions and answers related to link budget, TMA, processing gain, and calculating maximum number of users.
WCDMA network optimization involves four key steps:
1. Coverage optimization to ensure adequate signal levels across the network.
2. Neighbor optimization to create accurate neighbor lists and avoid dropped calls.
3. Pilot pollution optimization to reduce interference between cells by adjusting tilts and adding sites.
4. Soft handover optimization to limit the percentage of routes in soft handover through tilt and azimuth changes.
The document provides technical specifications for the CMA5000a OSA optical spectrum analyzer module. It describes the module's key features such as its wide spectral range, high wavelength and power accuracy, excellent polarization dependent loss, and high optical rejection ratio. It also details the module's applications in characterizing EDFA amplifiers and selectively dropping individual wavelengths for further analysis using tunable filters. The document compares the performance of the OSA 425 and OSA 400 modules.
1) The document discusses various short range communication technologies and protocols for IoT devices, including Zigbee and 6LoWPAN.
2) It provides an overview of the Zigbee communication stack, which is based on the IEEE 802.15.4 standard and includes physical, MAC, network and application layers.
3) The Zigbee network layer supports tree-based routing along with an implementation of the AODV routing protocol to allow for more optimized routing in some cases.
This document provides an overview of tests for installing and maintaining LTE eNodeB base stations. It describes the key tests to check characteristics like downlink and uplink speeds, channel bandwidths, frequency bands, frame structure, and modulation schemes. The document then explains specific tests to check aspects like transmission power, occupied bandwidth, spectrum emission mask, ACLR, spurious emissions, and modulation quality of control and data channels. It provides procedures for configuring a tester and interpreting results for each test.
This document provides an overview of interfacing field programmable gate arrays (FPGAs) to analog-to-digital converter (ADC) outputs. It discusses various digital interface protocols and standards used by ADCs, including single data rate CMOS, double data rate CMOS, parallel low voltage differential signaling, serial LVDS, I2C, and JESD204. The document provides recommendations for minimizing noise when interfacing with CMOS outputs and examples of using series termination resistors. It also compares the ANSI and IEEE LVDS standards and shows the effects of trace length on signal integrity. Finally, it includes troubleshooting tips and examples of issues detectable from digital plots.
3G Huawei RAN Resource Monitoring and management.pptNailat2
This document summarizes resources that need to be monitored in a Huawei WCDMA network to avoid congestion and blockages. It discusses monitoring nodeB and cell level resources like CE cards, licenses, OVSF codes, power levels, and Iub bandwidth. It also covers monitoring traffic, KPIs, service distributions and generating relationships between resources, traffic, and quality of service to determine if resources are sufficient. Counter examples are provided to monitor resource usage like TCP, ENU, OVSF code occupancy, and power levels.
This document appears to be an assignment on link adaptation and adaptive modulation and coding. It contains chapters on coding gain and BER, modulation gain and BER, adapting energy per bit, adapting coding technique, and adapting modulation technique. It also includes algorithms and flow charts for adapting energy per bit and coding/modulation techniques. The goal is to dynamically select modulation, coding, and transmission power based on changing channel conditions to optimize throughput while maintaining a target BER.
Engineer EMERSON EDUARDO RODRIGUES PRESENTA UNA NUEVA VERSION
THERE ONE NEW ONE PRESENTATION FOR 2G AND 3G ENGINEERING FOR LTE AND PSCORE ENGINEER
ITS VERY SUITABLE FOR YOUR RESEARCH AT ALL LEVELS OF RF ENGINEERING AND PS CS
The document discusses the OIF CEI-56G projects which are optimizing signal integrity for different interconnect applications. Five projects are underway for chip-to-chip reaches: LR for backplanes up to 100cm, MR for midplanes up to 50cm, VSR for chip-to-module up to 10cm, XSR for chip-to-nearby optics up to 5cm, and USR for 2.5D/3D die-to-die up to 1cm. Modulation variants like NRZ and ENRZ are being considered to meet power and latency requirements for applications like HPC that cannot tolerate forward error correction. Simulation results show ENRZ can achieve sufficient eye opening for long-reach
The final thesis defense presentation for my master's project. The purpose of this thesis was to compare alternative wireless links for transfer of data from sink motes of remote wireless sensor networks to a central repository. A few different protocol stacks to be implemented in the WSN (Wireless Sensor Network) uplink gateway and along with them a few implementation environments based on open source software and low-power hardware were discussed. To facilitate measurements and experimental validation, some of the alternatives have been implemented. Experiments have been made using two of the amateur radio bands, the 144 MHz band (VHF) and the 433 MHz band (UHF). The parameters studied include throughput, range, power-requirements, portability and compatibility with standards.
Using different protocol stacks, different bands and sometimes different hardware 5 solutions were designed, implemented, tested and experimented with. Namely these solutions are called Radiotftp, Radiotftp_process, Radiotunnel, Soundmodem and APRX in this thesis.
After the implementation phase, there was an open-field experimentation to measure the aforementioned parameters. The tests were conducted in Riddarholmen, Stockholm of Sweden. These open-field experiments helped us obtain real-life measurements about power, throughput, stability etc. Experiments were conducted in a range of from a minimum of 2 meters to a maximum of 2.1 kilometers with some of the solutions.
In the end, some of these solutions proved themselves to be viable for the purpose of data communications for remote wireless sensor networks. Radiotftp gave the best throughput in both bands where it proved itself to be difficult to develop further applications. Radiotftp_process removed the necessity for a Linux running gateway machine but it was unable to work with faster baud rates. Radiotunnel opened up the path for a range of network applications to use radio links, but it also proved that it was unstable. On the other hand Soundmodem and APRX which were based on standard and open-source software proved that they were stable but rather slow. It was proven that every approach to problem has its advantages and disadvantages from different aspects such as throughput, range, power-requirements, portability and compatibility.
The document discusses the front-end electronics (FEE) developed for the timing RPCs used in the HADES experiment. The FEE consists of daughter boards (DBOs) connected to the RPC cells that amplify and digitize signals, and mother boards (MBOs) that interface between the DBOs and data acquisition system. The FEE achieves a time resolution of less than 17 ps using a charge-to-width algorithm to encode timing and charge information. Testing shows the FEE performs well and could be adapted for use in the TRASGO detector with some modifications to reduce power consumption.
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The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
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2. About Us: Teledyne LeCroy
o LeCroy founded in 1964 by Walter LeCroy
o Origins are high speed digitizers for particle physics
research
o Teledyne LeCroy corporate headquarters is located in
Chestnut Ridge, NY
o Teledyne LeCroy has the most advanced technology
and widest line of Real-Time digital oscilloscopes
(from 40 MHz to 100 GHz)
o Long History of Innovation in Digital Oscilloscopes
o Teledyne LeCroy became the world leader in protocol
analysis with the purchase of CATC and Catalyst, and
creating a protocol analyzer division based in Santa
Clara, CA.
o In August 2012, LeCroy was acquired by Teledyne
Technologies and was renamed Teledyne LeCroy
o In April 2016 we acquired Frontline Test Equipment
and Quantum Data to add wireless and video to our
protocol analyzer portfolio
3. About the Presenter
1. Field Applications Engineer with
Teledyne LeCroy in Michigan for over
16 years
2. BSEE from Iowa State University and
an MSEE from the University of Arizona
3. Awarded six U.S. patents for
oscilloscope measurement design
Mike Hertz
Senior Field Applications Engineer
Teledyne LeCroy
mike.hertz@teledynelecroy.com
9. Bit rate and baud rate
Bit rate (
𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏
𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
) = Baud rate (
𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
) ∗ (
𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏
𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
)
Bit rate is
#𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏
𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
Baud rate is
#𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠
PAM4 encodes 2 bits into each symbol, therefore a 56 Gb/s throughput requires a PAM4 signal at 28 Gbaud.
56 Gb/s is often referred to as “50G” because coding overhead results in a reduced data payload capacity.
PAM4-based Ethernet standards for 100G, 200G and 400G use 2, 4, or 8 lanes of 28 Gbaud PAM4.
11. Ethernet interfaces and nomenclature
Electrical Optical
Source: Ethernet Alliance
Note that NRZ electrical signaling is used at 10 and 25 Gb/s, and PAM4 is exclusively used for rates 50 Gb/s and higher
12. Ethernet technologies nomenclature (followed by most of the high-speed Ethernet standards)
400GBASE-CDAUI-8
100GBASE-KR2
Aggregate bit rate of
entire link after coding
overhead is removed Interface type
Number of Lanes
Attachment Unit Interface
Backplane interface
Roman numerals for aggregate bitrate
in Gb/s are appended when followed by
“AUI”
400 Gb/s across 8 lanes,
or 50 Gb/s on each lane
100 Gb/s across 2 lanes,
or 50 Gb/s on each lane
Emerging standards such as 50GBASE-KR and 100GBASE-CR2 achieve 50 Gb/s per lane by using PAM4 signaling.
Ethernet standards which have a speed of 50 Gb/s per lane are using 28 Gbaud PAM4 signaling (includes overhead coding),
with a bitrate of 56 Gb/s (data throughput of 50 Gb/s)
13. OIF and IEEE
OIF-CEI56G-*-PAM4, where “*” is a variant:
OIF-CEI56G-XSR-PAM4, for 0-50mm traces
OIF-CEI56G-VSR-PAM4, for 125mm host + 25mm
module traces
OIF-CEI56G-MR-PAM4, for 500mm trace + 1 connector
OIF-CEI56G-LR-PAM4, for 1000mm trace + 2 connectors
Two IEEE 802.3 (Ethernet) amendments:
802.3bs, for 400 GbE (8 lanes of 25G PAM4)
802.3cd, for 50/100/200 GbE (1/2/4 lanes of 25G PAM4)
IEEE 802.3 bs
IEEE 802.3 cd
The VSR variant involves most of the test requirements for PAM4 because:
VSR has normative (compliance) tests which are somewhat unique to it and to XSR
But it also has informative tests which are measurements that also appear in –MR, -LR
and the IEEE specs
Most measurements in this presentation refer to –VSR unless specified otherwise
Most of the measurement concepts can be easily generalized
15. Test point TP1a
“The output of the Host Compliance Board
(HCB) provides access to the host-to-module
electrical signal (host electrical output) defined at
TP1a.”
Signals from the host Tx are measured after
passing through the host’s PCB trace and a
defined Host Compliance Board (HCB). Signals
at TP1a are expected to be measured using a
standard receiver CTLE for CEI-56G.
The HCB can either be a physical compliance
board, or emulated using S-parameters. A .s4p
file is used for the HCB, and CDR and CTLE are
emulated in the scope.
Device
under
test
HCB
16. Test point TP4
“The output of the Module Compliance Board
(MCB) provides access to the module to host
electrical signal (module electrical output)
defined at TP4.”
The signal from a module Tx is measured after
passing through the host’s PCB trace and a
defined Module Compliance Board (MCB).
Signals at TP4 are expected to be measured
using a standard receiver CTLE for CEI-56G,
and the MCB can either be a physical
compliance board, or emulated using S-
parameters. A .s4p S-parameter file is used for
the MCB, and, CDR and CTLE are
implemented within the scope software.
Device
under
test
MCB
17. Test setup for TP0a
“TP0a is defined to be separated from TP0, the ball
of the package performing the host-to-module
transmit function, by 1 dB of PCB attenuation at 14
GHz.”
TP0a does not have a well-defined test setup
because it is not at or near a point of connection in
an actual interface. The goal for TP0a is to connect
as close to the output pin of the Tx chip as possible.
This point is typically accessible for silicon/IP
developers who are working on a development
board.
The exact connection setup and embedding or de-
embedding requirements will vary depending on
what development or evaluation board connections
are available. Signals at TP0a are expected to be
measured without any receiver equalizer emulation,
and VSR tests at TP0a are informative only.
19. PAM4 Differential Voltage, Common Mode Voltage, Common Mode Noise
Differential voltage pk-pk = max(Dp - Dn) – min(Dp - Dn)
Max Common mode voltage = max(Dp + Dn)
Min Common mode voltage = min(Dp + Dn)
RMS Common mode noise = sdev(Dp + Dn)
20. Transition Time Measurement
The Transition Time measurement is described in
the standard as:
“Transition times (rise and fall
times) are defined as the time
between the 20% and 80% times, or 80%
and 20% times, respectively, of
isolated -1 to +1 or +1 to -1 PAM4
edges. Using the QPRBS13-CEI test
pattern the transitions within
sequences of three -1s followed by
three +1s, and three +1s followed by
three -1s, respectively, are
measured. These are PAM4 symbols 1820
to 1825 and 2086 to 2091,
respectively, where symbols 1 to 7
are the run of seven +1’s. In this
case, the 0% level and 100% level may
be estimated as the average signal
within windows from -1.5 UI to -1 UI
and from 1.5 UI to 2 UI relative to
the edge.”
Histogram of rise times
Histogram of fall times Histogram of slew rates
21. CEI-56G-VSR-PAM4 and 106
Signaling speed
Baud rate of 18 – 29 Gbaud
Most devices operate at 28 Gbaud
This corresponds to a raw bit rate
of 56 Gb/s
Forward Error Correction (FEC)
CEI-56G-VSR-PAM4 only requires
a raw BER of only 10-6 (very
different from NRZ signals)
22. Eye Diagram measurements and 106 UI
Most of the eye diagram measurements are
made with specific reference to 10-6
contours because the threshold for FEC in
use by these standards is a BER of 10-6 at
the physical layer. Therefore, unlike NRZ
analysis, extrapolation is not needed for
PAM4 analysis, because 106 symbols can
be easily captured in a single acquisition on
a real-time oscilloscope.
Acquire a sufficient number of UI’s, at least
106, and ideally 107.
10-6 contours are displayed here in green.
24. Eye Diagram measurements: Tmid
Tmid is the midpoint of
the maximum horizontal
eye opening of the 10-3
(red) inner eye contour
of the middle eye.
Tmid is the expected
time position for the
hardware receiver to
sample the signal.
The Tmid calculation is
the starting point for
many other eye-diagram
based measurements.
Tmid
25. Eye Diagram Measurements: EH6 (Eye Height @ 10-6)
EH6 represents the height of the respective
eye at a BER of 10-6, (green contour)
determined from voltage CDFs in a +/-
0.025 UI time window centered on Tmid.
Tmid
EH6 upp
EH6 mid
EH6 low
Note that EH6 is not necessarily measured at the point of
maximal eye height, since EH6 must be measured at
Tmid, the midpoint of the 10-3 (red contour). EH6 is the
distance between intersection points of Tmid and the 10-6
contour ring for each eye.
26. Eye Diagram measurements: EW6
EW6 is the width of the respective eyes
determined from CDFs of eye edges
halfway between the 10-6 points of the
voltage CDFs of the middle eye (EH6/2).
Note that EW6 is not necessarily
measured at the point of maximal eye
width (especially observable for the
upper and lower eyes), since the EW6
measurement location is (EH6/2) for
each eye.
(EH6 mid)/2
EW6 upp
EW6 low
EW6 mid
(EH6 upp)/2
(EH6 low)/2
27. Eye Diagram Measurements: Eye Linearity
Eye Linearity is an alternative to the RLM
measurement (discussed later). Eye
Linearity is defined as:
Where AVupp, AVmid and AVlow are the
average of the eye amplitudes (not heights),
defined as the difference of the mean levels
of the upper and lower level voltage
histograms in a +/- 0.025 UI time window
centered at Tmid.
The measurement of Eye Linearity
determines symmetry of the three eyes. An
ideal signal has an eye linearity of 1.000.
AVupp
AVmid
AVlow
28. Vertical Symmetry and Eye Linearity
Examples of good eye linearity Examples of problematic eye linearity
29. Eye Diagram measurements: Mask test
The VSR mask is purely horizontal
and is defined as:
“…an Eye Width mask centered on
Tmid having a width from the relevant
table which extends above and below
the waveform for the upper and lower
PAM4 eyes. The EW6 low, middle and
upper eye edges shall be outside this
Eye Width mask.”
Because the mask is centered on
Tmid, it’s possible for the upper and
lower eyes to pass the EW6 test (wide
enough at 10-6) but fail the mask test
(not sufficiently centered on Tmid)
Mask
32. Background on Jitter Methodology for PAM4
Many NRZ signal standards require extrapolation of Total Jitter (Tj) to BERs
of 10-12. This required fitting values to a model (dual-dirac), and the terms
involved (Tj, Rj, Dj) are associated with those models and extrapolation
methods.
PAM4 technologies require only a BER of 10-6 at the physical layer. Since
oscilloscopes can easily acquire 106 bits in a single acquisition, traditional
methods of Rj/Dj extrapolation are not needed, and new methods and
terminology is used for PAM4 signaling.
33. Jitter Methodology for PAM4
UUGJ (Unbounded, Uncorrelated Gaussian Jitter) – Conceptually similar to random jitter
UBHPJ (Uncorrelated, Bounded High-Probability Jitter) – Conceptually similar to deterministic
jitter
EOJ (Even-Odd Jitter) – Systematic jitter occurring between even- and odd-numbered
transitions. This was usually called “F/2 jitter” in an NRZ context, and was often mistaken for
DCD.
UJ4 – Measured peak-peak uncorrelated jitter at the 10-4 probability level
UJ6 – Measured peak-peak uncorrelated jitter at the 10-6 probability level
J4 – Measured peak-peak jitter at the 10-4 probability level
J6 – Measured peak-peak jitter at the 10-6 probability level
Note: J4 and J6 are deprecated terms that were used in jitter calculations before UJ4 and UJ6
were adopted in more recent revisions
34. Uncorrelated jitter (UJ4 and UJ6)
A repeating
pattern must
be used
For each
transition in
the pattern,
form a
histogram of
its edge
arrival times
35. Uncorrelated jitter (UJ4 and UJ6)
Remove the
mean from
each edge
histogram
and sum it
with all other
edges from
the same eye
Now we have
an
uncorrelated
jitter (UJ)
histogram for
each of the
three eyes
36. Calculating UUGJ and UBHPJ
A jitter CDF is derived from each
histogram
J4 and J6 are calculated as the
width of the CDF at 10-4 and 10-6
respectively
UUGJ and UBHPJ are
calculated from:
*Equation from CEI-56G-MR-PAM4 spec
37. Even-odd jitter
“Even-odd jitter is measured using two repetitions of a QPRBS13-CEI
test pattern with FIR off. The deviation of the time of each transition from
an ideal clock at the signaling rate is measured.
Even-odd jitter is defined as the magnitude of the difference between
the average deviation of all even-numbered transitions and the average
deviation of all odd-numbered transitions, where determining if a
transition is even or odd is based on possible transitions but only actual
transitions are measured and averaged.”
(from CEI-56G-MR-PAM4 spec)
Note QPRBS13-CEI is a pattern with an odd number of symbols – so in
any repetition, each symbol will land on the “opposite” even/odd clock
edge than it did in the previous repetition.
38. Linear Fit Method
1. Acquire waveform on scope.
2. Resample the waveform using an integer number of samples.
3. Generate an ideal waveform with the same pattern.
4. Deconvolve to obtain a pulse response of a full-swing 0-to-3-to-0 transition to
determine the impulse response of the system.
The mathematical definition is described in
OIF-CEI-03.1, section 11.3.1.6.4.
The linear fit error is calculated as the
difference between the pulse response and the
actual signal for each resampled point.
39. Linear fit pulse response - examples
This signal is
very clean
Note how
controlled the
pulse
response is
The impulse
response is
derived from
the waveform.
Linear fit pulse response
40. Linear fit pulse response - examples
This signal
has twice as
much noise.
Note the pulse
response
hasn’t
changed.
Linear fit pulse response
41. Linear fit pulse response - examples
This signal has
low noise but is
severely
bandwidth-
limited.
Note the pulse
response
reflects the
signal shape.
Linear fit pulse response
42. Linear fit pulse response - examples
Since LFPR is sampled an integer
number of times per UI, we can
decimate it to get one amplitude
value per UI.
This can be used to optimize
transmitter emphasis coefficient
values.
Removes all noise, all pattern
dependent artifacts to produce
ideal normalized coefficient values.
Linear fit pulse response
decimated to one point per UI
43. SNDR
The linear fit error is the difference between the
actual transmitter output signal and the ideal signal,
producing an error vector e(k). SNDR is calculated
using the maximum value of the pulse peak, pmax,
and the linear fit error, e(k). Note the RMS
deviations of the voltage levels are not used in the
calculation.
*from CEI-56G-MR-PAM4 spec
Signal-to-noise-and-distortion ratio (SNDR)
is calculated using the linear fit pulse
response and the linear fit error:
44. Transmitter Linearity (RLM)
This measurement is not required in
normative or informative –VSR tests, but
is required by most other variants
It is conceptually similar to Eye Linearity
but is measured in a different way (and
the resulting values are not directly
comparable)
A perfect signal has an RLM of 1 but it
does not scale the same as eye linearity
The definitions of the signal levels V-1, V-
1/3, V+1/3, V+1 have changed as the
standard evolved
RLM is also referred to as “Level
Separation Mismatch Ratio”
45. RLM – the “old” way
In older specifcation revisions, RLM
required a special pattern to be
used.
Note in this pattern, each symbol is
repeated for 16 UIs to ensure
settling.
The level values were determined
as the voltage at the middle of the
run of 16 symbols.
This pattern was difficult for many
device vendors to generate.
*from IEEE p802.3bj
46. RLM – the “new” way
Now as described in the –VSR spec (and referenced by the others), RLM
derives the voltage levels directly from a QPRBS13 signal (which is
much easier to generate)
The voltage level at the center of each symbol in the pattern is
measured, and these are used to calculate a mean value for each level.
47. RLM – what is measured currently
The RLM calculation was developed
when the “old” way was in use, but
was generalized to estimate RLM for
arbitrary patterns:
Find the longest run of each level
(must be >6 symbols)
Use the center point of this run to
calculate the voltage value for that
level
The result is the correct calculation
on the (now-deprecated) special
pattern, and good on other patterns
Considerations:
If the pattern does not have a
run of >6 UI of all 4 levels, no
values are produced
The measurement can change
substantially if the pattern
changes
Long patterns with long
consecutive symbols yield the
best results
62. Oscilloscope Bandwidth Selection:
Power Spectral Density Example of 28 Gb/s SERDES
The Power Spectral Density of a 28 Gb/s serial data waveform is plotted above, with Power (dB) on the Y-axis and Frequency (GHz) on the X-
axis. For a 28 Gb/s signal: the fundamental frequency is centered at 14 GHz, there is a null at 28 GHz, the third harmonic is centered at 42
GHz, and the next null is at 56 GHz. Therefore, an oscilloscope with at least 56 GHz bandwidth is needed in order to capture all of the power
spectral density of the third harmonic of a 28 Gb/s signal, and all of the PSD associated with the third harmonic will be captured by a
LabMaster 10-60Zi 60 GHz oscilloscope. The darker blue area is the extra power spectral density provided by a 60 GHz oscilloscope
compared to a 32 GHz oscilloscope.
Illustration of harmonic content forming a bit pattern
64. Recommended Oscilloscope Hardware and Software for PAM4 Testing
Serial Data Analyzer oscilloscope
(probably 65 GHz bandwidth)
PAM4 compliance test software
for conformance (and debug)
PAM4 signal analysis software
for PAM4 debug
65. Real Time and Sampling Scopes
Realtime Scope
A realtime scope (bandwidths up to 100 GHz)
typically triggers on a waveform event, then
collects many sample points (millions, billions)
from the single trigger event. The sample
resolution of a realtime acquisition can be as
low as 4.16 ps/pt, which is the inverse of the
sample rate (up to 240 GS/s)
Sampling Scope
A sampling scope (bandwidths up to 80 GHz)
typically triggers on a reference clock, then
collects one sample point per trigger. The
typical sampling scope maximum sample rate is
200 kS/s (slower for long patterns).
• Teledyne LeCroy has the world's highest bandwidth realtime
scope (100 GHz) with world’s highest sample rate (240 GS/s)
Sampling oscilloscope
Bandwidths up to 80 GHz
Max sample rate: 200 kS/s (very
undersampled)
Not able to capture one-time events
Events must be repetitive
Trigger source is mandatory
No software clock recovery for jitter
Limited debug and analysis
Real time oscilloscope
Bandwidths up to 100 GHz real time
Max sample rate: 240 GS/s real time
Able to capture one-time events:
transients, runts, glitches, etc.
Trigger source not required
Software clock recovery for jitter
Advanced debug and analysis
66. Real Time Scopes and Sampling Scopes for PAM4 Testing
A real time scope is able to sample at rates up to 240 Gigasamples per second real time, while a
sampling scope is limited to undersampling the signal at a maximum rate of approximately 200
Kilosamples per second (one million times slower than a real time scope). Unlike a real time
scope, a sampling scope cannot capture a contiguous block of data, so the risk is that low-
frequency anomalies cannot and will not be detected or measured.
A real time scope does not require an external clock source, which completely eliminates trigger
jitter from the measurement. A sampling scope always uses an external clock, which adds jitter
that is not real, into the measurement.
A real time scope is able to detect periodic jitter on contiguous waveform edges and demodulate it,
then display the modulation profile. Unlike a real time scope, a sampling scope cannot capture
contiguous data and therefore cannot identify the source of jitter.
A real time scope is able to display the periodic jitter spectrum in the frequency domain. A sampling
scope cannot do this. By displaying the periodic jitter spectrum, the frequency content of jitter
sources is revealed.
A real time scope can detect one-time glitches in a PAM4 signal. Undetected glitches can cause bit
errors at the receiver. A sampling scope cannot detect one-time glitches.
67. Real Time Scopes and Sampling Scopes for PAM4 Testing
A real time scope can detect one-time runts in a PAM4 signal. Undetected runts can cause bit
errors at the receiver. A sampling scope cannot detect one-time runts.
A real time scope can detect one-time non-monotonic edges in a PAM4 signal. Undetected non-
monotonic edges can cause bit errors at the receiver. A sampling scope cannot detect one-time
non-monotonic edges.
A real time scope can detect a signal dropout in a PAM4 waveform. Signal dropouts can result in
system malfunction. A sampling scope cannot detect a signal dropout.
A real time scope is able to isolate intersymbol interference (ISI) and display the effects of ISI on
the PAM4 pattern. A sampling scope does not have an ISI plot, and therefore cannot determine the
effect of bit order on jitter independently of the serial data pattern.
A real time scope is able to isolate data dependent jitter (DDj) and display the effects of DDj on the
PAM4 pattern. A sampling scope does not have a DDj plot, and therefore cannot determine the
effect of bit order on jitter relative to the serial data pattern.
A real time scope can generate a jitter simulation signal in software, used to verify PAM4 setups
without the need for a physical signal. A sampling scope cannot do this.
68. Real Time Scopes and Sampling Scopes for PAM4 Testing
Not all devices under test have access to the clock signal. In this case, a sampling scope cannot
be used since it requires access to the clock signal. A real time scope does not require a clock
signal.
A real time scope implements a software clock recovery, completely eliminating the effects of CDR
jitter. A sampling scope does not use a software CDR; it uses a hardware CDR, always introducing
hardware CDR jitter.
A sampling scope cannot be used for debug in the event of a PAM4 compliance test failure. A real
time scope provides detailed analysis capabilities including advanced math, measurements, and
custom algorithms to identify root cause of failure.
A real time scope allows for simplified deskewing of a differential signal pair using an automated
process. A sampling scope often requires expensive phase adjusters and a tedious manual
deskewing process.
A real time scope can perform timing measurements between data and clock while viewing both
waveforms, and can analyze the system clock. Since a sampling scope requires using the same
system clock as the reference, it cannot detect problems with the system clock. This is important
to identify and troubleshoot clock-related problems.
A real time scope is able to generate an eye pattern up to 1,000 times faster than a sampling
scope allowing for faster accumulation of meaningful, statistical data. Testing PAM4 using a real
time scope results in faster time to insight.