The Front-End Electronics of the HADES timing RPCs wall. Daniel Belver Fernández  LabCAF-University of Santiago de Compostela
The HADES tRPC TOF wall. The Front-End Electronics (FEE) developed for the RPCs. FEE performances. Time resolution. Calibration of the ‘Charge to Width’ algorithm. In beam results. Summary of the main FEE performances. Adaptation of the FEE to TRASGO detector. OUTLINE
HADES tRPC TOF wall
The RPC Front-End Electronics (FEE) t 1 t 2 FEE-DBOs (108 DBOs/sector x6) FEE-MBOs (16 MBOs/sector x6) Mechanical support board, providing power supply, test signal and threshold DAQs. Amplifying and timing discrimination board (QtoW algorithm).
FEE and DAQ system 4 MBOs/TRB  8 DBOs/MBO  4 cells/DBO 4 TRB/sector  2 LV/sector See M. Traxler talk Trigger ∑ Front-End MBO DBO RPC signals RPC signals RPC cells DC-DC converter Commercial power supply Low voltage system 5 3.3 -5 5V,-5V,3.3V 48V Ethernet TRB Data acquisition system
4-channel & 6-layer board  connected to 4 RPC cells. 1 amplifier (G=35.5 dB, BW=2 GHz, NF=4.5 dB) .   Generates  timing  and  trigger  signals. Time  &  charge encoded  in a single  LVDS digital output  (low power consumption and high noise immunity).  -  Leading edge      Arrival time  (ToF measure). -  Pulse width      Charge  (QtoW algorithm). DaughterBOard (DBO) All SMT available components (R & C 0402 size) SAMTEC connector (40 pins, 0.8 mm pitch) Area=5x4.5 cm 2 1 3 2 4 Width ~charge (QtoW) Arrival  time LVDS
TI OPA690 amp integrates the amplified signal (QtoW algorithm) PHILIPS BGM1013 amp (35.5 dB at 1 GHz) Protected by PHILIPS BAV199 2-diodes  RPC cell One DBO channel: analog stage Analog stage Digital stage Amplified RPC signal Integrated signal
MAX9601 dual PECL discriminator: LE   used for cut/shape the output pulse TI SN65LVDS100 PECL-LVDS converter PHILIPS BFT92 PNP wideband (5 GHz) transistor  for multiplicity trigger sum One DBO channel: digital stage Analog stage Digital stage Discriminator output Latch Enable (LE) Latch Enable/ (LE/)
MotherBOard (MBO) Interfaces board between DBO and DAQ system (TRB). 8-layer board  providing mechanical  support to 32 channels (8 DBOs) or 12 channels (3 DBOs). Area  40x6 cm 2 Area  16.5x6.5 cm 2
Delivers the  timing signals  from 8 DBOs to the TRB. DBO supply voltages ( + 5V,-5V,+3.3V)   Low-Dropout Regulators (ripple filtering). DACs for the thresholds  of the discriminator (DAC program interface). Test signals  distribution.  Combines the 32 multiplicity DBOS signals  low level trigger signal . MBO schematic
FEE performances: time resolution Q=V max  x e -t/R in C R in C>>t r Q=C x V σ t(FEE+TRB)  <40 ps/ch ToF threshold=-20mV σ t(FEE)  < 17  ps/ch (Q>90 fC)
Charge measurements through QtoW algorithm, using pulser signals and RPC signals measurements. FEE performances: QtoW calibration Streamer region Avalanche region
In-beam results QtoW spectrums for one cell ToF threshold=-50 mV σ t =76 ps  3σ tails=2.2%
Summary of the FEE performances
Immediately  application of the FEE to the TRASGO project. FEE adaptation to TRASGO Possible FEE positions Cut view of the TRASGO DBOs placed over one MBO TRB between RPC planes
Power consumption for 128 channels: •  1 TRB   10-20 W. •  4 MBOs+32 DBOs    90-100 W. Possible solutions (new FEE approach): Adapt other RPC-FEE as NINO (CERN) or PADI (GSI). Integrate the FEE in an integrated circuit (ASIC). Power consumption  ≈120 W per TRB FEE improvements for TRASGO Easy for the power supply but not for solar panels.
Thanks for your attention!

D Belver FEE for Trasgos

  • 1.
    The Front-End Electronicsof the HADES timing RPCs wall. Daniel Belver Fernández LabCAF-University of Santiago de Compostela
  • 2.
    The HADES tRPCTOF wall. The Front-End Electronics (FEE) developed for the RPCs. FEE performances. Time resolution. Calibration of the ‘Charge to Width’ algorithm. In beam results. Summary of the main FEE performances. Adaptation of the FEE to TRASGO detector. OUTLINE
  • 3.
  • 4.
    The RPC Front-EndElectronics (FEE) t 1 t 2 FEE-DBOs (108 DBOs/sector x6) FEE-MBOs (16 MBOs/sector x6) Mechanical support board, providing power supply, test signal and threshold DAQs. Amplifying and timing discrimination board (QtoW algorithm).
  • 5.
    FEE and DAQsystem 4 MBOs/TRB 8 DBOs/MBO 4 cells/DBO 4 TRB/sector 2 LV/sector See M. Traxler talk Trigger ∑ Front-End MBO DBO RPC signals RPC signals RPC cells DC-DC converter Commercial power supply Low voltage system 5 3.3 -5 5V,-5V,3.3V 48V Ethernet TRB Data acquisition system
  • 6.
    4-channel & 6-layerboard connected to 4 RPC cells. 1 amplifier (G=35.5 dB, BW=2 GHz, NF=4.5 dB) . Generates timing and trigger signals. Time & charge encoded in a single LVDS digital output (low power consumption and high noise immunity). - Leading edge  Arrival time (ToF measure). - Pulse width  Charge (QtoW algorithm). DaughterBOard (DBO) All SMT available components (R & C 0402 size) SAMTEC connector (40 pins, 0.8 mm pitch) Area=5x4.5 cm 2 1 3 2 4 Width ~charge (QtoW) Arrival time LVDS
  • 7.
    TI OPA690 ampintegrates the amplified signal (QtoW algorithm) PHILIPS BGM1013 amp (35.5 dB at 1 GHz) Protected by PHILIPS BAV199 2-diodes RPC cell One DBO channel: analog stage Analog stage Digital stage Amplified RPC signal Integrated signal
  • 8.
    MAX9601 dual PECLdiscriminator: LE used for cut/shape the output pulse TI SN65LVDS100 PECL-LVDS converter PHILIPS BFT92 PNP wideband (5 GHz) transistor for multiplicity trigger sum One DBO channel: digital stage Analog stage Digital stage Discriminator output Latch Enable (LE) Latch Enable/ (LE/)
  • 9.
    MotherBOard (MBO) Interfacesboard between DBO and DAQ system (TRB). 8-layer board providing mechanical support to 32 channels (8 DBOs) or 12 channels (3 DBOs). Area 40x6 cm 2 Area 16.5x6.5 cm 2
  • 10.
    Delivers the timing signals from 8 DBOs to the TRB. DBO supply voltages ( + 5V,-5V,+3.3V) Low-Dropout Regulators (ripple filtering). DACs for the thresholds of the discriminator (DAC program interface). Test signals distribution. Combines the 32 multiplicity DBOS signals low level trigger signal . MBO schematic
  • 11.
    FEE performances: timeresolution Q=V max x e -t/R in C R in C>>t r Q=C x V σ t(FEE+TRB) <40 ps/ch ToF threshold=-20mV σ t(FEE) < 17 ps/ch (Q>90 fC)
  • 12.
    Charge measurements throughQtoW algorithm, using pulser signals and RPC signals measurements. FEE performances: QtoW calibration Streamer region Avalanche region
  • 13.
    In-beam results QtoWspectrums for one cell ToF threshold=-50 mV σ t =76 ps 3σ tails=2.2%
  • 14.
    Summary of theFEE performances
  • 15.
    Immediately applicationof the FEE to the TRASGO project. FEE adaptation to TRASGO Possible FEE positions Cut view of the TRASGO DBOs placed over one MBO TRB between RPC planes
  • 16.
    Power consumption for128 channels: • 1 TRB 10-20 W. • 4 MBOs+32 DBOs 90-100 W. Possible solutions (new FEE approach): Adapt other RPC-FEE as NINO (CERN) or PADI (GSI). Integrate the FEE in an integrated circuit (ASIC). Power consumption ≈120 W per TRB FEE improvements for TRASGO Easy for the power supply but not for solar panels.
  • 17.
    Thanks for yourattention!