Paging,Segmentation & Segment with Paging
•Download as PPTX, PDF•
1 like•163 views
This is an PPT of Operating System. It include the following topic"Paging,Segmentation & Segment with Paging".
Report
Share
Report
Share
Recommended
Paging and segmentation
This document summarizes and compares paging and segmentation, two common memory management techniques. Paging divides physical memory into fixed-size frames and logical memory into same-sized pages. It maps pages to frames using a page table. Segmentation divides logical memory into variable-sized segments and uses a segment table to map segment numbers to physical addresses. Paging avoids external fragmentation but can cause internal fragmentation, while segmentation avoids internal fragmentation but can cause external fragmentation. Both approaches separate logical and physical address spaces but represent different models of how a process views memory.
What is Cache and how it works
What is Cache?
Cache Operation.
Cache Design.
Direct Mapping
Associative Mapping.
Replacement Algorithm.
Write Policy.
Write Through.
Write Back.
Memory segmentation-of-8086
The document discusses memory segmentation in the Intel 8086 processor. It explains that the 8086's 1MB of memory is divided into segments of varying sizes, including code, data, stack, and extra segments. Each segment is addressed by a 16-bit segment register that stores the segment's base address. To generate the full 20-bit physical address, the base address is combined with a 16-bit offset value contained in registers like IP, BX, DI, SI, and SP. This allows each segment to be up to 64KB in size. Examples are provided to demonstrate how logical addresses are translated to physical memory locations using the segment registers and offsets.
Register introduction
This document provides an introduction to the 8086 microprocessor registers. It defines a register as a small data holding place within the CPU that can store instructions, addresses, or data. The 8086 has several categories of registers including general purpose, pointer, index, segment, and flag registers. General purpose registers are AX, BX, CX, and DX. Pointer registers include BP, SP, and IP. Index registers are SI and DI. Flag registers store status information like carry, zero, and sign flags. The document outlines the role and purpose of each register type used by the 8086 microprocessor.
Allocation methods (1).pptx
The document discusses different methods for allocating disk space and managing free space in file systems. It describes several allocation methods like contiguous allocation, linked allocation, clustering, FAT, indexed allocation, and inode allocation. It also covers approaches for tracking free disk blocks like using a bit vector or linked list of free blocks. The conclusion states that allocation methods impact file access performance and free space management techniques depend on the operating system and storage devices.
Cache memory
About Cache Memory
working of cache memory
levels of cache memory
mapping techniques for cache memory
1. direct mapping techniques
2. Fully associative mapping techniques
3. set associative mapping techniques
Cache memroy organization
cache coherency
every thing in detail
Virtual memory
Virtual memory allows programs to access more memory than the physical memory available on a computer by storing unused portions of memory on disk. It was first developed in 1959-1962 at the University of Manchester. Key aspects of virtual memory include: dividing memory into pages that can be swapped between disk and physical memory as needed, using page tables to map virtual to physical addresses, and page replacement algorithms like LRU to determine which pages to swap out. Virtual memory provides benefits like running more programs simultaneously but can reduce performance due to disk access times.
Register Transfer Language,Bus and Memory Transfer
This document discusses register transfer language (RTL) which provides a concise way to describe operations between registers in a computer using symbolic notation. It defines common registers like the memory address register (MAR) and program counter (PC). Information can be transferred between registers using arrows. Basic symbols are used to denote registers and parts of registers. Transfers can happen over a shared bus connecting all registers. Memory is represented as a device that is accessed using a memory address register to specify the location. RTL provides an organized way to describe the internal operations of a computer concisely and precisely.
Recommended
Paging and segmentation
This document summarizes and compares paging and segmentation, two common memory management techniques. Paging divides physical memory into fixed-size frames and logical memory into same-sized pages. It maps pages to frames using a page table. Segmentation divides logical memory into variable-sized segments and uses a segment table to map segment numbers to physical addresses. Paging avoids external fragmentation but can cause internal fragmentation, while segmentation avoids internal fragmentation but can cause external fragmentation. Both approaches separate logical and physical address spaces but represent different models of how a process views memory.
What is Cache and how it works
What is Cache?
Cache Operation.
Cache Design.
Direct Mapping
Associative Mapping.
Replacement Algorithm.
Write Policy.
Write Through.
Write Back.
Memory segmentation-of-8086
The document discusses memory segmentation in the Intel 8086 processor. It explains that the 8086's 1MB of memory is divided into segments of varying sizes, including code, data, stack, and extra segments. Each segment is addressed by a 16-bit segment register that stores the segment's base address. To generate the full 20-bit physical address, the base address is combined with a 16-bit offset value contained in registers like IP, BX, DI, SI, and SP. This allows each segment to be up to 64KB in size. Examples are provided to demonstrate how logical addresses are translated to physical memory locations using the segment registers and offsets.
Register introduction
This document provides an introduction to the 8086 microprocessor registers. It defines a register as a small data holding place within the CPU that can store instructions, addresses, or data. The 8086 has several categories of registers including general purpose, pointer, index, segment, and flag registers. General purpose registers are AX, BX, CX, and DX. Pointer registers include BP, SP, and IP. Index registers are SI and DI. Flag registers store status information like carry, zero, and sign flags. The document outlines the role and purpose of each register type used by the 8086 microprocessor.
Allocation methods (1).pptx
The document discusses different methods for allocating disk space and managing free space in file systems. It describes several allocation methods like contiguous allocation, linked allocation, clustering, FAT, indexed allocation, and inode allocation. It also covers approaches for tracking free disk blocks like using a bit vector or linked list of free blocks. The conclusion states that allocation methods impact file access performance and free space management techniques depend on the operating system and storage devices.
Cache memory
About Cache Memory
working of cache memory
levels of cache memory
mapping techniques for cache memory
1. direct mapping techniques
2. Fully associative mapping techniques
3. set associative mapping techniques
Cache memroy organization
cache coherency
every thing in detail
Virtual memory
Virtual memory allows programs to access more memory than the physical memory available on a computer by storing unused portions of memory on disk. It was first developed in 1959-1962 at the University of Manchester. Key aspects of virtual memory include: dividing memory into pages that can be swapped between disk and physical memory as needed, using page tables to map virtual to physical addresses, and page replacement algorithms like LRU to determine which pages to swap out. Virtual memory provides benefits like running more programs simultaneously but can reduce performance due to disk access times.
Register Transfer Language,Bus and Memory Transfer
This document discusses register transfer language (RTL) which provides a concise way to describe operations between registers in a computer using symbolic notation. It defines common registers like the memory address register (MAR) and program counter (PC). Information can be transferred between registers using arrows. Basic symbols are used to denote registers and parts of registers. Transfers can happen over a shared bus connecting all registers. Memory is represented as a device that is accessed using a memory address register to specify the location. RTL provides an organized way to describe the internal operations of a computer concisely and precisely.
previous question solve of operating system.
This document contains the answers to several questions about memory management techniques. It compares internal and external fragmentation, discusses how a linkage editor changes binding of instructions and data, and analyzes how first-fit, best-fit, and worst-fit placing algorithms handle sample processes. It also examines the requirements for dynamic memory allocation in different schemes and compares schemes in terms of issues like fragmentation and code sharing.
Cache memoy designed by Mohd Tariq
Cache memory is a small, fast memory located between the CPU and main memory that stores copies of frequently used instructions and data. It accelerates computer speed while keeping costs low. When the CPU requests data, the cache is checked first for a cache hit before accessing the slower main memory. If the data is not found in cache, a cache miss occurs and the data must be retrieved from main memory, which is slower. Replacement algorithms like LRU determine which cached data to replace when new data must be added to a full cache.
U I - 4. 80386 Real mode.pptx
The document provides details about the 80386 processor architecture in real mode. It discusses the 80386 features, architecture, register set, memory addressing, and segmentation in real mode. The architecture of 80386 consists of the central processing unit, memory management unit, and bus interface unit. The central processing unit contains the instruction decoder and execution unit. The execution unit performs operations using the data unit, control unit, and test protection unit.
Cache memory
Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.
Cache memory
Cache memory is a small, fast memory located close to the CPU that stores frequently accessed instructions and data. It aims to bridge the gap between the fast CPU and slower main memory. Cache memory is organized into blocks that each contain a tag field identifying the memory address, a data field containing the cached data, and status bits. There are different mapping techniques like direct mapping, associative mapping, and set associative mapping to determine how blocks are stored in cache. When cache is full, replacement algorithms like LRU, FIFO, LFU, and random are used to determine which existing block to replace with the new block.
Cache Memory
This document discusses various aspects of computer memory systems including cache memory. It begins by defining key terms related to memory such as capacity, organization, access methods, and physical characteristics. It then covers cache memory in particular, explaining the basic concept of caching as well as aspects of cache design like mapping, replacement algorithms, and write policies. Examples of cache configurations from different processor models over time are also provided.
Segment registers
Segment registers specify the location of segments in memory and hold the starting addresses of different segments. The four main segment registers are the code segment register (CS), data segment register (DS), extra segment register (ES), and stack segment register (SS). To reference a specific location within a segment, the processor combines the starting address stored in the segment register with an offset value for that location.
Cache memory ppt
Cache memory is a small, fast memory located close to the processor that stores frequently accessed data from main memory. When the processor requests data, the cache is checked first. If the data is present, there is a cache hit and the data is accessed quickly from the cache. If not present, there is a cache hit and the data must be fetched from main memory, which takes longer. Cache memory relies on principles of temporal and spatial locality, where frequently and nearby accessed data is likely to be needed again soon. Mapping functions like direct, associative, and set-associative mapping determine how data is stored in the cache. Replacement policies like FIFO, LRU, etc. determine which cached data gets replaced when new
Memory System
The memory system of the Intel 80386 microprocessor has the following properties:
- It has a 4GB physical address space that is accessed using virtual addressing via a memory management unit. This allows programs larger than 4GB.
- Memory is divided into four 8-bit wide banks that can each store up to 1GB, allowing the 80386 to transfer 32-bit words in a single cycle.
- There are three types of memory systems used: buffered, pipelined with caches, and interleaved. Buffered systems increase fan-out using buffers. Pipelined systems begin executing instructions before previous ones finish. Interleaved systems improve speed using multiple memory banks.
Virtual memory
Virtual memory is a technique that allows a program to use more memory than the amount physically installed on the system. When physical memory is full, infrequently used pages are written to disk. This allows processes with memory needs greater than physical memory to run. Common page replacement algorithms are first-in, first-out (FIFO), least recently used (LRU), and optimal (OPT) which replaces the page not used for the longest time. Virtual memory provides benefits like allowing more programs to run simultaneously but has disadvantages like reduced performance and system stability.
Introduction to 80386
The document discusses the architecture and features of the Intel 80386 16-bit microprocessor. It describes the key components of the 80386 including the central processing unit with execution and instruction units, memory management unit, and bus interface unit. It also summarizes the 80386's addressing modes, registers, memory management, and real address mode of operation.
Memory Hierarchy (RAM and ROM)
Main memory is made up of RAM and ROM chips. RAM is read-write memory that can be accessed randomly; data is lost when power is off. There are static and dynamic RAM types. Static RAM retains data indefinitely if powered, dynamic RAM must be periodically refreshed. ROM is read-only and permanently stores data. There are mask, PROM, EPROM and EEPROM ROM types that can be programmed at different stages. Cache memory uses fast static RAM. Main memory often uses dynamic RAM for its ability to store large amounts of data at lower cost despite slower access.
Addressing modes of 80386
The 80386 microprocessor provides 11 addressing modes, including register, immediate, direct, register indirect, based, index, scaled index, based index, based scaled index, based index with displacement, and based scaled index with displacement addressing modes. These addressing modes indicate how the source and destination addresses for instructions are accessed and located in memory or registers. The addressing modes allow data to be accessed using registers, immediate values, memory addresses formed from registers and offsets.
UNIT-3.pptx
The document discusses the central processing unit and its components. It describes the general register organization and stack organization of a CPU. It discusses the instruction formats used in CPUs, including three address, two address, one address, zero address, and RISC instruction formats. It also covers addressing modes and data transfer and manipulation instructions used in CPUs.
80486 microprocessor
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
Storage Area Networks Unit 2 Notes
INTELLIGENT DISK SUBSYSTEMS – 2, I/O TECHNIQUES – 1
Caching: Acceleration of Hard Disk Access; Intelligent disk subsystems; Availability of disk subsystems. The Physical I/O path from the CPU to the Storage System; SCSI.
I/O TECHNIQUES – 2, NETWORK ATTACHED STORAGE
Fibre Channel Protocol Stack; Fibre Channel SAN; IP Storage. The NAS Architecture, The NAS hardware Architecture, The NAS Software Architecture, Network connectivity, NAS as a storage system.
Addressing mode Computer Architecture
This document discusses different addressing modes used in computer architecture. It defines 10 addressing modes: immediate, register, register indirect, direct, indirect, implied, relative, indexed, base register, and autoincrement/autodecrement. Each addressing mode is described in terms of how the operand is specified and accessed from memory or registers. Examples are provided to illustrate each addressing mode.
Cache management
A brief introduction to Cache, Types of Cache Miss, Memory Mapping Techniques and Methods to Overcome Cache Miss
Cache memory principles
This document discusses cache memory principles and provides details about cache operation, structure, organization, and design considerations. The key points covered are:
- Cache is a small, fast memory located between the CPU and main memory that stores frequently used data.
- During a cache read operation, the CPU first checks the cache for the requested data. If present, it is retrieved from the fast cache. If not, the data is read from main memory into cache.
- Cache design considerations include size, mapping function, replacement algorithm, write policy, line size, and number of cache levels.
- Modern CPUs use hierarchical cache designs with multiple levels (L1, L2, etc.) to improve performance.
Virtual memory ppt
briefly describe about virtual memory.
what is virtual memory?
advantage of virtual memory
disadvantage of virtual memory
needs of virtual memory
LRU
FIFO
OPT
FIFO ALGORITHM
LRU ALGORITHM
OPT ALGORITHM
PAGE REPLACEMENT ALGORITHM
Memory Management
This document discusses memory management techniques used by operating systems. It covers logical vs physical address spaces, dynamic loading and linking, memory allocation, virtual memory, fragmentation, paging, demand paging, page replacement algorithms, segmentation, and comparisons between paging and segmentation. The key points are that memory management handles memory checks, allocation, protection and tracks memory usage. It allows for virtual memory through techniques like paging and segmentation that map logical to physical addresses.
Memory management
This document discusses memory management techniques in operating systems, specifically paging and segmentation. It explains that paging partitions memory into equal fixed-size chunks called pages, while segmentation divides memory into variable-sized regions called segments. The document then provides details on how the memory management hardware and page/segment tables map logical addresses to physical addresses to allow processes to access memory in these schemes.
More Related Content
What's hot
previous question solve of operating system.
This document contains the answers to several questions about memory management techniques. It compares internal and external fragmentation, discusses how a linkage editor changes binding of instructions and data, and analyzes how first-fit, best-fit, and worst-fit placing algorithms handle sample processes. It also examines the requirements for dynamic memory allocation in different schemes and compares schemes in terms of issues like fragmentation and code sharing.
Cache memoy designed by Mohd Tariq
Cache memory is a small, fast memory located between the CPU and main memory that stores copies of frequently used instructions and data. It accelerates computer speed while keeping costs low. When the CPU requests data, the cache is checked first for a cache hit before accessing the slower main memory. If the data is not found in cache, a cache miss occurs and the data must be retrieved from main memory, which is slower. Replacement algorithms like LRU determine which cached data to replace when new data must be added to a full cache.
U I - 4. 80386 Real mode.pptx
The document provides details about the 80386 processor architecture in real mode. It discusses the 80386 features, architecture, register set, memory addressing, and segmentation in real mode. The architecture of 80386 consists of the central processing unit, memory management unit, and bus interface unit. The central processing unit contains the instruction decoder and execution unit. The execution unit performs operations using the data unit, control unit, and test protection unit.
Cache memory
Explain cache memory with a diagram, demonstrate hit ratio and miss penalty with an example. Discussed different types of cache mapping: direct mapping, fully-associative mapping and set-associative mapping. Discussed temporal and spatial locality of references in cache memory. Explained cache write policies: write through and write back. Shown the differences between unified cache and split cache.
Cache memory
Cache memory is a small, fast memory located close to the CPU that stores frequently accessed instructions and data. It aims to bridge the gap between the fast CPU and slower main memory. Cache memory is organized into blocks that each contain a tag field identifying the memory address, a data field containing the cached data, and status bits. There are different mapping techniques like direct mapping, associative mapping, and set associative mapping to determine how blocks are stored in cache. When cache is full, replacement algorithms like LRU, FIFO, LFU, and random are used to determine which existing block to replace with the new block.
Cache Memory
This document discusses various aspects of computer memory systems including cache memory. It begins by defining key terms related to memory such as capacity, organization, access methods, and physical characteristics. It then covers cache memory in particular, explaining the basic concept of caching as well as aspects of cache design like mapping, replacement algorithms, and write policies. Examples of cache configurations from different processor models over time are also provided.
Segment registers
Segment registers specify the location of segments in memory and hold the starting addresses of different segments. The four main segment registers are the code segment register (CS), data segment register (DS), extra segment register (ES), and stack segment register (SS). To reference a specific location within a segment, the processor combines the starting address stored in the segment register with an offset value for that location.
Cache memory ppt
Cache memory is a small, fast memory located close to the processor that stores frequently accessed data from main memory. When the processor requests data, the cache is checked first. If the data is present, there is a cache hit and the data is accessed quickly from the cache. If not present, there is a cache hit and the data must be fetched from main memory, which takes longer. Cache memory relies on principles of temporal and spatial locality, where frequently and nearby accessed data is likely to be needed again soon. Mapping functions like direct, associative, and set-associative mapping determine how data is stored in the cache. Replacement policies like FIFO, LRU, etc. determine which cached data gets replaced when new
Memory System
The memory system of the Intel 80386 microprocessor has the following properties:
- It has a 4GB physical address space that is accessed using virtual addressing via a memory management unit. This allows programs larger than 4GB.
- Memory is divided into four 8-bit wide banks that can each store up to 1GB, allowing the 80386 to transfer 32-bit words in a single cycle.
- There are three types of memory systems used: buffered, pipelined with caches, and interleaved. Buffered systems increase fan-out using buffers. Pipelined systems begin executing instructions before previous ones finish. Interleaved systems improve speed using multiple memory banks.
Virtual memory
Virtual memory is a technique that allows a program to use more memory than the amount physically installed on the system. When physical memory is full, infrequently used pages are written to disk. This allows processes with memory needs greater than physical memory to run. Common page replacement algorithms are first-in, first-out (FIFO), least recently used (LRU), and optimal (OPT) which replaces the page not used for the longest time. Virtual memory provides benefits like allowing more programs to run simultaneously but has disadvantages like reduced performance and system stability.
Introduction to 80386
The document discusses the architecture and features of the Intel 80386 16-bit microprocessor. It describes the key components of the 80386 including the central processing unit with execution and instruction units, memory management unit, and bus interface unit. It also summarizes the 80386's addressing modes, registers, memory management, and real address mode of operation.
Memory Hierarchy (RAM and ROM)
Main memory is made up of RAM and ROM chips. RAM is read-write memory that can be accessed randomly; data is lost when power is off. There are static and dynamic RAM types. Static RAM retains data indefinitely if powered, dynamic RAM must be periodically refreshed. ROM is read-only and permanently stores data. There are mask, PROM, EPROM and EEPROM ROM types that can be programmed at different stages. Cache memory uses fast static RAM. Main memory often uses dynamic RAM for its ability to store large amounts of data at lower cost despite slower access.
Addressing modes of 80386
The 80386 microprocessor provides 11 addressing modes, including register, immediate, direct, register indirect, based, index, scaled index, based index, based scaled index, based index with displacement, and based scaled index with displacement addressing modes. These addressing modes indicate how the source and destination addresses for instructions are accessed and located in memory or registers. The addressing modes allow data to be accessed using registers, immediate values, memory addresses formed from registers and offsets.
UNIT-3.pptx
The document discusses the central processing unit and its components. It describes the general register organization and stack organization of a CPU. It discusses the instruction formats used in CPUs, including three address, two address, one address, zero address, and RISC instruction formats. It also covers addressing modes and data transfer and manipulation instructions used in CPUs.
80486 microprocessor
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
Storage Area Networks Unit 2 Notes
INTELLIGENT DISK SUBSYSTEMS – 2, I/O TECHNIQUES – 1
Caching: Acceleration of Hard Disk Access; Intelligent disk subsystems; Availability of disk subsystems. The Physical I/O path from the CPU to the Storage System; SCSI.
I/O TECHNIQUES – 2, NETWORK ATTACHED STORAGE
Fibre Channel Protocol Stack; Fibre Channel SAN; IP Storage. The NAS Architecture, The NAS hardware Architecture, The NAS Software Architecture, Network connectivity, NAS as a storage system.
Addressing mode Computer Architecture
This document discusses different addressing modes used in computer architecture. It defines 10 addressing modes: immediate, register, register indirect, direct, indirect, implied, relative, indexed, base register, and autoincrement/autodecrement. Each addressing mode is described in terms of how the operand is specified and accessed from memory or registers. Examples are provided to illustrate each addressing mode.
Cache management
A brief introduction to Cache, Types of Cache Miss, Memory Mapping Techniques and Methods to Overcome Cache Miss
Cache memory principles
This document discusses cache memory principles and provides details about cache operation, structure, organization, and design considerations. The key points covered are:
- Cache is a small, fast memory located between the CPU and main memory that stores frequently used data.
- During a cache read operation, the CPU first checks the cache for the requested data. If present, it is retrieved from the fast cache. If not, the data is read from main memory into cache.
- Cache design considerations include size, mapping function, replacement algorithm, write policy, line size, and number of cache levels.
- Modern CPUs use hierarchical cache designs with multiple levels (L1, L2, etc.) to improve performance.
Virtual memory ppt
briefly describe about virtual memory.
what is virtual memory?
advantage of virtual memory
disadvantage of virtual memory
needs of virtual memory
LRU
FIFO
OPT
FIFO ALGORITHM
LRU ALGORITHM
OPT ALGORITHM
PAGE REPLACEMENT ALGORITHM
What's hot (20)
Similar to Paging,Segmentation & Segment with Paging
Memory Management
This document discusses memory management techniques used by operating systems. It covers logical vs physical address spaces, dynamic loading and linking, memory allocation, virtual memory, fragmentation, paging, demand paging, page replacement algorithms, segmentation, and comparisons between paging and segmentation. The key points are that memory management handles memory checks, allocation, protection and tracks memory usage. It allows for virtual memory through techniques like paging and segmentation that map logical to physical addresses.
Memory management
This document discusses memory management techniques in operating systems, specifically paging and segmentation. It explains that paging partitions memory into equal fixed-size chunks called pages, while segmentation divides memory into variable-sized regions called segments. The document then provides details on how the memory management hardware and page/segment tables map logical addresses to physical addresses to allow processes to access memory in these schemes.
Csc4320 chapter 8 2
Paging is a memory management scheme that allows the physical address space of a process to be non-contiguous. The logical memory is divided into pages of a fixed size, while physical memory is divided into frames of the same size. When accessing a memory location, the CPU generates a page number and page offset. The page number is used to index into a page table stored in main memory to map the logical page to a physical frame. A Translation Lookaside Buffer (TLB) cache is used to improve performance by caching recent page table lookups.
Memory Management
The document discusses various techniques for memory management including basic memory management without swapping or paging, multiprogramming with fixed partitions, swapping, paging, segmentation, page replacement algorithms like FIFO, LRU, and working set, and design issues for paging systems like page size, separate instruction and data spaces, and implementation issues like page fault handling.
Chapter 04
This document discusses various memory management techniques including basic memory management, swapping, virtual memory, page replacement algorithms, segmentation, and the implementation of paging systems. It covers topics such as fixed and variable memory partitioning, page tables, segmentation, page replacement algorithms like FIFO, LRU and working set, and the role of the operating system in memory management.
Hardware implementation of page table
The document discusses different approaches to implementing page tables in hardware. It describes:
1) Using dedicated high-speed registers to store small page tables. For example, the PDP-11 stored its 16-bit page table of 8 entries in registers.
2) Storing large page tables in main memory, using a page table base register and translation lookaside buffer (TLB) to cache recent translations and avoid multiple memory accesses.
3) TLBs store a cache of recent page table entries and allow fast translation of logical to physical addresses if the page is cached, falling back to memory if not present.
Paging +Algorithem+Segmentation+memory management
The document discusses memory management techniques used in computer systems, including memory partitioning, paging, segmentation, and virtual memory. It provides details on:
1) How memory is divided between the operating system and currently running program.
2) The use of fixed and variable size partitions and their tradeoffs.
3) How paging divides programs and memory into pages to more efficiently allocate memory.
4) How segmentation further subdivides memory to simplify programming and enable access controls.
5) How virtual memory uses paging, disk storage, and demand paging to make programs appear larger than physical memory.
CSI-503 - 8.Paging and Segmentation
Paging and segmentation are non-contiguous memory allocation techniques that divide processes into smaller pages or segments. Paging divides memory into equal-sized pages and frames, using a page table to map logical page numbers to physical frame numbers. Segmentation divides processes into variable-sized segments, using a segment table to map logical segment numbers to physical base addresses. Both techniques reduce external fragmentation compared to contiguous allocation, but increase access time and require page/segment tables stored in memory.
Cs416 08 09a
This document discusses virtual memory concepts including:
1. Paging and segmentation allow processes to have portions not currently in main memory by using page/segment tables and bringing pieces into memory on demand via interrupts.
2. Locality of reference and intelligent prepaging of nearby pages can improve efficiency by reducing interrupt overhead from paging.
3. Hardware and OS software support is needed for virtual memory through memory management units, page/segment tables, and algorithms for fetch, placement, and replacement policies.
4. Common policies discussed include demand paging, first/next fit placement, and LRU, clock, and optimal page replacement.
Os unit 2
This document discusses memory management techniques in operating systems including paging, segmentation, and virtual memory. It defines key concepts such as logical versus physical addresses, page tables, frames, and how memory management units map between these spaces. Advantages and disadvantages of different algorithms like FIFO, LRU and clock are presented. The goals of memory management are to allow for more efficient use of limited memory and enable running multiple processes simultaneously.
Memory management
Memory management is the act of managing computer memory. The essential requirement of memory management is to provide ways to dynamically allocate portions of memory to programs at their request, and free it for reuse when no longer needed. This is critical to any advanced computer system where more than a single process might be underway at any time
Unit 5Memory management.pptx
This document discusses different memory management techniques:
- It describes swapping, where a process is temporarily moved out of memory to disk to make room for other processes. Paging and segmentation are also covered, where memory is divided into pages/segments and logical addresses are translated to physical addresses.
- Memory management aims to allocate processes efficiently in memory while avoiding issues like fragmentation. Techniques like contiguous allocation, paging, and segmentation map logical addresses to physical frames and protect memory access.
Ch9 OS
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
OSCh9
This document discusses several memory management techniques:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation.
2. Paging divides memory into pages and processes into page tables to map virtual to physical addresses, reducing fragmentation. It uses translation lookaside buffers (TLBs) to speed address translation.
3. Segmentation divides processes into logical segments and uses segment tables to map segments to physical addresses. It provides a modular view of memory but external fragmentation remains an issue.
OS_Ch9
This document discusses different memory management techniques including:
1. Contiguous allocation allocates processes to contiguous regions of memory but can lead to fragmentation. Paging and segmentation address this by allowing non-contiguous allocation.
2. Paging maps logical addresses to physical frames through a page table. It supports non-contiguous allocation but has translation overhead that is reduced using translation lookaside buffers.
3. Segmentation divides memory into logical segments and uses a segment table to map logical to physical addresses. It matches the user's view of memory but external fragmentation remained an issue until combined with paging.
Main memory os - prashant odhavani- 160920107003
This document describes various memory management techniques used in computer systems, including swapping, contiguous allocation, paging, segmentation, and the memory architecture of the Intel Pentium CPU. It discusses how paging uses a page table to map logical addresses to physical frames through an address translation process. Segmentation divides memory into variable-length segments and uses segment tables. The Pentium supports both pure segmentation and a hybrid of segmentation and paging to translate logical addresses to physical memory locations.
Unix Memory Management - Operating Systems
The document discusses memory management techniques in UNIX, including swapping, demand paging, and how they are implemented in Intel Pentium hardware. Swapping involves copying processes from memory to disk swap space to free up memory. Demand paging only loads pages into memory when accessed. The Pentium supports segmentation and paging, where logical addresses are translated to linear then physical addresses using segment descriptors, page directories and tables.
Chapter 8 - Main Memory
Background
Swapping
Contiguous Memory Allocation
Paging
Structure of the Page Table
Segmentation
Example: The Intel Pentium
Memory+management
The document discusses several memory management techniques including paging, segmentation, and swapping. Paging divides memory into fixed-size blocks called frames and logical memory into blocks called pages. It uses a page table to map logical to physical addresses. Segmentation divides programs into logical segments like code and data and allows segments to be placed anywhere in memory. Swapping temporarily moves processes out of memory to disk to allow other processes to run.
virtual memory
Virtual memory is a memory management technique that allows programs to access memory addresses beyond their actual physical RAM size. It maps virtual addresses to physical addresses stored in RAM or on a hard disk using page tables and a translation process. When a program requests a page not in RAM, a page fault occurs and the OS moves a page from disk to RAM, suspending the program until the page is loaded. Page replacement algorithms like LRU then select pages to remove from RAM and write to disk when RAM is full to make space for new pages. This allows for larger memory sizes, more efficient memory usage, and multitasking.
Similar to Paging,Segmentation & Segment with Paging (20)
More from Meghaj Mallick
24 partial-orderings
This document defines and provides examples of partial order relations. It discusses the key properties of a partial order being reflexive, antisymmetric, and transitive. Examples are given to show that the relation of greater than or equal to (≥) forms a partial order on integers, while division (|) forms a partial order on positive integers. The document also discusses comparability, total orders, well-ordered sets, and Hasse diagrams which are used to visually represent partial orders.
PORTFOLIO BY USING HTML & CSS
The primary focus of the PPT is to develop the initial skill of using HTML & CSS programming language to develop a static web page like Portfolio.
This PowerPoint Presentation is of Front End Design.
This PPT will give an entire view on developing the static web page.
Introduction to Software Testing
The primary focus is on Software Testing process. This PPT will covers the overall process of the software testing.
Introduction to System Programming
The entire PPT focuses about the subject "System Programming".
The PPT consist of the basics of the topic that will cover the entire topic.
MACRO ASSEBLER
This PPT covers the entire topic of Macro Assembler. This Includes the topic such as design of a macro assembler, 3 passes of macro assembler etc.
This is the PPT of System Programming.
Icons, Image & Multimedia
This is an PPT about the Icons that are used in Graphical User Interface, the Images that are used for developing a web page & the use of multimedia for various purpose.
This is an PowerPoint Presentation of Front End Design.
Project Tracking & SPC
This PPT describes about the "Project Tracking" activity & statistical process control at Infosys.
It covers the entire topic such as project tracking, activities tracking, defect tracking, issue tracking, etc.
It covers all main activity of SPC such as SPC analysis, control chart for SPC etc.
This PowerPoint presentation is of "Software Project Management".
Peephole Optimization
This is the PowerPoint presentation on the topic "Peephole Optimization". This presentation covers the entire topic of peephole optimization.
This PowerPoint presentation is of Compiler Design.
Routing in MANET
This is the PPT of "Routing in Manet". It covers the entire topic of routing protocol.
This PowerPoint presentation is of Data Communication & Computer Network.
Macro assembler
The document discusses the design of a two-pass macro preprocessor. In pass one, macro definitions are identified and stored in a macro definition table along with their parameters. A macro name table is also created. In pass two, macro calls are identified and replaced by retrieving the corresponding macro definition and substituting actual parameters for formal parameters using an argument list array. Databases like the macro definition table, macro name table, and argument list array are used to store and retrieve macro information to enable expansion of macro calls. The algorithm scans the input sequentially in each pass to process macro definitions and calls.
Architecture and security in Vanet PPT
This document discusses Vehicular Ad-Hoc Networks (VANETs) which allow vehicles to communicate with each other to share safety and traffic information. It outlines the architecture of VANETs including vehicle-to-vehicle and vehicle-to-infrastructure communication. The document also discusses security issues in VANETs such as bogus information attacks, identity disclosure, and denial-of-service attacks. It proposes the use of authentication, message integrity, privacy, traceability and availability to address these security requirements. The document assumes that roadways are divided into regions managed by trusted roadside infrastructure units.
Design Model & User Interface Design in Software Engineering
This is an PPT of Software Engineering. This contains the following topic such as "Design Model & User Interface Design in Software Engineering ".
Text Mining of Twitter in Data Mining
This is an PPPt of Data Mining.It contains the following topic such as " Text Mining of Twitter in Data Mining".
DFS & BFS in Computer Algorithm
This document discusses breadth-first search (BFS) and depth-first search (DFS) algorithms for traversing graphs. It provides examples of how BFS uses a queue to search all neighbors at the current level before moving to the next level, while DFS uses a stack and explores each branch as far as possible before backtracking. The document compares key differences between BFS and DFS such as their time and space complexities, usefulness for finding shortest paths, and whether queues or stacks are used. Application areas for each algorithm are also mentioned.
Software Development Method
This is PPT of Computer-Science Paper. This presentation consist of various software development method.
Secant method in Numerical & Statistical Method
This is an PPT of a Mathematical Paper i.e Numerical & Statistical Method. It contsin the following topic such as "Secant method in Numerical & Statistical Method ".
Motivation in Organization
This is an PPT of Management. This contains the following topic such as "Motivation in Organization".
Communication Skill
This document discusses communication and barriers to effective communication. It defines communication as the exchange of information, ideas, thoughts and feelings between individuals through speech, writing and behavior. It then outlines some common barriers to communication, including badly expressed messages, loss in transmission, semantic problems, over or under communication, prejudices on the sender's part, and poor attention, inattentive listening, evaluation, interests/attitudes and refutation on the receiver's part. The document suggests identifying and addressing such barriers to improve communication.
Partial-Orderings in Discrete Mathematics
This is an PPT of Discrete Mathematics. It contains the following topic " Partial-Orderings in Discrete Mathematics ".
Hashing In Data Structure
This document provides an introduction to hashing and hash tables. It defines hashing as a data structure that uses a hash function to map values to keys for fast retrieval. It gives an example of mapping list values to array indices using modulo. The document discusses hash tables and their operations of search, insert and delete in O(1) time. It describes collisions that occur during hash function mapping and resolution techniques like separate chaining and linear probing.
More from Meghaj Mallick (20)
Design Model & User Interface Design in Software Engineering
Design Model & User Interface Design in Software Engineering
Recently uploaded
ACTIVE IMPLANTABLE MEDICAL DEVICE IN EUROPE
This presentation will help you to know about the classification ,approval process and article related to active implantable medical device
怎么办理(lincoln学位证书)英国林肯大学毕业证文凭学位证书原版一模一样
原版定制【微信:bwp0011】《(lincoln学位证书)英国林肯大学毕业证文凭学位证书》【微信:bwp0011】成绩单 、雅思、外壳、留信学历认证永久存档查询，采用学校原版纸张、特殊工艺完全按照原版一比一制作（包括：隐形水印，阴影底纹，钢印LOGO烫金烫银，LOGO烫金烫银复合重叠，文字图案浮雕，激光镭射，紫外荧光，温感，复印防伪）行业标杆！精益求精，诚心合作，真诚制作！多年品质 ,按需精细制作，24小时接单,全套进口原装设备，十五年致力于帮助留学生解决难题，业务范围有加拿大、英国、澳洲、韩国、美国、新加坡，新西兰等学历材料，包您满意。
【业务选择办理准则】
一、工作未确定，回国需先给父母、亲戚朋友看下文凭的情况，办理一份就读学校的毕业证【微信bwp0011】文凭即可
二、回国进私企、外企、自己做生意的情况，这些单位是不查询毕业证真伪的，而且国内没有渠道去查询国外文凭的真假，也不需要提供真实教育部认证。鉴于此，办理一份毕业证【微信bwp0011】即可
三、进国企，银行，事业单位，考公务员等等，这些单位是必需要提供真实教育部认证的，办理教育部认证所需资料众多且烦琐，所有材料您都必须提供原件，我们凭借丰富的经验，快捷的绿色通道帮您快速整合材料，让您少走弯路。
留信网认证的作用:
1:该专业认证可证明留学生真实身份
2:同时对留学生所学专业登记给予评定
3:国家专业人才认证中心颁发入库证书
4:这个认证书并且可以归档倒地方
5:凡事获得留信网入网的信息将会逐步更新到个人身份内，将在公安局网内查询个人身份证信息后，同步读取人才网入库信息
6:个人职称评审加20分
7:个人信誉贷款加10分
8:在国家人才网主办的国家网络招聘大会中纳入资料，供国家高端企业选择人才
【关于价格问题（保证一手价格）】
我们所定的价格是非常合理的，而且我们现在做得单子大多数都是代理和回头客户介绍的所以一般现在有新的单子 我给客户的都是第一手的代理价格，因为我想坦诚对待大家 不想跟大家在价格方面浪费时间
对于老客户或者被老客户介绍过来的朋友，我们都会适当给一些优惠。
ServiceNow CIS-ITSM Exam Dumps & Questions [2024]
• For a full set of 530+ questions. Go to
https://skillcertpro.com/product/servicenow-cis-itsm-exam-questions/
• SkillCertPro offers detailed explanations to each question which helps to understand the concepts better.
• It is recommended to score above 85% in SkillCertPro exams before attempting a real exam.
• SkillCertPro updates exam questions every 2 weeks.
• You will get life time access and life time free updates
• SkillCertPro assures 100% pass guarantee in first attempt.
Using-Presentation-Software-to-the-Fullf.pptx
Slides on 7 Commonly Used Presentation Softwares; thier usage and features.
The Intersection between Competition and Data Privacy – KEMP – June 2024 OECD...
The Intersection between Competition and Data Privacy – KEMP – June 2024 OECD...OECD Directorate for Financial and Enterprise Affairs
This presentation by Katharine Kemp, Associate Professor at the Faculty of Law & Justice at UNSW Sydney, was made during the discussion “The Intersection between Competition and Data Privacy” held at the 143rd meeting of the OECD Competition Committee on 13 June 2024. More papers and presentations on the topic can be found at oe.cd/ibcdp.
This presentation was uploaded with the author’s consent.
Gamify it until you make it Improving Agile Development and Operations with ...
So many challenges, so little time. While we’re busy developing software and keeping it operational, we also need to sharpen the saw, but how? Gamification can be a way to look at how you’re doing and find out where to improve. It’s a great way to have everyone involved and get the best out of people.
In this presentation, Ben Linders will show how playing games with the DevOps coaching cards can help to explore your current development and deployment (DevOps) practices and decide as a team what to improve or experiment with.
The games that we play are based on an engagement model. Instead of imposing change, the games enable people to pull in ideas for change and apply those in a way that best suits their collective needs.
By playing games, you can learn from each other. Teams can use games, exercises, and coaching cards to discuss values, principles, and practices, and share their experiences and learnings.
Different game formats can be used to share experiences on DevOps principles and practices and explore how they can be applied effectively. This presentation provides an overview of playing formats and will inspire you to come up with your own formats.
The Intersection between Competition and Data Privacy – OECD – June 2024 OECD...
The Intersection between Competition and Data Privacy – OECD – June 2024 OECD...OECD Directorate for Financial and Enterprise Affairs
This presentation by OECD, OECD Secretariat, was made during the discussion “The Intersection between Competition and Data Privacy” held at the 143rd meeting of the OECD Competition Committee on 13 June 2024. More papers and presentations on the topic can be found at oe.cd/ibcdp.
This presentation was uploaded with the author’s consent.
The Intersection between Competition and Data Privacy – CAPEL – June 2024 OEC...
The Intersection between Competition and Data Privacy – CAPEL – June 2024 OEC...OECD Directorate for Financial and Enterprise Affairs
This presentation by Tim Capel, Director of the UK Information Commissioner’s Office Legal Service, was made during the discussion “The Intersection between Competition and Data Privacy” held at the 143rd meeting of the OECD Competition Committee on 13 June 2024. More papers and presentations on the topic can be found at oe.cd/ibcdp.
This presentation was uploaded with the author’s consent.
2 December UAE National Day - United Arab Emirates
UAE National Day, celebrated on December 2nd, commemorates the unification of the seven emirates and reflects national pride and unity.
The Intersection between Competition and Data Privacy – COLANGELO – June 2024...
The Intersection between Competition and Data Privacy – COLANGELO – June 2024...OECD Directorate for Financial and Enterprise Affairs
This presentation by Professor Giuseppe Colangelo, Jean Monnet Professor of European Innovation Policy, was made during the discussion “The Intersection between Competition and Data Privacy” held at the 143rd meeting of the OECD Competition Committee on 13 June 2024. More papers and presentations on the topic can be found at oe.cd/ibcdp.
This presentation was uploaded with the author’s consent.
Pro-competitive Industrial Policy – LANE – June 2024 OECD discussion
Pro-competitive Industrial Policy – LANE – June 2024 OECD discussionOECD Directorate for Financial and Enterprise Affairs
This presentation by Nathaniel Lane, Associate Professor in Economics at Oxford University, was made during the discussion “Pro-competitive Industrial Policy” held at the 143rd meeting of the OECD Competition Committee on 12 June 2024. More papers and presentations on the topic can be found at oe.cd/pcip.
This presentation was uploaded with the author’s consent.
BRIC_2024_2024-06-06-11:30-haunschild_archival_version.pdf
These are the slides of my presentation at BRIC 2024 about global science overlay maps using OpenAlex.
Proposal: The Ark Project and The BEEP Inc
1.) Introduction
Our Movement is not new; it is the same as it was for Freedom, Justice, and Equality since we were labeled as slaves. However, this movement at its core must entail economics.
2.) Historical Context
This is the same movement because none of the previous movements, such as boycotts, were ever completed. For some, maybe, but for the most part, it’s just a place to keep your stable until you’re ready to assimilate them into your system. The rest of the crabs are left in the world’s worst parts, begging for scraps.
3.) Economic Empowerment
Our Movement aims to show that it is indeed possible for the less fortunate to establish their economic system. Everyone else – Caucasian, Asian, Mexican, Israeli, Jews, etc. – has their systems, and they all set up and usurp money from the less fortunate. So, the less fortunate buy from every one of them, yet none of them buy from the less fortunate. Moreover, the less fortunate really don’t have anything to sell.
4.) Collaboration with Organizations
Our Movement will demonstrate how organizations such as the National Association for the Advancement of Colored People, National Urban League, Black Lives Matter, and others can assist in creating a much more indestructible Black Wall Street.
5.) Vision for the Future
Our Movement will not settle for less than those who came before us and stopped before the rights were equal. The economy, jobs, healthcare, education, housing, incarceration – everything is unfair, and what isn’t is rigged for the less fortunate to fail, as evidenced in society.
6.) Call to Action
Our movement has started and implemented everything needed for the advancement of the economic system. There are positions for only those who understand the importance of this movement, as failure to address it will continue the degradation of the people deemed less fortunate.
No, this isn’t Noah’s Ark, nor am I a Prophet. I’m just a man who wrote a couple of books, created a magnificent website: http://www.thearkproject.llc, and who truly hopes to try and initiate a truly sustainable economic system for deprived people. We may not all have the same beliefs, but if our methods are tried, tested, and proven, we can come together and help others. My website: http://www.thearkproject.llc is very informative and considerably controversial. Please check it out, and if you are afraid, leave immediately; it’s no place for cowards. The last Prophet said: “Whoever among you sees an evil action, then let him change it with his hand [by taking action]; if he cannot, then with his tongue [by speaking out]; and if he cannot, then, with his heart – and that is the weakest of faith.” [Sahih Muslim] If we all, or even some of us, did this, there would be significant change. We are able to witness it on small and grand scales, for example, from climate control to business partnerships. I encourage, invite, and challenge you all to support me by visiting my website.
Disaster Management project for holidays homework and other uses
It talks about disaster management in a helful way.
Artificial Intelligence, Data and Competition – LIM – June 2024 OECD discussion
Artificial Intelligence, Data and Competition – LIM – June 2024 OECD discussionOECD Directorate for Financial and Enterprise Affairs
This presentation by Yong Lim, Professor of Economic Law at Seoul National University School of Law, was made during the discussion “Artificial Intelligence, Data and Competition” held at the 143rd meeting of the OECD Competition Committee on 12 June 2024. More papers and presentations on the topic can be found at oe.cd/aicomp.
This presentation was uploaded with the author’s consent.
Artificial Intelligence, Data and Competition – ČORBA – June 2024 OECD discus...
Artificial Intelligence, Data and Competition – ČORBA – June 2024 OECD discus...OECD Directorate for Financial and Enterprise Affairs
This presentation by Juraj Čorba, Chair of OECD Working Party on Artificial Intelligence Governance (AIGO), was made during the discussion “Artificial Intelligence, Data and Competition” held at the 143rd meeting of the OECD Competition Committee on 12 June 2024. More papers and presentations on the topic can be found at oe.cd/aicomp.
This presentation was uploaded with the author’s consent.
Why Psychological Safety Matters for Software Teams - ACE 2024 - Ben Linders.pdf
Psychological safety in teams is important; team members must feel safe and able to communicate and collaborate effectively to deliver value. It’s also necessary to build long-lasting teams since things will happen and relationships will be strained.
But, how safe is a team? How can we determine if there are any factors that make the team unsafe or have an impact on the team’s culture?
In this mini-workshop, we’ll play games for psychological safety and team culture utilizing a deck of coaching cards, The Psychological Safety Cards. We will learn how to use gamification to gain a better understanding of what’s going on in teams. Individuals share what they have learned from working in teams, what has impacted the team’s safety and culture, and what has led to positive change.
Different game formats will be played in groups in parallel. Examples are an ice-breaker to get people talking about psychological safety, a constellation where people take positions about aspects of psychological safety in their team or organization, and collaborative card games where people work together to create an environment that fosters psychological safety.
Recently uploaded (20)
The Intersection between Competition and Data Privacy – KEMP – June 2024 OECD...
The Intersection between Competition and Data Privacy – KEMP – June 2024 OECD...
Gamify it until you make it Improving Agile Development and Operations with ...
Gamify it until you make it Improving Agile Development and Operations with ...
The Intersection between Competition and Data Privacy – OECD – June 2024 OECD...
The Intersection between Competition and Data Privacy – OECD – June 2024 OECD...
Prsentation for VIVA Welike project 1semester.pptx
Prsentation for VIVA Welike project 1semester.pptx
The Intersection between Competition and Data Privacy – CAPEL – June 2024 OEC...
The Intersection between Competition and Data Privacy – CAPEL – June 2024 OEC...
2 December UAE National Day - United Arab Emirates
2 December UAE National Day - United Arab Emirates
The Intersection between Competition and Data Privacy – COLANGELO – June 2024...
The Intersection between Competition and Data Privacy – COLANGELO – June 2024...
Pro-competitive Industrial Policy – LANE – June 2024 OECD discussion
Pro-competitive Industrial Policy – LANE – June 2024 OECD discussion
BRIC_2024_2024-06-06-11:30-haunschild_archival_version.pdf
BRIC_2024_2024-06-06-11:30-haunschild_archival_version.pdf
Disaster Management project for holidays homework and other uses
Disaster Management project for holidays homework and other uses
Legislation And Regulations For Import, Manufacture,.pptx
Legislation And Regulations For Import, Manufacture,.pptx
Artificial Intelligence, Data and Competition – LIM – June 2024 OECD discussion
Artificial Intelligence, Data and Competition – LIM – June 2024 OECD discussion
Artificial Intelligence, Data and Competition – ČORBA – June 2024 OECD discus...
Artificial Intelligence, Data and Competition – ČORBA – June 2024 OECD discus...
Why Psychological Safety Matters for Software Teams - ACE 2024 - Ben Linders.pdf
Why Psychological Safety Matters for Software Teams - ACE 2024 - Ben Linders.pdf
Paging,Segmentation & Segment with Paging
- 2. CONTENTS Meaning of paging Meaning of segmentation Paging using segmentation
- 3. PAGING Paging is a memory management technique that permits the physical address space of a process to be non-contiguous. In the logical view, the address space of a process consists of a linear arrangement of PAGES. Each page has s bytes in it, where s is a power of 2. The physical memory is divided into fixed block called FRAMES. Size of page = size of frame.
- 4. PAGING HARDWARE The hardware partitions memory into areas called page frames page frames in memory are numbered from 0. At any moment, some page frames are allocated to pages of processes, while others are free. The kernel maintains a list called the free frames list to note the frame numbers of free page frames. While loading a process for execution, the kernel consults the free frames list and allocates a free page frame to each page of the process.
- 5. The MMU decomposes a logical address into the pair (pi , bi ), where pi is the page number and bi is the byte number within page pi . To facilitate address translation, the kernel constructs a page table (PT) for each process. The page table has an entry for each page of the process, which indicates the page frame allocated to the page. While performing address translation for a logical address (pi , bi), the MMU uses the page number pi to index the page table of the process, obtains the frame number of the page frame allocated to pi ,and computes the effective memory address.
- 6. ADDRESS TRANSLATION IN PAGING Page address is called logical address and represented by page number and the offset. Logical Address = Page number + page offset. Frame address is called physical address and represented by a frame number and the offset. Physical Address = Frame number + page offset
- 8. ADVANTAGES AND DISADVANTAGES OF PAGING Paging is simple to implement and assumed as an efficient memory management technique. Due to equal size of the pages and frames, swapping becomes very easy. Page table requires extra memory space, so may not be good for a system having small RAM.
- 9. SEGMENTATION A segment is a logical entity in a program, e.g., a function, a data structure, or an object. Hence it is meaningful to manage it as a unit—load it into memory for execution or share it with other programs. In the logical view, a process consists of a collection of segments. In the physical view, segments of a process exist in nonadjacent areas of memory.
- 10. For example:A process Q consists of five logical entities with the symbolic names main, database, search, update, and stack. While coding the program, the programmer declares these five as segments in Q. This information is used by the compiler or assembler to generate logical addresses while translating the program.
- 11. The figure shows how the kernel handles process Q. The left part of the figure shows the logical view of process Q. To facilitate address translation, the kernel constructs a segment table for Q. Each entry in the table shows the size of a segment and the address of the memory area allocated to it. The MMU uses the segment table to perform address translation. Memory allocation for each segment is performed as in the contiguous memory allocation model. The kernel keeps a free list of memory areas. While loading a process, it searches through this list to perform first-fit or best-fit allocation to each segment of the process.
- 12. SEGMENTATION WITH PAGING In this approach, each segment in a program is paged separately. Accordingly, an integral number of pages is allocated to each segment. A page table is constructed for each segment, and the address of the page table is kept in the segment’s entry in the segment table.
- 13. Figure shows processQ in a system using segmentation with paging. Each segment is paged independently, so internal fragmentation exists in the last page of each segment. Each segment table entry now contains the address of the page table of the segment. The size field in a segment’s entry is used to facilitate a bound check for memory protection.