real mode processor

1. “Processor Architecture &
Interfacing”
Unit I – 80386 Real Mode Details
Sinhgad Technical Education Society
Sinhgad Collge of Engineering
Mr. M V Nimbalkar
Department of Information Technology

2. Unit 1 Syllabus – Lecture wise
Lecture No Topics to be covered
1 Introduction to assembly language programming
2 ALP tools- Assembler, Linker, Loader, Debugger,
Emulator, Assembler directives, Far and near
procedure, Macros
3 DOS Internals, DOS Calls.
4 80386 - Features and Architecture, Register Set, Real
mode segmentation and Address translation
5 80386 - Addressing modes
6 - 8 80386 - Instruction set.

3. 3
80x86 Family of Processors Summarization

4. Comparison of 8086 with 80386
Sr.
no.
8086 80386
1 8086 is 16 bit processor. 30386 is 32 bit processor
2 16 bit data bus and 20 bit address bus 32bit data and address bus.
3 Instruction set is subset of 80386. Instruction set is superset of 8086.
4 Two operating modes maximum and
minimum.
Three operating modes real,
protected and virtual 8086 mode.
5 Memory Addressing Capacity – 1 MB Memory Addressing Capacity – 4 GB
6 Multitasking is not possible Multitasking is possible.
7 Protection feature is not available in
8086
Protection feature is available in
80386.
8 Paging is not available. Paging is available.
9 Less addressing modes are available. More addressing modes are
available.
4

5. 80386 Features
• Two versions 80386DX & 80386SX
• It has 132-pins Pin Grid Array package.
• True 32 bit processor with Data bus, Address bus & ALU bus size = 32
bits.
• 4GB (Gigabyte) of Physical memory.
• It has 64TB (Terabyte) of Virtual memory.
• Maximum size of each segment is 4 GB (Gigabyte).
• It is operated with a frequency of 16MHz-33MHz.
• It can handle 8/16/32-bit data types.
• It has 16 byte prefetch queue.
• The integrated memory management and protection architecture
• Pipelined Architecture with 6 units operating simultaneously
• Instruction pipelining, Integrated support for Multitasking
• Three operating modes – Real, Protected & Virtual 8086
5

6. 80386 Architecture
6
Fig. 1. Architecture of 80386

7. Architecture of 80386
The architecture of 80386DX consists of three functional units:
A] Central Processing Unit.
B] Memory Management Unit.
C] Bus Interface Unit.
A] Central Processing Unit:
Central processing unit is responsible for handling all instructions it receives
from hardware. Central processing unit consists of :
1. Instruction Decoder.
2. Execution Unit.
1. Instruction Decoder:
The instruction decoder unit takes instruction bytes from the code prefetch
queue and translates them into microcode. The decoded instructions are
then stored in the instruction queue. They are passed to the control section
for deriving the necessary control signals.
2. Execution Unit:
Execution unit reads instruction from instruction queue and execute it.
80386 Architecture Functional Units

8. For executing an instruction execution unit has three subunits:
a. Data unit,
b. Control unit
c. Test protection unit
a. Data Unit:
Data unit is responsible for performing different operations on data. It is
divided into three units:
I. Barrel Shifter Adder Unit.
II. Multiply/Divide Unit.
III. Register file.
i. Barrel Shifter Unit:
64-bit barrel shifter used to shift, rotate operations.
ii. Multiply/Divide Unit:
The multiply and divide logic uses a 1-bit per cycle algorithm. The multiply
algorithm stops the iteration when the most significant bits of multiplier
are all zero.
iii. Register File:
Register file contains the eight 32-bit general purpose register which are
used for both address calculation and data operations. It is used to hold
the temporary /intermediate data.
80386 Architecture - Execution Unit

9. b. Control Unit:
It contains microcode and special hardware. The microcode and special
hardware allows 80386DX to reduce time required for execution of multiply
and divide instructions.
Control unit has two sub units:
I. Control ROM
II. Decode and sequencing
i. Control ROM:
It is an intermediate level to execute computer program instructions. Micro
programs were organized as a sequence of microinstruction and stored in
special control memory. It manages the translation of instruction into
micro- instructions.
ii. Decode and Sequencing:
It manages scheduling of the micro- instruction between the various
execution units and deal with results coming from pipeline.
C, Test Protection Unit:
It checks for segmentation violations under the control of the microcode.
80386 Architecture - Execution Unit

10. B] Memory Management Unit:
Memory management unit converts logical address used by the programmer
into physical address.
The memory management unit consists of two subunits :
1. Segmentation unit
2. Paging unit
1. Segmentation unit:
– The segmentation unit translates the 48 bit logical address space into a 32-
bit linear address space. If the paging unit is not enabled then the 32-bit
linear address corresponds to the physical address.
– The segmentation unit compares the effective address for the length limit
specified in the segment descriptor.
– The segment unit adds the segment base and the effective address to
generate linear address.
– Before calculation of linear address it also checks for access rights.
– The limit and attribute PLA checks segment limits and attributes at
segment level to avoid invalid accesses to code and data in the memory
segments.
80386 Architecture – Memory Management Unit

11. 2. Paging Unit:
The paging unit translates the 32 bit linear address space into 32 bit physical
address space. Each segment is divided into one or more 4k byte pages.
Paging unit have 3 sub components
a. Adder:
In adder the selector’s linear base address is added to the offset to from
the physical address.
b. Page cache:
A cache is a small amount of memory which operates more quickly than
main memory. Data is moved from main memory to the cache so that it can
be accessed faster.
a. Control and attributes PLA:
Control and attribute PLA checks the privileges at the page level. Each of
the pages maintains the paging information of the task.
80386 Architecture – Memory Management Unit

12. C] Bus interface unit:
Looks after 80386’s communication with the outside world. It provides 32 bit
data bus and 32 bit address bus. It is responsible for following operations:
– It accepts internal requests for code fetch and data transfers from the
code fetch unit and from the execution unit. It then prioritize the
request with the help of prioritizer and generates signal to perform bus
cycles.
– It sends address and data control signal to communicate with memory
and I/O devices.
– It controls the interface to external bus masters and coprocessors.
Instruction prefetch unit:
• It fetches sequentially the instruction from the memory. It uses bus control
unit to fetch instruction bytes.
• These prefetched instruction bytes are stored in the 16 byte code queue.
The prefetcher always fetches instructions in the order in which they appear
in the memory.
• When the jump or call instructions are executed, the contents of the
prefetched and decode queues are cleared out. And prefetcher again starts
filling up its queue.
80386 Architecture – Bus Interace Unit

13. 80386DX Register Set
The register categories of 80386DX
• General Purpose Registers
[EAX,EBX,ECX,EDX]
• Segment Registers
[CS,DS,SS,ES,GS,FS]
• Pointer and Index Registers
[EIP,ESP,ESI,EDI,EBP]
• Flag Register [EFR]
• Control Registers
[CR0,CR1,CR2,CR3]
• System Address Registers
[GDTR,IDTR,LDTR,TR]
• Debug Registers
[DR0- DR7]
• Test Registers
[TR6 & TR7]

14. Real-Mode Software Architecture
• Reset -> real
mode; object code
compatible with
8086
• Real-mode
software model

15. • Reset and Initialization
– Starting address : FFFFFFF0H
– After the first Intersegment Jump or Call,
– A20-A31 will drop low
Flag Word UUUU0002H
MSW(CR0) UUUUUUU0H
IP 0000FFF0H
CS FFF0H
DS,SS,ES,FS,GS 0000H
DX Component and stepping ID
all other registers undefined
Real-Mode Software Architecture

16. Memory-Address Space and Data Organization
• 80386DX Real-Mode: 1MB of external memory
• 1 MB address space : 8086 address space
Data Types
• Fundamental Data Format : byte, word, double word
• Integer
– unsigned : byte, word, double word; signed : byte, word, double word
• BCD(binary-coded decimal) numbers: packed, unpacked
• ASCII
0
3FFH
400H
FFFFFH
dedicated(interrrupt service vector table)
pointer
segment base
general

17. Segment Registers and Memory Segmentation
• 64 KB segments : 1 MB of memory
• CS(code segment) SS(stack segment)
DS(data segment) ES(extra segment)
FS, GS (data segment F, G)
• 6 segments : total of 384 KB active
memory;
64 K for a code, 64 K for a stack, 256 K
for data storage
• Segments can be set up to be
contiguous, adjacent, disjoint, or even
overlapping

18. General Purpose Registers

19. Pointers and Index Registers
• Two index registers (ESI, EDI) and two pointer registers (EBP, ESP);
• Contains offset addresses (16-bit in real mode: 64 KB)
• ESP(extended stack pointer) and EBP(extended base pointer)
– combined with the contents of the SS register to produce physical memory
address
– TOS (top of stack) : SS:SP
– BP : an offset relative to the SS register
• ESI (extended source index register) and EDI (extended destination index
register)
– automatically combined with the value in the DS register

20. FLAGS REGISTER
• 32-bit flags; just nine of its bits
are active in the real mode
Flag Register
Carry flag(CF): carry-out, borrow-in
Parity flag (PF): set if even parity
Auxiliary carry flag (AF): carry-out
from the low nibble
Zero flag(ZF): arithmetic or logic 0
Sign bit (SF): sign
Overflow flag (OF): the signed result is
out of range
Trap flag (TF): single step mode
Interrupt flag (IF): Maskable interrupt
requests
Direction flag (DF): string operation;
when set, the string ops automatically
decrements the address.

21. • Real-mode physical address generation :
Generating A Real-Mode Memory Addresses

22. • Segment-override prefix
– change the segment from which the variable is
accessed.
– CS and SS: alternate seg : none
– variables, string sources : default DS; alternate seg :
ES, FS, GS, SS, CS
– string destination : ES; alternate seg: none
– BP used as base register: default SS: alternate seg: ES.
FS, GS, DS, CS
– BX used as base register: default DS: alternate seg: ES,
FS, GS, SS, CS
Generating A Real-Mode Memory Addresses

23. Example
1 2 3 4
0 0 2 2
0 0 2 2
1 2 3 4 0
1 2 3 6 2
Segment
Base
Offset
Logical
Address
Physical Address

24. Real-Mode Input / Output Address Space
Real-Mode Input / Output
Address Space
• Separate memory and Input /
Output address spaces
• 64KB I/O address space
• page 0 : 0000H through
00FFH --> direct I/O
• indirect addressing: DX
register