E.ON Energy Research Center builds first interface between OPAL-RT and RTDS Technologies real-time simulators, opens new collaborative research opportunities
E.ON Energy Research Center builds first interface between OPAL-RT and RTDS Technologies real-time simulators, opens new collaborative research opportunities
SIMULATION OF CASCADED H- BRIDGE MULTILEVEL INVERTER USING PD, POD, APOD TECH...ecij
Multilevel inverter (MLI) can achieve medium voltage high power efficiency inverters in industrial
application. It can generate stepped waveform by reducing harmonic distortion with increase in the
number of voltage level; a full bridge is known as H-bridge inverter because it shows alphabet ‘H’. In this
paper, Multicarrier PWM topologies and there Modulation schemes are discussed. Level Shifted [LS]
Scheme is applied to the Cascade H-bridge multilevel inverter and the complete analysis of THD to 9 levels
is done.
Chiptroniks is premier training institute for LED TV Panel Repair. We also manufacture VD-680-ps acf led lcd bonding machine and laser repair machine VD-512. For details contact :+91 9971004998
Abstract
This report focuses on controlling the speed of a DC motor using PWM technique.
Direct current (DC) motors have been widely used in many industrial applications such as electric vehicles, steel rolling mills, electric cranes, and robotic manipulators due to precise, wide, simple, and continuous control characteristics
The dc motor speed in general is directly proportional to the supply voltage, so if reduce the voltage from 12 volts to 6 volts then our speed become half of what it originally had. But in practice, for changing the speed of a dc motor we cannot go on changing the supply voltage all the time. Rather than simply adjusting the voltage sent to the motor, we can switch the motor supply on and off where switching is done so much fast that the motor only notices the average voltage effect and not the switching operation.
In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage
follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um
CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it
consumes only 31.8μW quiescent power and 110MHZ bandwidth.
This product is a parallel 100Gb/s Quad Small Form-factor Pluggable (QSFP28) optical module. It provides increased port density and total system cost savings. The QSFP28 full-duplex optical module offers 4 independent transmit and receive channels, each capable of 25Gb/s operation for an aggregate data rate of 100Gb/s on 100 meters of OM4 multi-mode fiber.
An optical fiber ribbon cable with an MTP/MPO connector can be plugged into the QSFP28 module receptacle. Proper alignment is ensured by the guide pins inside the receptacle. The cable usually cannot be twisted for proper channel to channel alignment. Electrical connection is achieved through an MSA-compliant 38-pin edge type connector.
The module operates by a single +3.3V power supply. LVCMOS/LVTTL global control signals, such as Module Present, Reset, Interrupt and Low Power Mode, are available with the modules. A 2-wire serial interface is available to send and receive more complex control signals, and to receive digital diagnostic information. Individual channels can be addressed and unused channels can be shut down for maximum design flexibility.
The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP28 Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference. The module offers very high functionality and feature integration, accessible via a two-wire serial interface.
Cascaded h bridge multilevel inverter in a three phase eleven leveleSAT Journals
Abstract
This paper essentially concentrates on the design and implementation of a unique topology for a three phase eleven level
cascaded H-bridge multilevel cluverter by employing different kinds of switching schemes. The basic purpose of this paper is to
enhance the number of voltage level at the output without addition of any complexity to power circuit.
The main advantages of this proposed topology is to scale down the THD and reducing electromagnetic interface EMI generation
and high voltage with very close to sine waveform. In this paper, severel kinds of carrier pulse width modulation techniques are
proposed as which scale down the total harmonic distortion and improve the out voltage from the proposed topology and POD
modulation techniques reduce the THD. A number of H-bridge arranged in cascaded to increase the voltage level with the
different switching schemes analyzed in this paper. It is observed that this new topology can be recommended to three phase
eleven level cascaded H-bridge inverter for the best and optimum performance over the conventional methods. This performance
in optimized in the eleven level of inverter.
Improving the fundamental waveforms and reducing the total harmonic distortion by using 60 IGBTs and switching is arranged
by a topology in cascaded manners.
The simulation model is produced by MATLAB2009 software version.
Key Words: Cascaded H-bridge multilevel inverter, different phase pulse width modulation, total harmonic
distortionTHD, EMI
This DataComm product is a transceiver module designed for 2km optical communication applications. The
design is compliant to IEEE802.3ba and 100G-CLR4 standard. The module converts 4 inputs channels
of 25Gb/s electrical data to 4 CWDM optical signals, and multiplexes them into a single channel for
100Gb/s optical transmission. Reversely, on the receiver side, the module optically de-multiplexes a
100Gb/s input into 4 CWDM channels signals, and converts them to 4 channel output electrical data.
FOUR QUADRANT SPEED CONTROL OF DC MOTOR USING AT89S52 MICROCONTROLLERJournal For Research
Speed control of a machine is the most vital and important part in any industrial organization. This paper is designed to develop a four quadrant speed control system for a DC motor using microcontroller. The motor is operated in four quadrants i.e. clockwise, counter clock-wise, forward brake and reverse brake. It also has a feature of speed control. The four quadrant operation of the dc motor is best suited for industries where motors are used and as per requirement they can rotate in clockwise, counter-clockwise and also apply brakes immediately in both the directions. In case of a specific operation in industrial environment, the motor needs to be stopped immediately. In such scenario, this proposed system is very apt as forward brake and reverse brake are its integral features. Instantaneous brake in both the directions happens as a result of applying a reverse voltage across the running motor for a brief period and the speed control of the motor can be achieved with the PWM pulses generated by the microcontroller. The microcontroller used in this project is from 8051 family. Push buttons are provided for the operation of the motor which are interfaced to the microcontroller that provides an input signal to it and controls the speed of the motor through a motor driver IC. The speed and direction of DC motor has been observed on digital CRO. Microcontroller programming has been written in assembly language by using notepad and it has been converted in hex file by using micro vision Kiel. The burning of programming in the 8051 microcontroller chip has been done by using positron boot loader software.
Real-Time Hardware-in-the-Loop Testing of an Excitation Control System for Os...Luigi Vanfretti
Poster Presentation at the IEEE PES General Meeting.
A feature of an Excitation Control System (ECS) for synchronous generators is to enable power system stabilization by providing an additional input to the Automatic Voltage Regulator (AVR) for external stabilization signals. This paper explores this feature by externally generating stabilization signals which are fed as an analog input to a commercial ECS. This allows bypassing the built-in PSS function in the ECS and gives more freedom to the end-user to utilize custom stabilizer models. ABB’s Unitrol 1020 Excitation Control System is coupled with Opal-RT’s eMEGAsim Real-Time simulator to perform Hardware-in-the-Loop simulation of the ECS. The output of several stabilizer models is fed to the ABB’s Unitrol 1020 ECS as external power system stabilization signals to analyze their performance for small signal stability enhancement.
SIMULATION OF CASCADED H- BRIDGE MULTILEVEL INVERTER USING PD, POD, APOD TECH...ecij
Multilevel inverter (MLI) can achieve medium voltage high power efficiency inverters in industrial
application. It can generate stepped waveform by reducing harmonic distortion with increase in the
number of voltage level; a full bridge is known as H-bridge inverter because it shows alphabet ‘H’. In this
paper, Multicarrier PWM topologies and there Modulation schemes are discussed. Level Shifted [LS]
Scheme is applied to the Cascade H-bridge multilevel inverter and the complete analysis of THD to 9 levels
is done.
Chiptroniks is premier training institute for LED TV Panel Repair. We also manufacture VD-680-ps acf led lcd bonding machine and laser repair machine VD-512. For details contact :+91 9971004998
Abstract
This report focuses on controlling the speed of a DC motor using PWM technique.
Direct current (DC) motors have been widely used in many industrial applications such as electric vehicles, steel rolling mills, electric cranes, and robotic manipulators due to precise, wide, simple, and continuous control characteristics
The dc motor speed in general is directly proportional to the supply voltage, so if reduce the voltage from 12 volts to 6 volts then our speed become half of what it originally had. But in practice, for changing the speed of a dc motor we cannot go on changing the supply voltage all the time. Rather than simply adjusting the voltage sent to the motor, we can switch the motor supply on and off where switching is done so much fast that the motor only notices the average voltage effect and not the switching operation.
In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage
follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um
CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it
consumes only 31.8μW quiescent power and 110MHZ bandwidth.
This product is a parallel 100Gb/s Quad Small Form-factor Pluggable (QSFP28) optical module. It provides increased port density and total system cost savings. The QSFP28 full-duplex optical module offers 4 independent transmit and receive channels, each capable of 25Gb/s operation for an aggregate data rate of 100Gb/s on 100 meters of OM4 multi-mode fiber.
An optical fiber ribbon cable with an MTP/MPO connector can be plugged into the QSFP28 module receptacle. Proper alignment is ensured by the guide pins inside the receptacle. The cable usually cannot be twisted for proper channel to channel alignment. Electrical connection is achieved through an MSA-compliant 38-pin edge type connector.
The module operates by a single +3.3V power supply. LVCMOS/LVTTL global control signals, such as Module Present, Reset, Interrupt and Low Power Mode, are available with the modules. A 2-wire serial interface is available to send and receive more complex control signals, and to receive digital diagnostic information. Individual channels can be addressed and unused channels can be shut down for maximum design flexibility.
The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP28 Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference. The module offers very high functionality and feature integration, accessible via a two-wire serial interface.
Cascaded h bridge multilevel inverter in a three phase eleven leveleSAT Journals
Abstract
This paper essentially concentrates on the design and implementation of a unique topology for a three phase eleven level
cascaded H-bridge multilevel cluverter by employing different kinds of switching schemes. The basic purpose of this paper is to
enhance the number of voltage level at the output without addition of any complexity to power circuit.
The main advantages of this proposed topology is to scale down the THD and reducing electromagnetic interface EMI generation
and high voltage with very close to sine waveform. In this paper, severel kinds of carrier pulse width modulation techniques are
proposed as which scale down the total harmonic distortion and improve the out voltage from the proposed topology and POD
modulation techniques reduce the THD. A number of H-bridge arranged in cascaded to increase the voltage level with the
different switching schemes analyzed in this paper. It is observed that this new topology can be recommended to three phase
eleven level cascaded H-bridge inverter for the best and optimum performance over the conventional methods. This performance
in optimized in the eleven level of inverter.
Improving the fundamental waveforms and reducing the total harmonic distortion by using 60 IGBTs and switching is arranged
by a topology in cascaded manners.
The simulation model is produced by MATLAB2009 software version.
Key Words: Cascaded H-bridge multilevel inverter, different phase pulse width modulation, total harmonic
distortionTHD, EMI
This DataComm product is a transceiver module designed for 2km optical communication applications. The
design is compliant to IEEE802.3ba and 100G-CLR4 standard. The module converts 4 inputs channels
of 25Gb/s electrical data to 4 CWDM optical signals, and multiplexes them into a single channel for
100Gb/s optical transmission. Reversely, on the receiver side, the module optically de-multiplexes a
100Gb/s input into 4 CWDM channels signals, and converts them to 4 channel output electrical data.
FOUR QUADRANT SPEED CONTROL OF DC MOTOR USING AT89S52 MICROCONTROLLERJournal For Research
Speed control of a machine is the most vital and important part in any industrial organization. This paper is designed to develop a four quadrant speed control system for a DC motor using microcontroller. The motor is operated in four quadrants i.e. clockwise, counter clock-wise, forward brake and reverse brake. It also has a feature of speed control. The four quadrant operation of the dc motor is best suited for industries where motors are used and as per requirement they can rotate in clockwise, counter-clockwise and also apply brakes immediately in both the directions. In case of a specific operation in industrial environment, the motor needs to be stopped immediately. In such scenario, this proposed system is very apt as forward brake and reverse brake are its integral features. Instantaneous brake in both the directions happens as a result of applying a reverse voltage across the running motor for a brief period and the speed control of the motor can be achieved with the PWM pulses generated by the microcontroller. The microcontroller used in this project is from 8051 family. Push buttons are provided for the operation of the motor which are interfaced to the microcontroller that provides an input signal to it and controls the speed of the motor through a motor driver IC. The speed and direction of DC motor has been observed on digital CRO. Microcontroller programming has been written in assembly language by using notepad and it has been converted in hex file by using micro vision Kiel. The burning of programming in the 8051 microcontroller chip has been done by using positron boot loader software.
Real-Time Hardware-in-the-Loop Testing of an Excitation Control System for Os...Luigi Vanfretti
Poster Presentation at the IEEE PES General Meeting.
A feature of an Excitation Control System (ECS) for synchronous generators is to enable power system stabilization by providing an additional input to the Automatic Voltage Regulator (AVR) for external stabilization signals. This paper explores this feature by externally generating stabilization signals which are fed as an analog input to a commercial ECS. This allows bypassing the built-in PSS function in the ECS and gives more freedom to the end-user to utilize custom stabilizer models. ABB’s Unitrol 1020 Excitation Control System is coupled with Opal-RT’s eMEGAsim Real-Time simulator to perform Hardware-in-the-Loop simulation of the ECS. The output of several stabilizer models is fed to the ABB’s Unitrol 1020 ECS as external power system stabilization signals to analyze their performance for small signal stability enhancement.
Performance improvement of parallel active power filters using droop control ...Ghazal Falahi
In this paper, a new method based on droop control scheme is proposed for controlling parallel operation of active filters. The harmonic components of the load current are extracted by an enhanced phase-locked loop (EPLL). In the parallel group, each filter operates as a conductance and the harmonic workload is shared among them. A droop relationship between the conductance and non-fundamental apparent power controls the operation of each unit. The non-fundamental apparent power has been calculated based on IEEE Std 1459. Principles of operation are explained in this paper and simulation results which are presented approve the effectiveness of this method. The results indicate a significant reduction in Total Harmonic Distortion (THD) in a rectifier application.
In this webinar, learn how OPAL-RT's state-of-the-art Hardware-in-the-Loop (HIL) simulation solutions empower engineers to design and test ECUs, and other integrated power electronic systems and controllers, with efficiency.
The OP1200, Lab-Scale Modular Multilevel Converters Test Bench, is dedicated to the hardware verification of new control algorithms for new and existing power electronic converter topologies. It is used for experimental work on converter interactions and network control.
In this webinar, learn about common cybersecurity threats and the crucial role played by real-time digital simulation in the reinforcement of cybersecurity in power systems.
Challenges in Protection Relay Testing for Tomorrow’s Power Grid
Very many challenges related to protection relay testing are met today in the field and in the research industry.
There are often new and more complex applications such as wind turbines, very fast switching power electronics, photovoltaic cells and the battery and electric vehicle technologies. This implies among other things new converter topologies and smart grid considerations. These systems cannot be protected the same way as what was already being done, so this increases the complexity of the algorithms used.
Real-time simulation is a novel approach to design and test protection relay algorithms.
MIPI DevCon 2021: MIPI I3C Signal Integrity Challenges on DDR5-based Server P...MIPI Alliance
Presented by Azusena Lupercio Ramirez, Juan Orozco and Nestor Hernandez Cruz, Intel Corporation
The MIPI I3C® protocol is first used in a server application for the DDR5 DIMM SPD function. MIPI I3C was defined for low capacitance applications, while DDR5 SPD exceeds by far the bus capacitance specification. This presentation covers the interoperability challenges of the dynamic push-pull and open-drain operating modes, on server applications with an in-depth analysis of the implications of long PCB traces, multiple DIMM routing branches, and multiple loads to the electrical and timing parameters.
This connection or communication of multiple microcontrollers in a network is to a get a desired output. It is widely used in modern automobile industries. More and more microcontrollers are embedded in different kinds of products from industrial environment to domestic area.
Detailed large-scale real-time HYPERSIM EMT simulation for transient stabilit...OPAL-RT TECHNOLOGIES
Towards cloud-based real-time HIL for wide-area special control and protection system testing
Presented by: Jean Belanger, President and CTO of OPAL-RT TECHNOLOGIES
Abstract: High penetration of inverter-based Distributed Energy Resources (DERs), widespread installation of FACTS and HVDC interconnection systems, and the decommissioning of thermal and nuclear plants are significantly reducing inertia in large-scale power systems. Fast power-electronics based control and protection schemes act to stabilize these systems, but they are sensitive to harmonics, transients, and system imbalances. It has been shown that simplified positive-sequence RMS models alone are insufficient for Transient Stability Assessment (TSA) of large-scale, low-inertia power grids. Therefore, utilities and regulators such as NERC, as well as professional associations such as CIGRE and IEEE, have begun investigating detailed EMT simulation to assess the transient stability of large-scale, low-inertia power grids that include power-electronic plant controllers.
However, detailed EMT simulation of large-scale power grids for 20 to 30 second time-frames and hundreds of contingencies presents a number of computational and analytic challenges including excessive simulation time, large-scale grid data management and the unavailability of detailed and validated models of power-electronic plant controllers. Furthermore, these plant controllers, if they are provided by OEMs, are in the form of blackbox, pre-compiled DLLs, which are implemented for specific simulation tools, without any interoperability standard.
This presentation will describe OPAL-RT solutions to achieve very large-scale, detailed grid EMT simulation in real-time for Hardware-in-the-Loop (HIL) / Software-in-the-Loop (SIL) control and protection testing, as well as quasi-real-time simulation for fast TSA evaluation of large-scale, low-inertia power systems. With these solutions, blackboxcontrol and protection systems can be implemented natively in the EMT simulation tool, HYPERSIM. PSCAD DLLs can also be co-simulated with HYPERSIM using a software interface based on the CIGRE model-interoperability guidelines.
Such advances will accelerate connection studies and can be used to implement cloud-native tools to help operators assess system stability with hundreds of contingencies in 5-to 10-minute time-frames. This performance can be achieved for grids having several thousand busses with a 50-microsecond time-step using a few hundred processors.
As HYPERSIM runs under Windows or LINUX, powerful cloud-based applications can be implemented for TSA and to test wide area control and protection systems using SIL or HIL with real control and protection software and hardware. Communication system emulators, such as eXata can also be used to analyze cyber-attacks and countermeasures as well as to evaluate the effect of communication failures and delays on system performance.
Learn more at www.opal-rt.com
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
2. 2
Your Hosts
Presenter
Luc-André Grégoire
Simulation Specialist
OPAL-RT TECHNOLOGIES
Lead Demo
Wei Li
Lead Specialist, Power System
Simulation
OPAL-RT TECHNOLOGIES
Special Guest
Sébastien Dennetière
Power system engineer
RTE FRANCE
Jean Belanger
CEO & CTO
OPAL-RT TECHNOLOGIES
3
Darcy Laronde
Business development
OPAL-RT TECHNOLOGIES
3. 3
Presentation Outline
• Introduction to Modular Multilevel Converter (MMC)
• Challenges of MMC in HIL
• Live demo: Real-Time / Fast Simulation of MMC
• Benefits and features of MMC solutions
• Modeling of MMC for the France-Spain link by RTE
• Vision MMC - Accuracy and Flexibility
4
4. 4
MMC business at OPAL-RT TECHNOLOGIES
• Founded in 1997, leading developer of open Real-Time Digital Simulators
and Hardware-in-the-loop testing equipment for:
o Electrical, electro-mechanical and power electronic systems.
o Headquarters: Montreal and regional subsidiaries in OPAL-RT Europe,
India and USA.
• OPALRT’s MMC Hardware-in-the-loop Simulation can emulate
MMC systems
• Our platforms can be interconnected to simulate several MMCs in real time
• MMC is becoming a more and more significant portion of our Global
Business
5
5. 5
MMC Customers
6
customer site delivery
MMC model /
Hardware
cell number
/Terminals
IO/protocol projects
ABB Switzerland 2012
MMC FPGA model, MMC
controller/OP7000
8*6
2 terminals
48 AO, 96 DI
Hardware-in-the-loop test
controller
Alstom UK 2012 MMC cpu model /OP5600
100*6
2 terminals
no Fast simulation
China South Grid (CSG) China
2013
MMC FPGA
model/OP7020
200*6
3 terminals
Aurora
Simulation a real 3-terminal
MMC HVDC project and
validation its controller
China Electric Power
Research Institute
(CEPRI)
China 2013
MMC FPGA
model/OP7000
500*6
2 terminals
no
Simulation of a 3-terminal MMC
HVDC project
Nari-Relays (NR)
phase 1
China 2011
MMC CPU and fpga
model/OP5600+ML605
50*6
2 terminals
48*6 AO, 96*6 D
3200 IO in total
25 microsI
Hardware-in-the-loop test
Nari-Relays (NR)
phase 2
China 2013
MMC fpga model/
10 VIRTEX7 OP7020
250*6
5 terminals
Aurora/Gigabit
HIL Simulation of a 5-terminal
MMC HVDC project
XJ Group phase 1 China 2013 MMC controller/OP7020
5 terminals
IO Rapid Control Prototyping (RCP)
State Power Economic
Research Institute
(SPERI)
China 2013
MMC controller/OP7020
10 VIRTEX7 OP7020 5 terminals
Aurora
HIL Simulation of a 5-terminal
MMC HVDC project
6. 6
Introduction to MMC
67
Cells output can either be the capacitor voltage or zero. The sum of all the cells from 1
arm equals two times the HVDC bus, at any given time there is only half of the cell with
there capacitor voltage at there output.
7. 7
Introduction to Modular Multilevel Converter (MMC)
78
Two Basic Cell Topologies for High-Power Converters
Half-Bridge
- Most popular
- Difficulties to eliminate DC-bus fault
Full-Bridge
- More losses
- Bus capable to eliminate DC-buss faultVcap
+
-
Vab
+
-
A
B
ISM
T1
T2
T3
T4
8. 8
Introduction to Modular Multilevel Converter (MMC)
89
Advantages and Disadvantages vs Traditional Thyristor-based converters
Advantages
- Reduced stress on converter and grid component
- Redundancy of the model increases its reliability
- VSC allows easier power flow control
- Very fast recovery on fault to stabilize power grids
- Can feed loads without any generators (no limit on short-
circuit ratio)
- Easy and start-up
- Smaller foot print
- No filters
Disadvantages
- Requires more components
- Control more complex
- Limited power capability
9. 9
Challenges of MMC in HIL
- Model computation
910
Equations for each
- Reactive component (state-space solver).
- Node (Nodal approach)
Equations need to be recomputed at each switching instant
1 cell == 1 state or 2 nodes
1 arm == 100 cells == 102 states or 201 nodes
3 arms == 300 cells == 306 states or 603 nodes
10. 10
Challenges of MMC in HIL
- IO management
1011
For a small converter
IO requirements
1 cell :
- 2 digital inputs
- 1 Analog output
300 cells
- 600 digital inputs
- 300 analog outputs
Can be replaced by high
speed optical IO
11. 11
Challenges of MMC in HIL
- IO management
1112
For a small converter
25µs 50µs0 µs
t
Inputs
Model
Calc.
Outputs
RCP: Converter measurement
HIL: Gating signal
RCP: Control law
HIL: Real-time simulation
RCP: Gating signal
HIL: Converter measurement
500ns 1µs0 ns
t
12. 12
Demo System
12
Description of Parameters Value
Grid frequency and voltage 50 Hz, 230 kV
Transformer power rating 280 MVA
Transformer voltage ratio 230 kV / 100 kV
Transformer impedance 10%
Arm Impedance 24 mH
MMC power rating 200 MVA
Number of SM per valve in MMC 250
SM capacitance 24 mF
DC link Voltage ± 100 kV
13
13. 13
13
MMC FPGA model
MMC valve control
Voltage balancing control
+ gating signal generation
MMC
255*6 SM
Selectork1
Gating
Signals
to MMC
FPGA
Protocol drive (or IO drive)
Selector k2
Gating
Signals
from CPU
Gating signals by
valve control
SPF or IO
Reference
from CPU
Gating signals
to protocol
Target
Gating signals
from protocol
Selectork3
Capacitor voltage
Capacitor Voltage
from Protocol
MMC & system
Measurements
14
14. 14
14
Fiber optic
Gating signals
by valve
control
Gating
Signals
to MMC
MMC valve
control
MMC
Selectork1
FPGA 1
Protocol drive
Selector k2
Gating
Signals
from CPU
SPF
Reference
from CPU
Gating signals
to protocol
Gating signals
from protocol
Selectork3
Capacitor voltage
Capacitor Voltage
from Protocol
MMC
Sys.
Meas.
Gating
Signals
to MMC
MMC valve
control MMC
Selectork1
FPGA 2
Protocol drive
Selector k2
Gating
Signals
from CPU
Gating signals
by valve
control
SPF
Reference
from CPU
Gating signals
to protocol
Gating
signals
from protocol
Selectork3
Capacitor voltage
Capacitor Voltage
from Protocol
MMC
Sys.
Meas.
GridPole ctrlTarget 1 Target 2I/O I/O
Copper wiring
Simulating MMC in FPGA (External Control)
15
15. 15
15
Simulating MMC in FPGA (External Control)
Fiber optic
Gating signals
by valve
control
Gating
Signals
to MMC
MMC valve
control
MMC
Selectork1
FPGA 1
Protocol drive
Selector k2
Gating
Signals
from CPU
SPF
Reference
from CPU
Gating signals
to protocol
Gating signals
from protocol
Selectork3
Capacitor voltage
Capacitor Voltage
from Protocol
MMC
Sys.
Meas.
Gating
Signals
to MMC
MMC valve
control MMC
Selectork1
FPGA 2
Protocol drive
Selector k2
Gating
Signals
from CPU
Gating signals
by valve
control
SPF
Reference
from CPU
Gating signals
to protocol
Gating
signals
from protocol
Selectork3
Capacitor voltage
Capacitor Voltage
from Protocol
MMC
Sys.
Meas.
GridPole ctrlTarget 1 Target 2I/O I/O
Copper wiring
16
17. 17
MMC HIL and RCP and its applications
1718
Real-Time or faster than real-time MMC simulation for:
• Concept validation – Grid and Converters
• Control/protection system design and optimisation
• Stress analysis on power grid and converter components (arrestor sizing etc.)
• Monte carlo analysis
• Research work
• Academic application
18. 18
MMC HIL and RCP and its applications
1819
• Rapidly build a demonstration prototype
• Validate control algorithms
• MMC model validation
• De-risk control design
• Detect design faults
Rapid control prototyping with physical plant
RCP MMC real-time simulation to:
19. 19
MMC HIL and RCP and its applications
1920
• Controller validation
• Validate destructive test sequence without damaging physical material
• Control research and development in laboratory environment
• Controller production verification
Hardware-in-the-loop
HIL MMC real-time simulation connected to control system replica for:
20. 20
MMC Typical HIL Configuration
• Capable of simulating up to 1500 MMC
sub-modules
• Supports 16 SFP and SFP+
transceivers multi-mode fiber modules
• 20-Gbits/s PCI Express x4 links to
interface with any OPAL-RT real-time
simulator
OP7020
Virtex 7 FPGA Processor Expansion Unit
0
21
21. 21
MMC Typical HIL Configuration
• Capable of simulating up to 1500 MMC
sub-modules
• Supports 16 SFP and SFP+
transceivers multi-mode fiber modules.
• 20-Gbits/s PCI Express x4 links to
interface with any OPAL-RT real-time
simulator
• Up to 8 signal conditioning & A/D
converter modules with 16 or 32
channels each
OP5607
Virtex 7 FPGA Processor & I/O Expansion Unit
0
22
22. 22
Key Benefits and Features
• MMC FPGA models include up to 511 submodules per valve, 6
valves per FPGA, and run at 500ns
• MMC FPGA modules include features such as: cells short-circuit
fault, AC fault and DC fault
• FPGA model can also be coupled directly with SFP optical fiber
(Small Form-factor Pluggable)
• Total bandwidth selectable between 1 and 5 Gbits/s
• Minimum latency of 250 ns
• Total update time with actual controller smaller than 4 micros
with more than 511 sub modules per optical fiber pairs
• HIL system architecture allow easy I/O expansion
• OPAL-RT MMC open protocol using Aurora or Gbit Ethernet
• Possibility to implement custom protocol
23
23. Modeling of Modular Multilevel Converters for the France-Spain link
Sébastien Dennetière (RTE)
24. INELFE project: France-Spain ELectrical INterconnection
Santa
Llogaia
Baixas
A 2000 MW - 65 km underground cable – DC link connecting Baixas
(near Perpignan, France) and Santa Llogaia (near Figueras, Spain)
Santa Llogaia
Baixas
Tunnel
Modeling of Modular Multilevel Converters for the France-Spain link24
25. Scope of the project
Rated power: 2*1000 MW
DC voltage: ±320 kV for each 1000MW link
Reactive Power Control: +/- 300 MVAR for each
1000MW Converter
Converter Contractor : Siemens
DC cable length: 64 km
Cable Contractor: Prysmian
8 km dedicated Tunnel
Commissioning date: 2015
Cost of the Project : 700M€
with 225M€ financing from EU
GAUDIERE
BAIXAS
VIC
RIUDARENES
BESCANO
SANTA
LLOGAIA
RAMIS
FRANCE
SPAIN
HVDC
LINK1
HVDC
LINK2
+
-
+
-
BAIXAS
SANTA
LLOGAIA
Modeling of Modular Multilevel Converters for the France-Spain link25
26. Modeling of MMC for Rte
INELFE is the first VSC installation operated and maintained by RTE
Many HVDC projects in the future on the French grid…
Competences in modeling and simulation of VSC based equipment were
required in RTE
Manufacturers models are black box and are provided at the end of the
project
Collaborations with Ecole Polytechnique de Montréal (CA)
and Ecole Centrale de Lille (FR) to develop generic MMC models
for EMT studies
Modeling of Modular Multilevel Converters for the France-Spain link26
27. VSC MMC topology for INELFE
SM
1
SM
2
SM
n
SM
1
SM
2
SM
n
SM
1
SM
2
SM
n
SM
1
SM
2
SM
n
SM
1
SM
2
SM
n
SM
1
SM
2
SM
n
3
2
6
+320kV
-320 kV
4
56
2
3
4
5
Insertion resistors
Star point reactor
Arm reactor
Multi-valve arm
Converter transformer
1
1 Submodule
S1
S2
C ~400 SM
Detailed modeling of such converters is very
challenging :
improve numerical techniques
develop simplified models
Modeling of Modular Multilevel Converters for the France-Spain link27
28. Modeling of Modular Multilevel Converters for the France-Spain link
Type of Converter models
Description from converter topologies to semi conductors
Full detailed models – model1
28
Id
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
Vd
Ls
LsLsLs
Ls Ls
Sub-
Module
Multi-
valve
Arm
iua
ib
ic
vc
iub iuc
ila ilb ilc
vsua
vb
ia
va
vsla
p
n
g
S1
S2
C
K2K1
0 1000 2000 3000 4000 5000 6000
0
0.2
0.4
0.6
0.8
1
Current (A)
Voltage(V)
+
n
p
g
Simulation time for a 1s simulation in EMTP-RV ~ 3.5h (t=10µs)
29. Detailed equivalent models
Id
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
SM-1
SM-2
SM-400
:
Vd
Ls
LsLsLs
Ls Ls
Sub-
Module
Multi-
valve
Arm
iua
ib
ic
vc
iub iuc
ila ilb ilc
vsua
vb
ia
va
vsla
SMv t
MVi t
_SM eqr t
_SM eqv t T
++
_1
_1
SM
eq
v t
r t
_ 2
_ 2
SM
eq
v t
r t
_3
_3
SM
eq
v t
r t
_4
_4
SM
eq
v t
r t
_5
_5
SM
eq
v t
r t
_6
_6
SM
eq
v t
r t
_6eqr t
_5eqr t
_4eqr t
_3eqr t
_2eqr t
_1eqr t
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
DC_PLUS
DC_MINUS
a
b
c
AC
A solution to limit number of internal nodes – model2
Simulation time for a 1s simulation in EMTP-RV ~7.5min (t=10µs)
Modeling of Modular Multilevel Converters for the France-Spain link29
30. Models validation – comparison against full detailed model
3-phase AC fault
Saad, H.; Dennetière, S.; Mahseredjian, J.; Delarue, P.; Guillaud, X.; Peralta, J.; Nguefeu, S.,
"Modular Multilevel Converter Models for Electromagnetic Transients," IEEE Transactions on Power Delivery, Nov 2013
Modeling of Modular Multilevel Converters for the France-Spain link30
0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
-1.5
-1
-0.5
0
0.5current(pu)
time (s)
0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
0.95
1
1.05
1.1
1.15
voltage(pu)
time (s)
Model 4
Model 1, 2 and 3
Model 4
Model 1 and 2 Model 3
0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
-1.5
-1
-0.5
0
0.5
current(pu)
time (s)
0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
0.95
1
1.05
1.1
1.15
voltage(pu)
time (s)
Model 4
Model 1, 2 and 3
Model 4
Model 3
Model 1 and 2
1.85 1.9 1.95 2
-5
0
5
current(pu)
time (s)
1.85 1.9 1.95 2
0
5
10
current(pu)
time (s)
Model 4
Model 1, 2 and 3
Model 1, 2 and 3
Model 4
Zoomed
1.898 1.9 1.902 1.904 1.906
0
2
4
6
8
current(pu)
time (s)
2
4
6
8
current(pu)
Model 1, 2 and 3
Model 4
DC pole-to-pole fault
DC voltage and current
DC current
31. Conclusions
Generic models to have a better understanding of MMC
MMC models for EMT studies during and after the project
Models presently available in EMTP-RV – based on generic control
systems and validated against results given by manufacturers
Next steps
Models suitable for Real-time simulation and connected to control
system replica collaboration with OPAL-RT and Hydro-Québec to
develop very accurate MMC models for real-time simulation
Studies with control system replica connected to Hypersim real-time
simulator to test dynamic performances
to validate and maintain offline models
to perform HVDC studies
Modeling of Modular Multilevel Converters for the France-Spain link31
32. 32
VISION MMC : Accuracy and Flexibility
Better Model Accuracy and Flexibility (2014Q2)
• All arm inductors and transformer leakage inductors simulated
with a time step of 500 nanos or lower on FPGA chips
• Better accuracy during special pulse blocking conditions
• Better accuracy during natural rectification mode
• Better accuracy of fault transients on the converter side
• Better arrestor simulation (MMC side and DC bus arrestors)
• Easier to simulate complex back-to-back converters
Better Model Accuracy (2014Q4)
• Transformer saturation effect simulated at 500 ns
• Frequency dependent line and cable models simulated at 1 µs
24
33. 33
VISION MMC : Lower Cost
To provide smaller but powerful MMC simulators for R&D,
initial design and teaching
Fast/real-time simulation:
• HYPERSIM – 50 3-phase busses on 2 INTEL core
(20 to 50 us)
• High-Level MMC SIMULINK Controller on 1 Intel core
• Low-Level Cell controller on FPGA
• Up to 1500 MMC cells on one KINTEX 7 FPGA
(500 ns)
• Controller and MMC cell signal are interfaced inside the
FPGA chip (no external IO)
25
34. 34
VISION MMC : Lower Cost
To provide smaller but powerful MMC simulators for R&D,
initial design and teaching
Real-time simulation of the grid and MMC converters
• HYPERSIM – 50 3-phase buses on 2 INTEL core
• MMC SIMULINK Controller on 1 Intel core
• Up to 1500 MMC cells on one KINTEX 7 FPGA
MMC Control Prototyping System
• High-Level MMC SIMULINK Controller on 1 to 3 Intel cores
• Low-level MMC controller on one KINTEX 7 FPGA
• Can include all control and protection functions used in
industrial MMC controllers
• Some MMC manufacturers already use the same architecture
(INTEL + KINTEX7 FPGA)
26
35. 35
VISION MMC : Lower Cost
To provide smaller but powerful MMC simulators for R&D,
initial design and teaching
OP4500
optical fibers
(up to 4 SFP)
MMC Control Prototyping System
• High-Level MMC SIMULINK Controller on 1 to 3 Intel cores
• Low-level MMC controller on one KINTEX 7 FPGA
• Can include all control and protection functions used in industrial MMC
controllers
• Some MMC manufacturers already use the same architecture (INTEL +
KINTEX7 FPGA)
PHYSICAL
SET UP AND PHIL (Grid and
MMC)
27
36. 36
ACTUAL: Integrated Power Electronic LAB
EXT CNTR
Bench 1
Bench 2
Bench 3
Bench 4
5-Gbits optical fiber pair
Standard PCs
(12, 24 cores or 32 cores)
PCI Express 4x
University Sheffield UK
(delivery April 2014)
Bench 5
OP5607
Virtex 7 FPGA Processor & I/O Expansion Unit
28
37. 37
CONCLUSION
• OPAL-RT TECHNOLOGIES established a global leadership on
MMC HIL and RCP solutions over the last three years.
• OPAL-RT TECHNOLOGIES is in active discussion for future MMC
projects over 5 continents.
• OPAL-RT TECHNOLOGIES provides specific MMC hardware and
software expertise as well as service from experienced
engineers.
29
38. 38
OPAL-RT’S UPCOMING EVENTS
Montreal | June 9 – 12, 2014
• Call for Paper deadline extended - See topics
http://www.opal-rt.com/realtime2014/registration/call-for-papers/
• Conference Registration: http://www.opal-rt.com/realtime2014/registration/
IEEE PES T&D in Chicago | April 14-17, 2014
• Visit OPAL-RT at Booth 9123
More info at http://www.opal-rt.com/Events
30
39. 39
Thank you for your attention
This presentation will be available shortly on www.opal-rt.com
31