FPGA simulation provides high-fidelity models for hardware-in-the-loop testing of electric machines and power electronics. It allows control algorithms to be tested with highly resolved non-ideal behaviors faster and at lower cost compared to physical testing. The document discusses how eFPGAsim utilizes FPGA technologies to simulate electric drive systems with models exported from finite element analysis, improving collaboration between design and control engineers.
E.ON Energy Research Center builds first interface between OPAL-RT and RTDS Technologies real-time simulators, opens new collaborative research opportunities
The OP1200, Lab-Scale Modular Multilevel Converters Test Bench, is dedicated to the hardware verification of new control algorithms for new and existing power electronic converter topologies. It is used for experimental work on converter interactions and network control.
E.ON Energy Research Center builds first interface between OPAL-RT and RTDS Technologies real-time simulators, opens new collaborative research opportunities
The OP1200, Lab-Scale Modular Multilevel Converters Test Bench, is dedicated to the hardware verification of new control algorithms for new and existing power electronic converter topologies. It is used for experimental work on converter interactions and network control.
In this webinar, learn about common cybersecurity threats and the crucial role played by real-time digital simulation in the reinforcement of cybersecurity in power systems.
In this webinar, learn about common cybersecurity threats and the crucial role played by real-time digital simulation in the reinforcement of cybersecurity in power systems.
In this webinar, learn how OPAL-RT's state-of-the-art Hardware-in-the-Loop (HIL) simulation solutions empower engineers to design and test ECUs, and other integrated power electronic systems and controllers, with efficiency.
Performance improvement of parallel active power filters using droop control ...Ghazal Falahi
In this paper, a new method based on droop control scheme is proposed for controlling parallel operation of active filters. The harmonic components of the load current are extracted by an enhanced phase-locked loop (EPLL). In the parallel group, each filter operates as a conductance and the harmonic workload is shared among them. A droop relationship between the conductance and non-fundamental apparent power controls the operation of each unit. The non-fundamental apparent power has been calculated based on IEEE Std 1459. Principles of operation are explained in this paper and simulation results which are presented approve the effectiveness of this method. The results indicate a significant reduction in Total Harmonic Distortion (THD) in a rectifier application.
How to achieve 95%+ Accurate power measurement during architecture exploration? Deepak Shankar
During the conceptualization and architectural exploration phases, it is crucial to assess the power budget.
Would you like to accurately measure the:
1. Power consumed for a proposed embedded software or firmware?
2. Savings of a Power Management Algorithm prior to development?
3. Power impact of hardware configuration change?
4. Trade-off between Power and Performance?
5. Temperature, heat, peak power and cumulative power?
OPAL-RT Distributed Multi-User LaboratoriesDarcy La Ronde
Learn more about OPAL-RT's high-performance distributed multi-user real-time HIL laboratories, part of our Academic and Research offering, optimized to conduct several HIL projects in parallel.
PMU-Based Real-Time Damping Control System Software and Hardware Architecture...Luigi Vanfretti
Poster Presentation at the IEEE PES General Meeting. Low-frequency, electromechanically induced, inter- area oscillations are of concern in the continued stability of inter- connected power systems. Wide Area Monitoring, Protection and Control (WAMPAC) systems based on wide-area measurements such as synchrophasor (C37.118) data can be exploited to address the inter-area oscillation problem. This work develops a hardware prototype of a synchrophasor-based oscillation damping control system. A Compact Reconfigurable Input Output (cRIO) con- troller from National Instruments is used to implement the real- time prototype. This paper presents the design process followed for the development of the software architecture. The design method followed a three step process of design proposal, design refinement and finally attempted implementation. The goals of the design, the challenges faced and the refinements necessary are presented. The design implemented is tested and validated on OPAL-RT’s eMEGASIM real-time simulation platform and a brief discussion of the experimental results is included.
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POLYTEDA LLC, a provider of semiconductor design software and PV-services announced the general availability of PowerDRC/LVS version 2.2.
This release is dedicated to delivering fill layer generation for multi-CPU mode, new KLayout integration functionality and other significant improvements for multi-CPU mode
We build AI and HPC solutions. Expertise: highly optimized AI Engines and HPC Apps.
• HPC: accelerating time to results and adapting complex algorithms to GPU, FPGA, many-CPU architectures.
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Detailed large-scale real-time HYPERSIM EMT simulation for transient stabilit...OPAL-RT TECHNOLOGIES
Towards cloud-based real-time HIL for wide-area special control and protection system testing
Presented by: Jean Belanger, President and CTO of OPAL-RT TECHNOLOGIES
Abstract: High penetration of inverter-based Distributed Energy Resources (DERs), widespread installation of FACTS and HVDC interconnection systems, and the decommissioning of thermal and nuclear plants are significantly reducing inertia in large-scale power systems. Fast power-electronics based control and protection schemes act to stabilize these systems, but they are sensitive to harmonics, transients, and system imbalances. It has been shown that simplified positive-sequence RMS models alone are insufficient for Transient Stability Assessment (TSA) of large-scale, low-inertia power grids. Therefore, utilities and regulators such as NERC, as well as professional associations such as CIGRE and IEEE, have begun investigating detailed EMT simulation to assess the transient stability of large-scale, low-inertia power grids that include power-electronic plant controllers.
However, detailed EMT simulation of large-scale power grids for 20 to 30 second time-frames and hundreds of contingencies presents a number of computational and analytic challenges including excessive simulation time, large-scale grid data management and the unavailability of detailed and validated models of power-electronic plant controllers. Furthermore, these plant controllers, if they are provided by OEMs, are in the form of blackbox, pre-compiled DLLs, which are implemented for specific simulation tools, without any interoperability standard.
This presentation will describe OPAL-RT solutions to achieve very large-scale, detailed grid EMT simulation in real-time for Hardware-in-the-Loop (HIL) / Software-in-the-Loop (SIL) control and protection testing, as well as quasi-real-time simulation for fast TSA evaluation of large-scale, low-inertia power systems. With these solutions, blackboxcontrol and protection systems can be implemented natively in the EMT simulation tool, HYPERSIM. PSCAD DLLs can also be co-simulated with HYPERSIM using a software interface based on the CIGRE model-interoperability guidelines.
Such advances will accelerate connection studies and can be used to implement cloud-native tools to help operators assess system stability with hundreds of contingencies in 5-to 10-minute time-frames. This performance can be achieved for grids having several thousand busses with a 50-microsecond time-step using a few hundred processors.
As HYPERSIM runs under Windows or LINUX, powerful cloud-based applications can be implemented for TSA and to test wide area control and protection systems using SIL or HIL with real control and protection software and hardware. Communication system emulators, such as eXata can also be used to analyze cyber-attacks and countermeasures as well as to evaluate the effect of communication failures and delays on system performance.
Learn more at www.opal-rt.com
This presentation explores the real-time simulator as a platform for severe accident simulation and how it can be used to address post-Fukushima challenges in the nuclear energy industry. Presented at ANS PSA International Topical Meeting. For more information, go to GSES.com and follow GSE Systems on Twitter @GSESystems and Facebook.com/GSESystems. Thanks for viewing!
Similar to RT15 Berkeley | Introduction to FPGA Power Electronic & Electric Machine real-time simulation for HIL-OPAL-RT (20)
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Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
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2. 2
- Turnkey HIL Simulation Solutions (~20 minutes)
- Why organizations use HIL for power electronics & machine development & testing today
- Where we are today - Where are we going?
- "Signal Level" HIL versus "Power HIL"
- Workflow improvements: From e-Machine Specialists to Controls & testing Engineers
- CPU vs. FPGA based simulation
- Using FEA to accelerate machine design as well as controls testing & validation with HIL
- eFPGASim as a development & test tool
- eHS: The flexible solution for power electronics development & test in real-time
Agenda
3. 3
Our solutions cover the complete spectrum of power system analysis and studies
ePHASORsim
Real-Time Transient
Stability Simulator
10 ms time step
HYPERsim
Large Scale Power System
Simulation for Utilities & Manufacturers
25 µs to 100 µs time step
eFPGAsim
Power Electronics Simulation on FPGA
1 µs to 100 ns time step
1 s
(1 Hz)
10,000
2,000
1,000
500
100
10
0
10 ms
(100 Hz)
50 µs
(20 KHz)
10 µs
(100 KHz)
1µs
(1 MHz)
100 ns
(10 MHz)
10 ns
(100 MHz)
20,000
Period (frequency) of transient phenomena simulated
Number of
3-Phase
Buses
eMEGAsim
Power System & Power Electronics Simulation
Based on Matlab/Simulink and SimPowerSystems
10 µs to 100 µs time step
Alan’s Subject
OPAL-RT Solutions …. again
4. 44
The Challenge of Electric Motor & Power Electronics
Control Testing
Control engineers want :
To test the motor controller with non-ideal behavior.
To test the motor controller with different points of operation,
such a saturated states
To insert fault conditions
To rapidly simulate different types of motors and power
electronics topologies
High-fidelity and flexible Drive & PE simulation
5. 55
The Challenge of Electric Motor Control Testing 2
• increase test case coverage
• reduce costs
• accelerate time to market
By reducing testing time on real dynamometer
• How “real” can HIL get?
By detecting errors at earlier stages of the design
Faster improvement of complex control strategies
Managers want to:
Creation of a technical link between Designer
and control engineer – HIL model IS the design
6. 6
Model-based Design (MBD) &
Hardware-in-the-Loop (HIL)
Validate
Model
Off-line simulation
Virtual Prototype
HIL, RT simulation
3D visualization
Control Prototype
HIL, RT simulation,
Physical Components
Design
Implementation
Production Code
Physical Components
Lab Testing
with actual
controller
Integration & Test
In-system commiss-
ioning & calibration
Deployment
Production
Maintenance
This implementation is
performed by the
software team
This implementation is
performed by the
control team
This implementation
is performed by the
integration team
Models become the method to share
information with disparate
development teams
HIL
“AVOID REDUNDANT
MODEL DEVELOPMENT!”
7. 7
General eFPGAsim structure
• eFPGAsim is a suite of FPGA models and solvers
• All models/solvers uses floating point format
• Designed for full connectivity of models within a fixed
bitstream on Virtex-7
8. 8
eHS: ‘Electric Hardware Solver’
• Automated Electric Circuit Solver
• Variable topology, variable parameter, ‘non-flashing’
• Enable the simulation of switched electric circuits on
FPGA directly from a SimPowerSystems/PLECS/PSIM
model
9. 9
• Fixed Admittance Matrix Nodal Method
• All switches in the circuit:
• Modeled as a capacitor when open
• Modeled as an inductor when closed
• If L/h=h/C then the admittance matrix is constant
(For backward Euler method, h is the time step)
Automated Nodal Electric Circuit Solver
eHS: ‘Electric Hardware Solver’
10. 10
eHS example: Matrix Converter Drive
10
- 22 switches in total in the converter
- Connected to PMSM on the FPGA
- Calculation time on FPGA : 590 ns on eHS-16
(estimated timing on eHS-64: 350 ns)
11. 11
• FPGA structure based on optimized dot-product units
and operation scheduler
Automated Nodal Electric Circuit Solver
eHS: ‘Electric Hardware Solver’
eHS characteristics
Virtex-6
(eHS-16)
Virtex-7
(eHS-64)
Inputs 16 32
Outputs 16 32
Switches 24 64
Max # eHS
Core
2 2
Cycle time 150 ns - 1 µs 150 ns - 1 µs
eHS-16 configuration
12. 12
Why FPGA simulation?
• Low sampling time and therefore excellent resolution
for high frequency IGBT gating (up to 50-100 kHz)
• Excellent latency (typ. 1 µs) for direct current-control
motor applications or FODP (Fast On-board Drive Protection)
• Massively parallel pre-processing unit for CPU
• very good example: MMC (Multi-Level Modular Converter)
ALU cores
I/Os
DUT
(controller)
Logic & mem
CPU FPGA
PCIe bus
FOBP
13. 13
Disadvantages of FPGA simulation
• Higher coding complexity than CPU counterparts.
• User has more control over lower level abstraction levels but this
increases the complexity of the designs
• Many basic CPU coding schemes must be verbosely expressed in
the FPGA design, which can be cumbersome. Ex: ‘for’ loops in
matrix multiplications.
• Very long compilation time
• Generating a new FPGA bitstream from FPGA code can take 1-2
hours on big FPGA chips like Virtex-6 or Virtex-7
• Increased debugging/probing difficulty
eFPGAsim is designed to avoid these problems
14. 1414
HIL for ECU Testing and Validation
Virtual Plant
Machines, PE,
Peripherals
Electronic Control Unit (ECU) Under Test
15. 1515
Role of FPGA in HIL Simulation
CPU
I/Os
ECU
(controller)
Logic & mem
TARGET-PC FPGA
PCIe link
BASIC HIL SIMULATOR
Gates Signals
Probes Feedback
Feedback Latency: 1.5us
Feedback Latency: 40us
16. 1616
Example: PMSM Solver on FPGA
Performance Recap:
Step Time :
15-60us
Model total Latency:
20-100us
Step Time :
100-450ns
Model total Latency:
Bellow 2.5us
FEA PMSM Solver OPAL-RT PMSM FPGA Solver
17. 17
• Plant model exported from FEA, is integrated with I/O & any peripheral plant model
components in Simulink to be compiled for real-time.
• Xilinx System Generator is a FPGA Simulink blockset
• No need to know VHDL language
• User can customize the I/O for complex applications
RT-LAB I/O is fully programmable with Xilinx System Generator
A typical XSG model in RT-LAB
18. 18
Example eFPGAsim configuration (1)
Dual-PMSM +boost (Prius configuration)
• Common drive configuration used on the Prius, Ford
Fusion Hybrid and Denso supplier.
• PMSM Finite-Element Model (JMAG-RT/Infolytica)
M. Harakawa, C. Dufour, S. Nishimura, T.Nagano, “Real-Time Simulation of a PMSM Drive in Faulty Modes
with Validation Against an Actual Drive System”, Proceedings of the 13th European Conference on Power
Electronics and Applications (EPE-2009), Barcelona, Spain, Sept. 8-10, 2009
Validation of JMAG-PMSM model against real motor
19. 19
Example eFPGAsim configuration(2)
SRM + H-bridge buck-boost
• Switched Reluctance Motors offer an alternative to highly
priced rare-earth magnets of PMSM.
• FEA data of SRM imported from JMAG (JSOL) or
MotorSolve (Infolytica)
(3-phase shown)
L-1
(,iabc)
rotor
FPGA
(Virtex 6)
Digital Input
(5 ns) (IGBT
gates)
Multi-core CPU
(Intel Core i7)
Internal test
modulators
DC-DC PWM
10-100 kHz
SRM Drive
Analog
Output
(currents)
Analog
Output
(resolver)
Digital
Output
(quad enc)
I/Os &
sig. cond.
Analog Input
(resolver
excitation)
High-Level Mechanical system
(modeled in Simulink and RTW)
MasterECU
Battery
voltage
H-bridge
Buck-Boost converter
SG User
designed I/O
ECUundertest
CAN
(6/4 SRM shown)
SRM Motor
SRM Flux Data
Labc
SRM controller
(hysterisis current type)
SRM Torque Data
iabc
FPGA
(Virtex 6)
C. Dufour, S. Cense, J. Bélanger, “FPGA-based Switched Reluctance Motor Drive and DC-DC Converter
Models for High-Bandwidth HIL Real-Time Simulator”, Proceedings of the 15th European Conference on
Power Electronics and Applications (EPE’13 ECCE Europe), Lille, France, Sept. 3-5, 2013
SRM FEA analysis from MotorSolve
20. 20
Example eFPGAsim configuration(3)
Induction Motor Drive
• Linear induction motor
• Model with fixed DQ
frame.
• Mechanical model and
feeder grid circuit can
be interfaced on regular
CPUs of RT-LAB
C. Dufour, S. Cense, J. Bélanger, “ An Induction Machine and Power Electronic Test System
on FPGA”, ELECTRIMACS 2014 conference, Valencia, Spain, May 19th -22nd, 2014.
21. 21
Offline results (SPS) On-line results (Virtex-6 on-chip)
IM-FPGA test: 6-pulse mode, 1225 rpm
Test #1
PWM frequency 680 Hz
Modulation Null
6-pulse mode
Motor speed 1125 RPM
Slip 0.0625
Case from: C. Dufour, S. Abourida, J. Bélanger, “Real-Time Simulation of Electrical Vehicle Motor Drives on a PC Cluster”,
Proceedings of the 10th European Conference on Power Electronics and Applications (EPE 2003), Toulouse, September 2-4 2003.
22. 22
PMSM models: DQ, VDQ and SH
N
Siabc
rotor
PMSM
rotor
idqref
iabc idq (ref)
(Park transform)
(hysteresis switching)
+
- iabc(ref)
IGBT
inverterVdc
When the motor starts to saturate:
• DQ model: produces higher torque than normal
• VDQ (DQ with variable Ld Lq): has the correct average torque
• Spatial Harmonic (SH) : more precise with cogging torque and
slot-induced inductance torque variation
This test in current control mode shows
the different torque levels produced for
the SAME current!
23. 2323
Next step: Power HIL versus Signal Level HIL Simulation
PHIL simulation is a scenario where a simulation environment
virtually exchanges power with real hardware, in contrast to cases
which involves only low-power signal exchange.
Power Hardware-In-the-Loop
24. 2424
Power HIL: Why, How, Where?
• Join the real-time simulator capabilities to the power
equipment
• Power systems, power electronic, protection equipement,
controller logic, etc.
• Requires high quality amplifier
• High accuracy, low distorsion, high bandwith, low phase lag,
etc.
• Connect a real power device under test
• Wind turbine, solar panel, motors/generators, protection
relays, gate drives, etc.
• $ trade-off
26. 2626
Summary 1
FPGA is now the default solution for HIL testing
High-fidelity HIL model on FPGA is finally a reality
Large scale parametric analysis of (example) Prius Motor was done to
prepare data for Opal-RT software using ANSYS FEA software
Enhanced control algorithm validation is now possible on HIL
Faster tests, simplified workflow, lower cost
Motor and controller designer can work closely together – The
exported FEA model (Design) IS the HIL plant model
27. 27
Summary 2
• eFPGAsim is designed to ease the use of FPGA technologies for
motor drive and power electronic HIL testing
• avoid very long ‘Place And Route’ time of modern, large FPGAs.
• non-flashing, variable parameter and variable topology methodology
• Available motor models as of today: PMSM, SRM, IM . . .
• eHS can be used to build exotic power converter topologies
eFPGAsim is a useful tool to
increase test coverage of motor
drive and power electronics
systems in early stage of
development and reduce overall
project costs
…. Time for a quick Demo!
Req. Design Implement ValidationRateofdefectdiscovery
OldNew
The later the detection, the more expensive the correction