Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.
High functionality reversible arithmetic logic unitIJECEIAES
Energy loss is a big challenge in digital logic design primarily due to impending end of Moore‟s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17% reduction in garbage lines, 92% reduction in ancillary lines and 53% reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.
An optimised multi value logic cell design with new architecture of many val...IJMER
Propose thesis work is a design of a Multi Logic Memory cell of four logic levels which can hold Logic 0, Logic 1, Logic 2 & Logic 3 and also propose an Interface module design between multi logic system with binary systems, thesis work can reduce the no. of wires required to parallel interface with normal memory and also can increase the speed of simple serial data transfer
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adderijtsrd
Reversible circuits are one promising direction withapplications in the field of low-power design or quantumcomputation. However, no real design flow for this new kind ofcircuits exists so far. Significant contributions have been madein the literature towards the design of reversible logic gatestructures and arithmetic units, however, there are not manyefforts directed towards the design of reversible ALUs. In thispaper, a novel programmable reversible Kogge-Stone adder ispresented and verified, and its implementation in the design ofa reversible Arithmetic Logic Unit is demonstrated. Then,reversible implementations of ripple-carry, Kogge-Stone carrylook-ahead adders are analyzed and compared in terms ofdelay. The proposed design consists of the reversible Fredkin,Feynman, MG, HNG, PG and RKSC gates. The performancecharacteristics analysis is carried out in Xilinx environment. Swetha Potharla | Rajkumar R"A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-6 , October 2017, URL: http://www.ijtsrd.com/papers/ijtsrd5758.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/5758/a-novel-design-of-a-4-bit-reversible-alu-using--kogge-stone-adder/swetha-potharla
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
High functionality reversible arithmetic logic unitIJECEIAES
Energy loss is a big challenge in digital logic design primarily due to impending end of Moore‟s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17% reduction in garbage lines, 92% reduction in ancillary lines and 53% reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.
An optimised multi value logic cell design with new architecture of many val...IJMER
Propose thesis work is a design of a Multi Logic Memory cell of four logic levels which can hold Logic 0, Logic 1, Logic 2 & Logic 3 and also propose an Interface module design between multi logic system with binary systems, thesis work can reduce the no. of wires required to parallel interface with normal memory and also can increase the speed of simple serial data transfer
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adderijtsrd
Reversible circuits are one promising direction withapplications in the field of low-power design or quantumcomputation. However, no real design flow for this new kind ofcircuits exists so far. Significant contributions have been madein the literature towards the design of reversible logic gatestructures and arithmetic units, however, there are not manyefforts directed towards the design of reversible ALUs. In thispaper, a novel programmable reversible Kogge-Stone adder ispresented and verified, and its implementation in the design ofa reversible Arithmetic Logic Unit is demonstrated. Then,reversible implementations of ripple-carry, Kogge-Stone carrylook-ahead adders are analyzed and compared in terms ofdelay. The proposed design consists of the reversible Fredkin,Feynman, MG, HNG, PG and RKSC gates. The performancecharacteristics analysis is carried out in Xilinx environment. Swetha Potharla | Rajkumar R"A Novel Design of a 4 Bit Reversible ALU using Kogge-Stone Adder" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-1 | Issue-6 , October 2017, URL: http://www.ijtsrd.com/papers/ijtsrd5758.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/5758/a-novel-design-of-a-4-bit-reversible-alu-using--kogge-stone-adder/swetha-potharla
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Presented in this short document is a description of what we call "Advanced" Property Tracking or Tracing (APT). APT is the term given to the technique of predicting, simulating, calculating or estimating the properties (i.e., densities, compositions, conditions, qualities, etc.) in a network or superstructure with significant inventory using statistical data reconciliation and regression (DRR)
Presented in this short document is a description of modeling and solving partial differential equations (PDE’s) in both the temporal and spatial dimensions using IMPL. The sample PDE problem is taken from Cutlip and Shacham (1999 and 2014) and models the process of unsteady-state heat transfer or conduction in a one dimensional (1D) slab with one face insulated and constant thermal conductivity as discussed by Geankoplis (1993).
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,paperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Analysis of Proposed Full Adder Cell at Submicron TechnologiesIJMTST Journal
This paper presents an analysis of high-speed and low-voltage full adder circuit analysis. The proposed circuit analyzed for parameters like logic levels and power consumption. Full adder is an important circuit for designing many types of processors like microprocessors, digital signal processors, image processing and various VLSI applications etc. Many blocks of the designs, adders lie in critical data path of the circuit which affects the overall performance of the system. In this regards this paper analyses the proposed full adder cell at block level. Ripple carry adder is taken as the benchmark circuit to analyze the proposed full adder cell at 45nm technology.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of
power dissipation in low power VLSI systems. This paper presented an idea of using the power gating
structure for reducing the sub threshold leakage in the reversible system. This concept presented in the
paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for
the digital systems, the energy can be saved up to the gate level implementation. But at the physical level
designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array
(RPLA) is one of the important parts of the low power industrial applications and in this paper the physical
design of the RPLA is presented by using the sleep transistor and the results is shown with the help of
TINA- PRO software. The results for the proposed design is also compare with the CMOS design and
shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the
switching activity and showing that the proposed design is much better that the modern CMOS design of
the RPLA.
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Presented in this short document is a description of what we call "Advanced" Property Tracking or Tracing (APT). APT is the term given to the technique of predicting, simulating, calculating or estimating the properties (i.e., densities, compositions, conditions, qualities, etc.) in a network or superstructure with significant inventory using statistical data reconciliation and regression (DRR)
Presented in this short document is a description of modeling and solving partial differential equations (PDE’s) in both the temporal and spatial dimensions using IMPL. The sample PDE problem is taken from Cutlip and Shacham (1999 and 2014) and models the process of unsteady-state heat transfer or conduction in a one dimensional (1D) slab with one face insulated and constant thermal conductivity as discussed by Geankoplis (1993).
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,paperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance Analysis of Proposed Full Adder Cell at Submicron TechnologiesIJMTST Journal
This paper presents an analysis of high-speed and low-voltage full adder circuit analysis. The proposed circuit analyzed for parameters like logic levels and power consumption. Full adder is an important circuit for designing many types of processors like microprocessors, digital signal processors, image processing and various VLSI applications etc. Many blocks of the designs, adders lie in critical data path of the circuit which affects the overall performance of the system. In this regards this paper analyses the proposed full adder cell at block level. Ripple carry adder is taken as the benchmark circuit to analyze the proposed full adder cell at 45nm technology.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Approach to design a high performance fault-tolerant reversible ALUVIT-AP University
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular
automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to
optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of
power dissipation in low power VLSI systems. This paper presented an idea of using the power gating
structure for reducing the sub threshold leakage in the reversible system. This concept presented in the
paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for
the digital systems, the energy can be saved up to the gate level implementation. But at the physical level
designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array
(RPLA) is one of the important parts of the low power industrial applications and in this paper the physical
design of the RPLA is presented by using the sleep transistor and the results is shown with the help of
TINA- PRO software. The results for the proposed design is also compare with the CMOS design and
shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the
switching activity and showing that the proposed design is much better that the modern CMOS design of
the RPLA.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array (RPLA) is one of the important parts of the low power industrial applications and in this paper the physical design of the RPLA is presented by using the sleep transistor and the results is shown with the help of TINA- PRO software. The results for the proposed design is also compare with the CMOS design and shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the switching activity and showing that the proposed design is much better that the modern CMOS design of the RPLA.
MF-RALU: design of an efficient multi-functional reversible arithmetic and l...IJECEIAES
Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The MFRALU utilizes a <11% chip area and consumes 332 mW total power. The RISC processor utilizes a <3% chip area and works at 483 MHZ frequency by consuming 159 mW of total power on Artix-7 FPGA.
Novel conservative reversible error control circuits based on molecular QCAVIT-AP University
Quantum-dot cellular automata are a prominent part of the nanoscale regime. They
use a quantum cellular based architecture which enables rapid information process with high
device density. This paper targets the two kinds of novel error control circuits such as Hamming
code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity
preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the
proposed gates and a few existing gates, the Hamming code and parity generator and checker
circuits are constructed. The proposed gates have been framed and verified in QCA. The
simulation outcomes signify that their framed circuits are faultless. In addition to verification,
physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit
delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
Multiple Valued Logic for Synthesis and Simulation of Digital CircuitsIJERA Editor
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].
High Speed Time Efficient Reversible ALU Based Logic Gate Structure on Vertex...IJERD Editor
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, the two novel 4*4 reversible logic gates (MRG and PAOG) are used with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed. The proposed design is synthesized using Xilinx ISE software and simulated using MODEL SIM 6.5b.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Researchers like Landauer and Bennett have shown that every bit of information lost will generate kTlog2 joules of
energy, whereas the energy dissipation would not occur, if computation is carried out in a reversible way. k is
Boltzmann’s constant and T is absolute temperature at which computation is performed. Thus reversible circuits will be
the most important one of the solutions of heat dissipation in Future circuit design. Reversible computing is motivated
by the Von Neumann Landauer (VNL) principle, a theorem of modern physics telling us that ordinary irreversible logic
operation which destructively overwrite previous outputs)in cur a fundamental physics) that performance on most
applications within realistic power constraints might still continue increasing indefinitely. Reversible logic is also a
core part of the quantum circuit model
Amazon products reviews classification based on machine learning, deep learni...TELKOMNIKA JOURNAL
In recent times, the trend of online shopping through e-commerce stores and websites has grown to a huge extent. Whenever a product is purchased on an e-commerce platform, people leave their reviews about the product. These reviews are very helpful for the store owners and the product’s manufacturers for the betterment of their work process as well as product quality. An automated system is proposed in this work that operates on two datasets D1 and D2 obtained from Amazon. After certain preprocessing steps, N-gram and word embedding-based features are extracted using term frequency-inverse document frequency (TF-IDF), bag of words (BoW) and global vectors (GloVe), and Word2vec, respectively. Four machine learning (ML) models support vector machines (SVM), logistic regression (RF), logistic regression (LR), multinomial Naïve Bayes (MNB), two deep learning (DL) models convolutional neural network (CNN), long-short term memory (LSTM), and standalone bidirectional encoder representations (BERT) are used to classify reviews as either positive or negative. The results obtained by the standard ML, DL models and BERT are evaluated using certain performance evaluation measures. BERT turns out to be the best-performing model in the case of D1 with an accuracy of 90% on features derived by word embedding models while the CNN provides the best accuracy of 97% upon word embedding features in the case of D2. The proposed model shows better overall performance on D2 as compared to D1.
Design, simulation, and analysis of microstrip patch antenna for wireless app...TELKOMNIKA JOURNAL
In this study, a microstrip patch antenna that works at 3.6 GHz was built and tested to see how well it works. In this work, Rogers RT/Duroid 5880 has been used as the substrate material, with a dielectric permittivity of 2.2 and a thickness of 0.3451 mm; it serves as the base for the examined antenna. The computer simulation technology (CST) studio suite is utilized to show the recommended antenna design. The goal of this study was to get a more extensive transmission capacity, a lower voltage standing wave ratio (VSWR), and a lower return loss, but the main goal was to get a higher gain, directivity, and efficiency. After simulation, the return loss, gain, directivity, bandwidth, and efficiency of the supplied antenna are found to be -17.626 dB, 9.671 dBi, 9.924 dBi, 0.2 GHz, and 97.45%, respectively. Besides, the recreation uncovered that the transfer speed side-lobe level at phi was much better than those of the earlier works, at -28.8 dB, respectively. Thus, it makes a solid contender for remote innovation and more robust communication.
Design and simulation an optimal enhanced PI controller for congestion avoida...TELKOMNIKA JOURNAL
In this paper, snake optimization algorithm (SOA) is used to find the optimal gains of an enhanced controller for controlling congestion problem in computer networks. M-file and Simulink platform is adopted to evaluate the response of the active queue management (AQM) system, a comparison with two classical controllers is done, all tuned gains of controllers are obtained using SOA method and the fitness function chose to monitor the system performance is the integral time absolute error (ITAE). Transient analysis and robust analysis is used to show the proposed controller performance, two robustness tests are applied to the AQM system, one is done by varying the size of queue value in different period and the other test is done by changing the number of transmission control protocol (TCP) sessions with a value of ± 20% from its original value. The simulation results reflect a stable and robust behavior and best performance is appeared clearly to achieve the desired queue size without any noise or any transmission problems.
Improving the detection of intrusion in vehicular ad-hoc networks with modifi...TELKOMNIKA JOURNAL
Vehicular ad-hoc networks (VANETs) are wireless-equipped vehicles that form networks along the road. The security of this network has been a major challenge. The identity-based cryptosystem (IBC) previously used to secure the networks suffers from membership authentication security features. This paper focuses on improving the detection of intruders in VANETs with a modified identity-based cryptosystem (MIBC). The MIBC is developed using a non-singular elliptic curve with Lagrange interpolation. The public key of vehicles and roadside units on the network are derived from number plates and location identification numbers, respectively. Pseudo-identities are used to mask the real identity of users to preserve their privacy. The membership authentication mechanism ensures that only valid and authenticated members of the network are allowed to join the network. The performance of the MIBC is evaluated using intrusion detection ratio (IDR) and computation time (CT) and then validated with the existing IBC. The result obtained shows that the MIBC recorded an IDR of 99.3% against 94.3% obtained for the existing identity-based cryptosystem (EIBC) for 140 unregistered vehicles attempting to intrude on the network. The MIBC shows lower CT values of 1.17 ms against 1.70 ms for EIBC. The MIBC can be used to improve the security of VANETs.
Conceptual model of internet banking adoption with perceived risk and trust f...TELKOMNIKA JOURNAL
Understanding the primary factors of internet banking (IB) acceptance is critical for both banks and users; nevertheless, our knowledge of the role of users’ perceived risk and trust in IB adoption is limited. As a result, we develop a conceptual model by incorporating perceived risk and trust into the technology acceptance model (TAM) theory toward the IB. The proper research emphasized that the most essential component in explaining IB adoption behavior is behavioral intention to use IB adoption. TAM is helpful for figuring out how elements that affect IB adoption are connected to one another. According to previous literature on IB and the use of such technology in Iraq, one has to choose a theoretical foundation that may justify the acceptance of IB from the customer’s perspective. The conceptual model was therefore constructed using the TAM as a foundation. Furthermore, perceived risk and trust were added to the TAM dimensions as external factors. The key objective of this work was to extend the TAM to construct a conceptual model for IB adoption and to get sufficient theoretical support from the existing literature for the essential elements and their relationships in order to unearth new insights about factors responsible for IB adoption.
Efficient combined fuzzy logic and LMS algorithm for smart antennaTELKOMNIKA JOURNAL
The smart antennas are broadly used in wireless communication. The least mean square (LMS) algorithm is a procedure that is concerned in controlling the smart antenna pattern to accommodate specified requirements such as steering the beam toward the desired signal, in addition to placing the deep nulls in the direction of unwanted signals. The conventional LMS (C-LMS) has some drawbacks like slow convergence speed besides high steady state fluctuation error. To overcome these shortcomings, the present paper adopts an adaptive fuzzy control step size least mean square (FC-LMS) algorithm to adjust its step size. Computer simulation outcomes illustrate that the given model has fast convergence rate as well as low mean square error steady state.
Design and implementation of a LoRa-based system for warning of forest fireTELKOMNIKA JOURNAL
This paper presents the design and implementation of a forest fire monitoring and warning system based on long range (LoRa) technology, a novel ultra-low power consumption and long-range wireless communication technology for remote sensing applications. The proposed system includes a wireless sensor network that records environmental parameters such as temperature, humidity, wind speed, and carbon dioxide (CO2) concentration in the air, as well as taking infrared photos.The data collected at each sensor node will be transmitted to the gateway via LoRa wireless transmission. Data will be collected, processed, and uploaded to a cloud database at the gateway. An Android smartphone application that allows anyone to easily view the recorded data has been developed. When a fire is detected, the system will sound a siren and send a warning message to the responsible personnel, instructing them to take appropriate action. Experiments in Tram Chim Park, Vietnam, have been conducted to verify and evaluate the operation of the system.
Wavelet-based sensing technique in cognitive radio networkTELKOMNIKA JOURNAL
Cognitive radio is a smart radio that can change its transmitter parameter based on interaction with the environment in which it operates. The demand for frequency spectrum is growing due to a big data issue as many Internet of Things (IoT) devices are in the network. Based on previous research, most frequency spectrum was used, but some spectrums were not used, called spectrum hole. Energy detection is one of the spectrum sensing methods that has been frequently used since it is easy to use and does not require license users to have any prior signal understanding. But this technique is incapable of detecting at low signal-to-noise ratio (SNR) levels. Therefore, the wavelet-based sensing is proposed to overcome this issue and detect spectrum holes. The main objective of this work is to evaluate the performance of wavelet-based sensing and compare it with the energy detection technique. The findings show that the percentage of detection in wavelet-based sensing is 83% higher than energy detection performance. This result indicates that the wavelet-based sensing has higher precision in detection and the interference towards primary user can be decreased.
A novel compact dual-band bandstop filter with enhanced rejection bandsTELKOMNIKA JOURNAL
In this paper, we present the design of a new wide dual-band bandstop filter (DBBSF) using nonuniform transmission lines. The method used to design this filter is to replace conventional uniform transmission lines with nonuniform lines governed by a truncated Fourier series. Based on how impedances are profiled in the proposed DBBSF structure, the fractional bandwidths of the two 10 dB-down rejection bands are widened to 39.72% and 52.63%, respectively, and the physical size has been reduced compared to that of the filter with the uniform transmission lines. The results of the electromagnetic (EM) simulation support the obtained analytical response and show an improved frequency behavior.
Deep learning approach to DDoS attack with imbalanced data at the application...TELKOMNIKA JOURNAL
A distributed denial of service (DDoS) attack is where one or more computers attack or target a server computer, by flooding internet traffic to the server. As a result, the server cannot be accessed by legitimate users. A result of this attack causes enormous losses for a company because it can reduce the level of user trust, and reduce the company’s reputation to lose customers due to downtime. One of the services at the application layer that can be accessed by users is a web-based lightweight directory access protocol (LDAP) service that can provide safe and easy services to access directory applications. We used a deep learning approach to detect DDoS attacks on the CICDDoS 2019 dataset on a complex computer network at the application layer to get fast and accurate results for dealing with unbalanced data. Based on the results obtained, it is observed that DDoS attack detection using a deep learning approach on imbalanced data performs better when implemented using synthetic minority oversampling technique (SMOTE) method for binary classes. On the other hand, the proposed deep learning approach performs better for detecting DDoS attacks in multiclass when implemented using the adaptive synthetic (ADASYN) method.
The appearance of uncertainties and disturbances often effects the characteristics of either linear or nonlinear systems. Plus, the stabilization process may be deteriorated thus incurring a catastrophic effect to the system performance. As such, this manuscript addresses the concept of matching condition for the systems that are suffering from miss-match uncertainties and exogeneous disturbances. The perturbation towards the system at hand is assumed to be known and unbounded. To reach this outcome, uncertainties and their classifications are reviewed thoroughly. The structural matching condition is proposed and tabulated in the proposition 1. Two types of mathematical expressions are presented to distinguish the system with matched uncertainty and the system with miss-matched uncertainty. Lastly, two-dimensional numerical expressions are provided to practice the proposed proposition. The outcome shows that matching condition has the ability to change the system to a design-friendly model for asymptotic stabilization.
Implementation of FinFET technology based low power 4×4 Wallace tree multipli...TELKOMNIKA JOURNAL
Many systems, including digital signal processors, finite impulse response (FIR) filters, application-specific integrated circuits, and microprocessors, use multipliers. The demand for low power multipliers is gradually rising day by day in the current technological trend. In this study, we describe a 4×4 Wallace multiplier based on a carry select adder (CSA) that uses less power and has a better power delay product than existing multipliers. HSPICE tool at 16 nm technology is used to simulate the results. In comparison to the traditional CSA-based multiplier, which has a power consumption of 1.7 µW and power delay product (PDP) of 57.3 fJ, the results demonstrate that the Wallace multiplier design employing CSA with first zero finding logic (FZF) logic has the lowest power consumption of 1.4 µW and PDP of 27.5 fJ.
Evaluation of the weighted-overlap add model with massive MIMO in a 5G systemTELKOMNIKA JOURNAL
The flaw in 5G orthogonal frequency division multiplexing (OFDM) becomes apparent in high-speed situations. Because the doppler effect causes frequency shifts, the orthogonality of OFDM subcarriers is broken, lowering both their bit error rate (BER) and throughput output. As part of this research, we use a novel design that combines massive multiple input multiple output (MIMO) and weighted overlap and add (WOLA) to improve the performance of 5G systems. To determine which design is superior, throughput and BER are calculated for both the proposed design and OFDM. The results of the improved system show a massive improvement in performance ver the conventional system and significant improvements with massive MIMO, including the best throughput and BER. When compared to conventional systems, the improved system has a throughput that is around 22% higher and the best performance in terms of BER, but it still has around 25% less error than OFDM.
Reflector antenna design in different frequencies using frequency selective s...TELKOMNIKA JOURNAL
In this study, it is aimed to obtain two different asymmetric radiation patterns obtained from antennas in the shape of the cross-section of a parabolic reflector (fan blade type antennas) and antennas with cosecant-square radiation characteristics at two different frequencies from a single antenna. For this purpose, firstly, a fan blade type antenna design will be made, and then the reflective surface of this antenna will be completed to the shape of the reflective surface of the antenna with the cosecant-square radiation characteristic with the frequency selective surface designed to provide the characteristics suitable for the purpose. The frequency selective surface designed and it provides the perfect transmission as possible at 4 GHz operating frequency, while it will act as a band-quenching filter for electromagnetic waves at 5 GHz operating frequency and will be a reflective surface. Thanks to this frequency selective surface to be used as a reflective surface in the antenna, a fan blade type radiation characteristic at 4 GHz operating frequency will be obtained, while a cosecant-square radiation characteristic at 5 GHz operating frequency will be obtained.
Reagentless iron detection in water based on unclad fiber optical sensorTELKOMNIKA JOURNAL
A simple and low-cost fiber based optical sensor for iron detection is demonstrated in this paper. The sensor head consist of an unclad optical fiber with the unclad length of 1 cm and it has a straight structure. Results obtained shows a linear relationship between the output light intensity and iron concentration, illustrating the functionality of this iron optical sensor. Based on the experimental results, the sensitivity and linearity are achieved at 0.0328/ppm and 0.9824 respectively at the wavelength of 690 nm. With the same wavelength, other performance parameters are also studied. Resolution and limit of detection (LOD) are found to be 0.3049 ppm and 0.0755 ppm correspondingly. This iron sensor is advantageous in that it does not require any reagent for detection, enabling it to be simpler and cost-effective in the implementation of the iron sensing.
Impact of CuS counter electrode calcination temperature on quantum dot sensit...TELKOMNIKA JOURNAL
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
In place of the commercial Pt electrode used in quantum sensitized solar cells, the low-cost CuS cathode is created using electrophoresis. High resolution scanning electron microscopy and X-ray diffraction were used to analyze the structure and morphology of structural cubic samples with diameters ranging from 40 nm to 200 nm. The conversion efficiency of solar cells is significantly impacted by the calcination temperatures of cathodes at 100 °C, 120 °C, 150 °C, and 180 °C under vacuum. The fluorine doped tin oxide (FTO)/CuS cathode electrode reached a maximum efficiency of 3.89% when it was calcined at 120 °C. Compared to other temperature combinations, CuS nanoparticles crystallize at 120 °C, which lowers resistance while increasing electron lifetime.
A progressive learning for structural tolerance online sequential extreme lea...TELKOMNIKA JOURNAL
This article discusses the progressive learning for structural tolerance online sequential extreme learning machine (PSTOS-ELM). PSTOS-ELM can save robust accuracy while updating the new data and the new class data on the online training situation. The robustness accuracy arises from using the householder block exact QR decomposition recursive least squares (HBQRD-RLS) of the PSTOS-ELM. This method is suitable for applications that have data streaming and often have new class data. Our experiment compares the PSTOS-ELM accuracy and accuracy robustness while data is updating with the batch-extreme learning machine (ELM) and structural tolerance online sequential extreme learning machine (STOS-ELM) that both must retrain the data in a new class data case. The experimental results show that PSTOS-ELM has accuracy and robustness comparable to ELM and STOS-ELM while also can update new class data immediately.
Electroencephalography-based brain-computer interface using neural networksTELKOMNIKA JOURNAL
This study aimed to develop a brain-computer interface that can control an electric wheelchair using electroencephalography (EEG) signals. First, we used the Mind Wave Mobile 2 device to capture raw EEG signals from the surface of the scalp. The signals were transformed into the frequency domain using fast Fourier transform (FFT) and filtered to monitor changes in attention and relaxation. Next, we performed time and frequency domain analyses to identify features for five eye gestures: opened, closed, blink per second, double blink, and lookup. The base state was the opened-eyes gesture, and we compared the features of the remaining four action gestures to the base state to identify potential gestures. We then built a multilayer neural network to classify these features into five signals that control the wheelchair’s movement. Finally, we designed an experimental wheelchair system to test the effectiveness of the proposed approach. The results demonstrate that the EEG classification was highly accurate and computationally efficient. Moreover, the average performance of the brain-controlled wheelchair system was over 75% across different individuals, which suggests the feasibility of this approach.
Adaptive segmentation algorithm based on level set model in medical imagingTELKOMNIKA JOURNAL
For image segmentation, level set models are frequently employed. It offer best solution to overcome the main limitations of deformable parametric models. However, the challenge when applying those models in medical images stills deal with removing blurs in image edges which directly affects the edge indicator function, leads to not adaptively segmenting images and causes a wrong analysis of pathologies wich prevents to conclude a correct diagnosis. To overcome such issues, an effective process is suggested by simultaneously modelling and solving systems’ two-dimensional partial differential equations (PDE). The first PDE equation allows restoration using Euler’s equation similar to an anisotropic smoothing based on a regularized Perona and Malik filter that eliminates noise while preserving edge information in accordance with detected contours in the second equation that segments the image based on the first equation solutions. This approach allows developing a new algorithm which overcome the studied model drawbacks. Results of the proposed method give clear segments that can be applied to any application. Experiments on many medical images in particular blurry images with high information losses, demonstrate that the developed approach produces superior segmentation results in terms of quantity and quality compared to other models already presented in previeous works.
Automatic channel selection using shuffled frog leaping algorithm for EEG bas...TELKOMNIKA JOURNAL
Drug addiction is a complex neurobiological disorder that necessitates comprehensive treatment of both the body and mind. It is categorized as a brain disorder due to its impact on the brain. Various methods such as electroencephalography (EEG), functional magnetic resonance imaging (FMRI), and magnetoencephalography (MEG) can capture brain activities and structures. EEG signals provide valuable insights into neurological disorders, including drug addiction. Accurate classification of drug addiction from EEG signals relies on appropriate features and channel selection. Choosing the right EEG channels is essential to reduce computational costs and mitigate the risk of overfitting associated with using all available channels. To address the challenge of optimal channel selection in addiction detection from EEG signals, this work employs the shuffled frog leaping algorithm (SFLA). SFLA facilitates the selection of appropriate channels, leading to improved accuracy. Wavelet features extracted from the selected input channel signals are then analyzed using various machine learning classifiers to detect addiction. Experimental results indicate that after selecting features from the appropriate channels, classification accuracy significantly increased across all classifiers. Particularly, the multi-layer perceptron (MLP) classifier combined with SFLA demonstrated a remarkable accuracy improvement of 15.78% while reducing time complexity.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
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• Compatible with MAFI CCR system.
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• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
1. TELKOMNIKA Telecommunication, Computing, Electronics and Control
Vol. 18, No. 1, February 2020, pp. 234~239
ISSN: 1693-6930, accredited First Grade by Kemenristekdikti, Decree No: 21/E/KPT/2018
DOI: 10.12928/TELKOMNIKA.v18i1.12645 234
Journal homepage: http://journal.uad.ac.id/index.php/TELKOMNIKA
Novel high functionality fault tolerant ALU
Shaveta Thakral, Dipali Bansal
Department of Electronics and Communication Engineering, Faculty of Engineering and Technology,
Manav Rachna International Institute of Research and Studies, India
Article Info ABSTRACT
Article history:
Received Mar 11, 2019
Revised Jul 3, 2019
Accepted Jul 21, 2019
Miniaturization, cost, functionality, complexity and power dissipation are
important and necessary design traits which need attention in circuit
designing. There is a trade off between miniaturization and power
dissipation. Smart technology is always searching for new paradigms to
continue improve power dissipation. Reversible logic is one of smart
computing deployed to avoid power dissipation. Researchers have proposed
many reversible logic-based arithmetic and logic units (ALU). However,
the research in the area of fault tolerant ALU is still under progress. The aim
of this paper is to bridge the knowledge gap for a new researcher in area of
fault tolerance using parity preserving logic gates rather than searching huge
data through various sources. This paper also presents a high functionality
based novel fault tolerant arithmetic and logic unit architecture.
A comparison on optimization aspects is presented in tabular form and
results shows that proposed ALU architecture is optimum balance in terms of
all aspects of reversible logic synthesis. The proposed ALU architecture is
coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool.
The quantum cost of all gates used in proposed architecture is verified using
RCViewer + tool.
Keywords:
ALU
Fault tolerant
Power dissipation
Reversible logic
Synthesis
This is an open access article under the CC BY-SAlicense.
Corresponding Author:
Shaveta Thakral,
Department of Electronics and Communication Engineering, Faculty of Engineering and Technology,
Manav Rachna International Institute of Research & Studies,
Faridabad, India.
Email: shaveta.fet@mriu.edu.in
1. INTRODUCTION
Reversible computing is found to be one of the emerging and promising technologies to overcome
power dissipation due to loss of bits. Rolf Landauer [1] and C.H. Bennett [2], jointly addressed the issue and
shown the direction to work in this area. A significant work has been already done by many researchers and
efficient architectures have been investigated. Smart reversible computing is incorporating fault tolerance
mechanism in existing architectures. Circuit designed for any application is reliable and robust only if fault
coverage and testable features are embedded into it. Fault tolerance embedding avoids additional hardware
and complexity overhead. In order to achieve robustness and making reversible logic based designed system
fault tolerant; parity preserving logic gates are used. Complex computing environment is switching from peta
scale to exa scale and fault tolerant ALU is heart of it.
Parity preserving logic gates are based on principle of holding parity. If input vector (ABC) of
3*3 gate holds even/odd parity, then output vector (PQR) should also hold even/odd parity. Conservative
gate is not only parity preserving but it also maintains equal number of 1’s in both input and output vectors. It
is easy to investigate parity preserving reversible logic gate but making it conservative is a bit intractable.
2. TELKOMNIKATelecommun Comput El Control
Novel high functionality fault tolerant ALU (Shaveta Thakral)
235
Fredkin gate is exclusively designed to maintain conservative property. Researchers have investigated many
parity preserving logic gates. Some of them are one through and conservative also. Most of the researches
have shown quantum equivalence of their proposed gates and defined their corresponding quantum cost yet
quantum cost of some is still unknown and need to be investigated like PRUG and PPPG gates.
In the past few years researchers have made efforts to design reversible logic based ALU [3-6].
However, till now available research results on fault tolerant arithmetic logic unit are very few.
Guan et al. [6] proposed optimized arithmetic and logic circuit but fault tolerance is missing in their design.
Rakshith and Saligram [7] proposed fault tolerant arithmetic logic unit using parity preserving logic but
complexity of circuit is high for n bit ALU as divide and conquer approach is missing. Many other
researchers have obtained good results in ALU optimization [8, 9]. Saligram et al., [10] have proposed two
faults tolerant ALU architectures but quantum cost of both circuits is unspecified. Bashiri and
Haghparast [11] proposed fault tolerant ALU architecture but garbage and ancillary lines remain unoptimized
as compare to number of operations performed. Authors proposed and analyzed a basic model of fault
tolerant reversible ALU but quantum cost is high and number of operations are limited [12]. Fault tolerance
is incorporated in 1-bit ALU structure based on 7 parity preserving gates including FTRA, Fredkin and
double Feynman gates. There is optimum utilization of resources but functionality is limited [13].
Moallem et al., [14] provided another approach of designing arithmetic and logic unit but fault tolerance
feature is not added to circuit. Another unique approach of ALU design is presented in research work [15].
Sen et al., [16] proposed 1-bit ALU structure but many design traits remain unoptimized. Proposed design
does not even support fault tolerance.
Thakral and Bansal [17] proposed fault tolerant ALU architecture using parity preserving logic gates
but unable to prove it completely fault tolerant due to use of HNG gate. Some researchers have investigated
parity preserving reversible logic-based gates and utilized them to design fault tolerant ALU but quantum
cost of their proposed ALU remains unspecified [18, 19]. Implementation and comparative analysis of
existing ALU designs is focussed to investigate scope of improvement in state of the art [20]. In 2016,
Misra et al., [21] proposed new technique for fault tolerant ALU design with 32 operations but there are some
redundant operations. Rahimpour and Jafari [22] proposed fault tolerant ALU using QCA technology QCA
analysis shows good results as far as delay and area are concerned but functionality and quantum cost also
need to be focused in this work. Bahadori et al., [23] proposed reversible control unit with fault tolerance
mechanism. The quantum cost is optimum in terms of number of operations but for complete ALU, quantum
cost will rise with circuit expansion. Das and Chandaran [24] proposed 1-bit ALU incorporated with fault
tolerance. There is optimum utilization of resources like constant input lines, garbage output lines and gate
count as far as number of operations are concerned but there is scope of improvement of its functions and
quantum cost. Thakral and Bansal [25, 26] proposed reduced quantum cost-based fault tolerant ALU
architectures. Each existing design has some advantages and limitations. However, there is a lot of scope for
further improvement of optimization metrics like quantum cost, ancillary inputs, number of operations and
garbage outputs. This paper presents a novel low complex and high functionality-based fault tolerant
arithmetic logic unit. Proposed fault tolerant arithmetic logic unit is designed based on conservative and
parity preserving “Fredkin”, low quantum cost parity preserving based “Double Feynman” and high
functionality parity preserving based “FTRA” gates. A brief insight into used parity preserving logic gates
along with expression and quantum implementation is given in Table 1. The methodology of proposed ALU
design, proposed novel architecture, design traits comparison and conclusion are given in section 2 to 5.
Table 1. Popular parity preserving logic gates
Reversible logic gate Expression Quantum implementation
Fredkin
Double Feynman
Fault tolerant reversible adder
(FTRA)
3. ISSN:1693-6930
TELKOMNIKATelecommun Comput El Control, Vol. 18, No. 1, February 2020: 234 - 239
236
2. METHODOLOGY OF PROPOSED DESIGN
The proposed fault tolerant arithmetic logic unit architecture is designed to keep in view enhancing
functionality. Proposed circuit is designed using six “Fredkin” gates, four “Double Feynman” gates and one
“FTRA gate” which are parity preserving gates. Proposed Circuit is shown in Figure 1. “Double Feynman
gate 1” is passing B or B’ as per select line S0. “Fredkin gate 1” is acting as 2:1 multiplexer. S2 and T1 are
inputs of multiplexer and S1 is acting as selection line. “Fredkin gate 1” is passing 0, 1, B and B’ as per
desired logic depending upon combination of S1 and S2. “Double Feynman gate 2” is duplicating as well as
inverting the input signal. “Double Feynman gate 2” is passing B or B’ as per desired logic depending upon
select line S3. “Fredkin gate 2” is acting as 2:1 multiplexer. S5 and T3 are two input lines and S3 is acting as
select line. It is passing S5 (logic 0 /logic 1) or T3 (signal B/B’) as per desired logic depending upon
combination of S4 and S5. “Double Feynman gate 3” is duplicating as well as inverting input signal as per
requirement. “Double Feynman gate 3” is passing A as well as A’ as per desired logic depending upon select
lines S6 and S7. “Double Feynman gate 4” is used to avoid fan out problem and copying S8 signal on all
three output lines. “Double Feynman gate 4” is passing ‘0’ or ‘1’ chosen by select line S8. “Fredkin gate 3” is
passing logic ‘0’ or logic ‘1’ or signal A or AB or AB’ or A’B or A+B or A+B’ as per desired logic
depending upon combination of T6, T4 and T7. If T7 is 0, then AND of complement of signal on T6 input
line and signal on T4 input line is produced on T8 output line. If T7 is 1, Then OR of signals on T6 and T4
input lines is produced on T8 output line.
Figure 1. Proposed high functionality fault tolerant reversible ALU architecture
“FTRA gate” is 5x5 parity preserving fault tolerant reversible adder gate which can work as full
adder as well as full subtractor along with performing other logical operations; proving it to be a universal
logic gate. FTRA is operated under various combinations of selection lines to perform 12 logical operations
and 28 arithmetic operations. In total it can perform 40 operations. This high functionality proves it to be
optimum arithmetic logic unit. Fourteen selection lines are used to control operation of arithmetic and logic
unit. For performing logical operations, S3 is put don’t care, S4, S6 and S7 are put to zero. Logical operations
4. TELKOMNIKATelecommun Comput El Control
Novel high functionality fault tolerant ALU (Shaveta Thakral)
237
XOR, XNOR, A and A’ are obtained on F1 output line, AND, NOR, OR, NAND are obtained on F2 line and
(A+B’), (A’+B), AB’, A’B are obtained on F3 output line. If input vector of FTRA is considered as
A,B,C,D,E and output vector is considered as P,Q,R,S,T then FTRA works as full adder with three inputs
A,B and Cin are provided on A,B,C lines and D, E are put to zero . In this arrangement, sum is obtained on R
line and Cout is obtained on S line. While for subtraction inputs A, B and Bin are provided on A, B and D
lines respectively and C, E are put to zero. In this arrangement, Difference is obtained on R line and Bout is
obtained on T line. “Fredkin gate 5” is acting as 2:1 multiplexer. F1 and F2 are two input lines and S12 is
acting as select line. It is passing F1 or F2 on func1 output line as per desired logic depending upon select
line S12. “Fredkin gate 6” is acting as 2:1 multiplexer. It is passing func1 (F1 or F2) or F3 on func output line
as per desired logic depending upon select line S13.
3. PROPOSED FAULT TOLERANT ALU ARCHITECTURE
The proposed Fault tolerant ALU architecture is configured to perform 40 operations including
12 logical and 28 arithmetic operations. List of logical operations performed by proposed arithmetic and
logical unit is shown in Table 2. For performing logical operations; S3 is put to don’t care condition while
S4, S6, S7 and S9 are put to 0. List of arithmetic operations are divided into two sets. Arithmetic operations
set 1 comprises of addition related operations and Arithmetic operations set 2 comprises of subtraction
related operations. For set-1operations; S9, S10, S11, S12 and S13 are put to 0 while for set-2 operations; S9
is put equal to 1 and S10, S11, S12 and S13 are put to 0. List of arithmetic operations performed by proposed
arithmetic and logic unit is shown in Table 3. Total operations count is 40 making it high functionality fault
tolerant arithmetic and logical unit. Proposed high functionality fault tolerant reversible ALU architecture is
shown in Figure 1. As proposed novel architecture consists of six Fredkin gates (with quantum cost of
5 each), four double Feynman gates (with quantum cost of 2 each) and one FTRA gate with quantum cost of
8. Therefore, total quantum cost calculated is 46. The simulation waveform of proposed high functionality
fault tolerant reversible ALU architecture is shown in Figure 2
Table 2. Logical operations
S0 S1 S2 S5 S8 S10 S11 S12 S13 func
0 1 x 0 0 0 1 0 0 A XOR B
0 1 X 0 0 0 1 1 0 A AND B
0 1 X 0 0 0 1 X 1 A+B’
0 1 X 0 0 1 0 0 0 A XNOR B
0 1 X 0 0 1 0 1 0 A NOR B
0 1 X 0 0 1 0 X 1 A’+B
0 1 X 1 1 0 0 1 0 A OR B
0 1 X 1 1 0 0 X 1 AB’
0 1 X 1 1 1 1 1 0 A NAND B
0 1 X 1 1 1 1 X 1 A’B
X 0 0 0 0 0 1 0 0 A
X 0 1 0 0 0 1 0 0 A’
Table 3. Arithmetic operations
S0 S1 S2 S3 S4 S5 S6 S7 S8 Func (Set-1) Func (Set-2)
X 0 0 1 1 X 1 1 0 A plus AB’ A minus AB’
1 1 X 0 1 X 1 1 0 A plus B’ plus AB A minus B’ minus AB
0 1 X 1 1 X 1 1 0 A plus B plus AB’ A minus B minus AB’
0 1 X X 0 0 0 0 0 A plus B A minus B
1 1 X X 0 0 0 0 0 A plus B’ A minus B’
X 0 0 0 1 X 1 1 0 A plus AB A minus AB
1 1 X X 0 0 0 0 1 A plus B’ plus A A minus B’ minus A
0 1 X X 0 0 0 0 1 A plus B plus A A minus B minus A
X 0 0 0 1 X 0 0 0 A plus A’B A minus A’B
0 1 X 0 1 X 0 0 0 A plus B plus A’B A minus B minus A’B
1 1 X 0 1 X 0 0 0 A plus B’ plus A’B A minus B’ minus A’B
X 0 0 0 1 X 0 0 1 A plus (A+B) A minus (A+B)
X 0 0 1 1 X 0 0 1 A plus (A+B’) A minus (A+B’)
X 0 0 X 0 0 0 0 1 A plus A A minus A
5. ISSN:1693-6930
TELKOMNIKATelecommun Comput El Control, Vol. 18, No. 1, February 2020: 234 - 239
238
Figure 2. Simulation waveform of proposed fault tolerant reversible ALU architecture
4. COMPARISON AND RESULTS
The proposed novel high functionality fault tolerant ALU architecture is compared with
Design 1 [6], Design 2 [7] and Design 3 [21] in terms of important reversible design traits. The proposed
architecture is designed with minimum quantum cost; 46 and highest operations: 40. There is drastic
reduction in reversible logic gates, constant input lines and complexity is also avoided. Reversible design
trait comparison sheet of various ALU designs is presented in Table 4. A comparison on optimization aspects
is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of
all aspects of reversible logic synthesis. Bar chart representation is shown in Figure 3 to compare evaluation
results and clear understanding.
Figure 3. Bar chart comparison for quantitative analysis
Table 4. Reversible design trait comparison sheet
ALU
DESIGNS
Design
1
[6]
Design
2
[7]
Design
3
[21]
Proposed
Fault
Tolerant
ALU
Architecture
No. of
Gates
24 17 16 11
Quantum
Cost
70 595 77 46
Operations 32 32 32 40
Garbage
Outputs
12 37 25 20
Ancillary
Inputs
12 33 25 4
Fault
Tolerance
No Yes Yes Yes
5. CONCLUSION
The proposed novel high functionality fault tolerant ALU design promises the low quantum cost and
high functionality as compare to other existing designs. The bar chart comparison of proposed novel high
6. TELKOMNIKATelecommun Comput El Control
Novel high functionality fault tolerant ALU (Shaveta Thakral)
239
functionality fault tolerant ALU design over existing ALU design 1, 2 and 3 quantitatively demonstrates
25% increase in functionality with 40% reduction in quantum cost as compare to best results in literature.
Fault tolerance and test patterns not only make system robust but also demanded by smart computing
required for industrial and commercial applications. This research may be further extended for multibit fault
detection and correction along with functionality enhancement.
REFERENCES
[1] Landauer R., “Irreversibility and Heat Generation in the Computing Process,” IBM Journal of Research and
Development, vol. 5, no. 3, pp. 183-191, 1961.
[2] Bennett C., “Logical Reversibility of Computation,” IBM Journal of Research and Development, vol. 17, no. 6,
pp. 525-532, 1973.
[3] Thomsen M., Glück R., Axelsen H., “Reversible Arithmetic Logic Unit for Quantum Arithmetic,” Journal of
Physics A: Mathematical and Theoretical, vol. 43, no. 38, 2010.
[4] Matthew M, Matthew L, Richard M, Nagarajan R., “Design of a Novel Reversible ALU using an Enhanced Carry
Look Ahead Adder,” 11th
IEEE International Conference on Nanotechnology, 2012.
[5] Syamala Y, Tilak A., “Reversible Arithmetic Logic Unit,” 2011 3rd
International Conference on Electronics
Computer Technology, 2011.
[6] Guan Z., Li W., Ding W., Hang Y., Ni L., “An Arithmetic Logic Unit Design Based on Reversible Logic Gates,”
Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2011.
[7] Rakshith, T.R. and Saligram, R., “Parity Preserving Logic Based Fault Tolerant Reversible ALU,” 2013 IEEE
Conference on Information & Communication Technologies, 2013.
[8] Singh R, Upadhyay S, S S, Jagannath K, Hariprasad S., “Efficient Design of Arithmetic Logic Unit using
Reversible Logic Gates,” International Journal of Advanced Research in Computer Engineering & Technology
(IJARCET), vol. 3, no. 4, pp. 1474-1477, 2014.
[9] Gupta A, Malviya U, Kapse V., “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic
ALU for Digital Processors,” 2012 Nirma University International Conference on Engineering (NUiCONE),
2014.
[10] Saligram R., Shridhar Hegde S., A. Kulkarni S, H.R. Bhagyalakshmi, M.K. Venkatesha, “Design of Parity
Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit,” International Journal of VLSI Design
& Communication Systems, vol. 4, pp. 53-68, 2013.
[11] Bashiri R., HaghparastM., “Designing a Novel Nanometric Parity Preserving Reversible ALU,” Journal of Basic
and Applied Scientific Research, vol. 3, no. 6, pp. 572-580, 2013.
[12] Safari P., Haghparast M., Azari A., Branch A., “A Design of Fault Tolerant Reversible Arithmetic Logic Unit,”
Life Science Journal, vol. 9, no. 3, pp. 643-646, 2012.
[13] Sen B., Ganeriwal S., Sikdar B. K., “Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA,” International
Scholarly Research Notices, vol. 2013, pp. 1-9, 2013.
[14] Moallem P., Ehsanpour M., Bolhasani A., Montazeri M., “Optimized Reversible Arithmetic Logic Units,”
Journal of Electronics (China), vol. 31, no.5, pp. 394-405, 2014.
[15] Gopal L., Syahira N., Mahayadin M., Chowdhury A., Gopalai A., Singh A., “Design and Synthesis of Reversible
Arithmetic and Logic Unit (ALU),” International Conference on Computer, Communications, and Control
Technology (I4CT), 2014.
[16] Sen B., Dutta M., Goswami M., Sikdar B., “Modular Design of Testable Reversible ALU by QCA Multiplexer
with increase in Programmability,” Microelectronics Journal, vol. 45, no. 11, pp. 1522-1532, 2014.
[17] Thakral S., Bansal D., “Fault Tolerant ALU using Parity Preserving Reversible Logic Gates,” International
Journal of Modern Education and Computer Science, vol, 8, no. 8, pp. 51-58, 2016.
[18] Sasamal T., Singh A., Mohan A., “Efficient Design of Reversible ALU in Quantum-Dot Cellular Automata,”
Optik, vol. 127, no. 15, pp. 6172-6182, 2016.
[19] Krishna Murthy M., “Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate (PPPG),”
International Journal of VLSI Design & Communication Systems, vol. 3, no. 3, pp. 83-39, 2012.
[20] Thakral S., Bansal D., Chakarvarti S., “Implementation and Analysis of Reversible logic Based Arithmetic Logic
Unit,” TELKOMNIKA Telecommunication Computing Electronics and Control, vol. 14, no. 4, 1292-1298, 2016.
[21] Misra N. K., Wairya S., & Singh V. K., “Approach to Design a High-Performance Fault-Tolerant Reversible
ALU,” International Journal of Circuits and Architecture Design, vol. 2, no. 1, pp. 83-103, 2016.
[22] Gadim M. R., Navimipour N. J., “A New Three-Level Fault Tolerance Arithmetic and Logic Unit Based on
Quantum Dot Cellular Automata,” Microsystem technologies, vol. 24, no. 2, pp. 1295-1305, 2018.
[23] Bahadori G., Houshmand M., Zomorodi-Moghadam M., “Design of a Fault-Tolerant Reversible Control Unit in
Molecular Quantum-Dot Cellular Automata,” International Journal of Quantum Information, vol. 16, no. 1,
2018.
[24] Das B. and Chandran S., “Towards the Designing of Efficient Computing Reversible Fault Tolerant Arithmetic
Circuits and ALU,” European Journal of Scientific Research, vol.150, no. 2, pp. 126-151, 2018.
[25] Thakral S., and Bansal D., “Fault Tolerant Arithmetic Logic Unit,” International Conference on Emerging
Current Trends in Computing and Expert Technology, pp. 226-233, 2019.
[26] Thakral S., and Bansal D., “Improved Fault Tolerant ALU Architecture,” International Journal of Engineering
and Advanced Technology (IJEAT), vol. 8, no. 6, pp. 1477-1484, 2019.
![TELKOMNIKA Telecommunication, Computing, Electronics and Control
Vol. 18, No. 1, February 2020, pp. 234~239
ISSN: 1693-6930, accredited First Grade by Kemenristekdikti, Decree No: 21/E/KPT/2018
DOI: 10.12928/TELKOMNIKA.v18i1.12645 234
Journal homepage: http://journal.uad.ac.id/index.php/TELKOMNIKA
Novel high functionality fault tolerant ALU
Shaveta Thakral, Dipali Bansal
Department of Electronics and Communication Engineering, Faculty of Engineering and Technology,
Manav Rachna International Institute of Research and Studies, India
Article Info ABSTRACT
Article history:
Received Mar 11, 2019
Revised Jul 3, 2019
Accepted Jul 21, 2019
Miniaturization, cost, functionality, complexity and power dissipation are
important and necessary design traits which need attention in circuit
designing. There is a trade off between miniaturization and power
dissipation. Smart technology is always searching for new paradigms to
continue improve power dissipation. Reversible logic is one of smart
computing deployed to avoid power dissipation. Researchers have proposed
many reversible logic-based arithmetic and logic units (ALU). However,
the research in the area of fault tolerant ALU is still under progress. The aim
of this paper is to bridge the knowledge gap for a new researcher in area of
fault tolerance using parity preserving logic gates rather than searching huge
data through various sources. This paper also presents a high functionality
based novel fault tolerant arithmetic and logic unit architecture.
A comparison on optimization aspects is presented in tabular form and
results shows that proposed ALU architecture is optimum balance in terms of
all aspects of reversible logic synthesis. The proposed ALU architecture is
coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool.
The quantum cost of all gates used in proposed architecture is verified using
RCViewer + tool.
Keywords:
ALU
Fault tolerant
Power dissipation
Reversible logic
Synthesis
This is an open access article under the CC BY-SAlicense.
Corresponding Author:
Shaveta Thakral,
Department of Electronics and Communication Engineering, Faculty of Engineering and Technology,
Manav Rachna International Institute of Research & Studies,
Faridabad, India.
Email: shaveta.fet@mriu.edu.in
1. INTRODUCTION
Reversible computing is found to be one of the emerging and promising technologies to overcome
power dissipation due to loss of bits. Rolf Landauer [1] and C.H. Bennett [2], jointly addressed the issue and
shown the direction to work in this area. A significant work has been already done by many researchers and
efficient architectures have been investigated. Smart reversible computing is incorporating fault tolerance
mechanism in existing architectures. Circuit designed for any application is reliable and robust only if fault
coverage and testable features are embedded into it. Fault tolerance embedding avoids additional hardware
and complexity overhead. In order to achieve robustness and making reversible logic based designed system
fault tolerant; parity preserving logic gates are used. Complex computing environment is switching from peta
scale to exa scale and fault tolerant ALU is heart of it.
Parity preserving logic gates are based on principle of holding parity. If input vector (ABC) of
3*3 gate holds even/odd parity, then output vector (PQR) should also hold even/odd parity. Conservative
gate is not only parity preserving but it also maintains equal number of 1’s in both input and output vectors. It
is easy to investigate parity preserving reversible logic gate but making it conservative is a bit intractable.](https://image.slidesharecdn.com/2712645-200714055746/85/Novel-high-functionality-fault-tolerant-ALU-1-320.jpg)
![TELKOMNIKATelecommun Comput El Control
Novel high functionality fault tolerant ALU (Shaveta Thakral)
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Fredkin gate is exclusively designed to maintain conservative property. Researchers have investigated many
parity preserving logic gates. Some of them are one through and conservative also. Most of the researches
have shown quantum equivalence of their proposed gates and defined their corresponding quantum cost yet
quantum cost of some is still unknown and need to be investigated like PRUG and PPPG gates.
In the past few years researchers have made efforts to design reversible logic based ALU [3-6].
However, till now available research results on fault tolerant arithmetic logic unit are very few.
Guan et al. [6] proposed optimized arithmetic and logic circuit but fault tolerance is missing in their design.
Rakshith and Saligram [7] proposed fault tolerant arithmetic logic unit using parity preserving logic but
complexity of circuit is high for n bit ALU as divide and conquer approach is missing. Many other
researchers have obtained good results in ALU optimization [8, 9]. Saligram et al., [10] have proposed two
faults tolerant ALU architectures but quantum cost of both circuits is unspecified. Bashiri and
Haghparast [11] proposed fault tolerant ALU architecture but garbage and ancillary lines remain unoptimized
as compare to number of operations performed. Authors proposed and analyzed a basic model of fault
tolerant reversible ALU but quantum cost is high and number of operations are limited [12]. Fault tolerance
is incorporated in 1-bit ALU structure based on 7 parity preserving gates including FTRA, Fredkin and
double Feynman gates. There is optimum utilization of resources but functionality is limited [13].
Moallem et al., [14] provided another approach of designing arithmetic and logic unit but fault tolerance
feature is not added to circuit. Another unique approach of ALU design is presented in research work [15].
Sen et al., [16] proposed 1-bit ALU structure but many design traits remain unoptimized. Proposed design
does not even support fault tolerance.
Thakral and Bansal [17] proposed fault tolerant ALU architecture using parity preserving logic gates
but unable to prove it completely fault tolerant due to use of HNG gate. Some researchers have investigated
parity preserving reversible logic-based gates and utilized them to design fault tolerant ALU but quantum
cost of their proposed ALU remains unspecified [18, 19]. Implementation and comparative analysis of
existing ALU designs is focussed to investigate scope of improvement in state of the art [20]. In 2016,
Misra et al., [21] proposed new technique for fault tolerant ALU design with 32 operations but there are some
redundant operations. Rahimpour and Jafari [22] proposed fault tolerant ALU using QCA technology QCA
analysis shows good results as far as delay and area are concerned but functionality and quantum cost also
need to be focused in this work. Bahadori et al., [23] proposed reversible control unit with fault tolerance
mechanism. The quantum cost is optimum in terms of number of operations but for complete ALU, quantum
cost will rise with circuit expansion. Das and Chandaran [24] proposed 1-bit ALU incorporated with fault
tolerance. There is optimum utilization of resources like constant input lines, garbage output lines and gate
count as far as number of operations are concerned but there is scope of improvement of its functions and
quantum cost. Thakral and Bansal [25, 26] proposed reduced quantum cost-based fault tolerant ALU
architectures. Each existing design has some advantages and limitations. However, there is a lot of scope for
further improvement of optimization metrics like quantum cost, ancillary inputs, number of operations and
garbage outputs. This paper presents a novel low complex and high functionality-based fault tolerant
arithmetic logic unit. Proposed fault tolerant arithmetic logic unit is designed based on conservative and
parity preserving “Fredkin”, low quantum cost parity preserving based “Double Feynman” and high
functionality parity preserving based “FTRA” gates. A brief insight into used parity preserving logic gates
along with expression and quantum implementation is given in Table 1. The methodology of proposed ALU
design, proposed novel architecture, design traits comparison and conclusion are given in section 2 to 5.
Table 1. Popular parity preserving logic gates
Reversible logic gate Expression Quantum implementation
Fredkin
Double Feynman
Fault tolerant reversible adder
(FTRA)](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)