This document contains Sai Dheeraj Polagani's resume. It includes his contact information, objective, education history, industrial experience at Intel as a physical design engineer and layout engineer, previous experience at Wipro Technologies as an ASIC physical design and verification engineer, technical skills, projects completed and academic projects during his Master's program. His experience includes full-chip static timing analysis, noise analysis, cross-talk analysis, place and route, timing closure, and physical verification. He has a Master's in Electrical Engineering from San Jose State University and a Bachelors in Information and Communication Technology from DA-IICT, India.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
vlsi projects using verilog code 2014-2015E2MATRIX
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Implementation of Rotation and Vectoring-Mode Reconfigurable CORDICijtsrd
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. In this project A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 13.2. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by Chip Scope Pro analysis of the output logic waveforms was performed. Kothapally Mounika | P. Pavan Kumar | K. Shobha Rani"Implementation of Rotation and Vectoring-Mode Reconfigurable CORDIC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14396.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14396/implementation-of-rotation-and-vectoring-mode-reconfigurable-cordic/kothapally-mounika
Hardware simulation for exponential blind equal throughput algorithm using sy...IJECEIAES
Scheduling mechanism is the process of allocating radio resources to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution base station, Evolved Node B. Normally, most of the proposed algorithms are not focusing on handling the real-time and non-real-time traffics simultaneously. Thus, UE with bad channel quality may starve due to no resources allocated for quite a long time. To solve the problems, Exponential Blind Equal Throughput (EXP-BET) algorithm is proposed. User with the highest priority metrics is allocated the resources firstly which is calculated using the EXP-BET metric equation. This study investigates the implementation of the EXP-BET scheduling algorithm on the FPGA platform. The metric equation of the EXP-BET is modelled and simulated using System Generator. This design has utilized only 10% of available resources on FPGA. Fixed numbers are used for all the input to the scheduler. The system verification is performed by simulating the hardware co-simulation for the metric value of the EXP-BET metric algorithm. The output from the hardware co-simulation showed that the metric values of EXP-BET produce similar results to the Simulink environment. Thus, the algorithm is ready for prototyping and Virtex-6 FPGA is chosen as the platform.
The growing interest in FPGA-based solutions for accelerating compute demanding algorithms is pushing the need for new tools and methods to improve productivity. High-Level Synthesis (HLS) tools already provide an handy way to describe an FPGA-based hardware implementations starting from a software description of an algorithm. However, HLS directives allow to improve the hardware design only from a computational perspective, requiring a manual code restructuring in case memory transfer needs optimizing. This aspect limits the effectiveness of Design Space Exploration (DSE) approaches that only target HLS directives. Therefore, we present a comprehensive methodology to support the designer in the generation of optimal HLS-based hardware implementations. First, we propose an automated roofline model generation that directly operates on a C/C++ description of the target algorithm. The approach enables a fast evaluation of the operational intensity of the target function and visualizes the main bottlenecks of the current HLS implementation, providing guidance on how to improve it. Second, we introduce a DSE methodology for quickly evaluating different HLS directives to identify an optimal implementation. We report the DSE performance when running on the PolyBench test suite, outperforming previous automated solutions in the literature. Finally, we illustrate the process of accelerating by means of our framework a complex application such as the N-body physics simulation algorithm, achieving results comparable to bespoke state-of-the-art implementations.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,paperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
one of the areas of discrete mathematics is graph theory. From a pure mathematics viewpoint, graph theory studies the pairwise relationships between objects. Those objects are vertices. Graph theory is frequently applied to analysing relationships between objects. It is a natural extension of graph theory to apply that mathematical tool to the evaluation of forensic evidence. In fact the literature reveals several, limited, forensic applications of graph theory. The current paper describes a more broad based application of graph theory to the problem of evaluation relationships in forensic investigation. The process takes standard graph theory and identifies entities in the investigation as vertices with the connections between the various entities as edges. Those entities can be suspects, victims, computer system, or any entity relevant to the investigation. Regardless of the nature of the entity, all entities are represented as vertices, and the relationship between them is represented as edges connecting the vertices. This allows the mathematical modelling of the events in question and facilitates analysis of the data.
vlsi projects using verilog code 2014-2015E2MATRIX
E2MATRIX Research Lab
Are you scratching your head to write your M Tech thesis?
Don’t know where to start and where to find the relevant matter on the topic?
We Provide Complete Thesis Help For M.Tech / Phd Studnets.
E2MATRIX deals with Thesis guidance and research work for M.Tech, PhD Students.
If you are looking for professional thesis guidance then of course you are at the right place. We have a best team of Technical Developers and professionals who specialize in developing and delivering best and authenticated work with an assurance of on time delivery.
Contact : +91 9041262727, 9779363902.
Email : support@e2matrix.com
Web : www.e2matrix.com
Implementation of Rotation and Vectoring-Mode Reconfigurable CORDICijtsrd
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. In this project A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 13.2. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by Chip Scope Pro analysis of the output logic waveforms was performed. Kothapally Mounika | P. Pavan Kumar | K. Shobha Rani"Implementation of Rotation and Vectoring-Mode Reconfigurable CORDIC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14396.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14396/implementation-of-rotation-and-vectoring-mode-reconfigurable-cordic/kothapally-mounika
Hardware simulation for exponential blind equal throughput algorithm using sy...IJECEIAES
Scheduling mechanism is the process of allocating radio resources to User Equipment (UE) that transmits different flows at the same time. It is performed by the scheduling algorithm implemented in the Long Term Evolution base station, Evolved Node B. Normally, most of the proposed algorithms are not focusing on handling the real-time and non-real-time traffics simultaneously. Thus, UE with bad channel quality may starve due to no resources allocated for quite a long time. To solve the problems, Exponential Blind Equal Throughput (EXP-BET) algorithm is proposed. User with the highest priority metrics is allocated the resources firstly which is calculated using the EXP-BET metric equation. This study investigates the implementation of the EXP-BET scheduling algorithm on the FPGA platform. The metric equation of the EXP-BET is modelled and simulated using System Generator. This design has utilized only 10% of available resources on FPGA. Fixed numbers are used for all the input to the scheduler. The system verification is performed by simulating the hardware co-simulation for the metric value of the EXP-BET metric algorithm. The output from the hardware co-simulation showed that the metric values of EXP-BET produce similar results to the Simulink environment. Thus, the algorithm is ready for prototyping and Virtex-6 FPGA is chosen as the platform.
The growing interest in FPGA-based solutions for accelerating compute demanding algorithms is pushing the need for new tools and methods to improve productivity. High-Level Synthesis (HLS) tools already provide an handy way to describe an FPGA-based hardware implementations starting from a software description of an algorithm. However, HLS directives allow to improve the hardware design only from a computational perspective, requiring a manual code restructuring in case memory transfer needs optimizing. This aspect limits the effectiveness of Design Space Exploration (DSE) approaches that only target HLS directives. Therefore, we present a comprehensive methodology to support the designer in the generation of optimal HLS-based hardware implementations. First, we propose an automated roofline model generation that directly operates on a C/C++ description of the target algorithm. The approach enables a fast evaluation of the operational intensity of the target function and visualizes the main bottlenecks of the current HLS implementation, providing guidance on how to improve it. Second, we introduce a DSE methodology for quickly evaluating different HLS directives to identify an optimal implementation. We report the DSE performance when running on the PolyBench test suite, outperforming previous automated solutions in the literature. Finally, we illustrate the process of accelerating by means of our framework a complex application such as the N-body physics simulation algorithm, achieving results comparable to bespoke state-of-the-art implementations.
Design and Implementation of Area Efficiency AES Algoritham with FPGA and ASIC,paperpublications3
Abstract: A public domain encryption standard is subject to continuous, vigilant, expert cryptanalysis. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. To implement AES Rijndael algorithm on FPGA using Verilog and synthesis using Xilinx, Plain text of 128 bit data is considered for encryption using Rijndael algorithm utilizing key. This encryption method is versatile used for military applications. The same key is used for decryption to recover the original 128 bit plain text. For high speed applications, the Non LUT based implementation of AES S-box and inverse S-box is preferred. Development of physical design of AES-128 bit is done using cadence SoC encounter. Performance evaluation of the physical design with respect to area, power, and time has been done. The core consumes 10.11 mW of power for the core area of 330100.742 μm2.
Keywords: Encryption, Decryption Rijndael algorithm, FPGA implementation, Physical Design.
one of the areas of discrete mathematics is graph theory. From a pure mathematics viewpoint, graph theory studies the pairwise relationships between objects. Those objects are vertices. Graph theory is frequently applied to analysing relationships between objects. It is a natural extension of graph theory to apply that mathematical tool to the evaluation of forensic evidence. In fact the literature reveals several, limited, forensic applications of graph theory. The current paper describes a more broad based application of graph theory to the problem of evaluation relationships in forensic investigation. The process takes standard graph theory and identifies entities in the investigation as vertices with the connections between the various entities as edges. Those entities can be suspects, victims, computer system, or any entity relevant to the investigation. Regardless of the nature of the entity, all entities are represented as vertices, and the relationship between them is represented as edges connecting the vertices. This allows the mathematical modelling of the events in question and facilitates analysis of the data.
1. 1535 N Scottsdale Rd, #2165
Tempe, AZ – 85281. SAI DHEERAJ POLAGANI
saidheeraj@ymail.com
Phone: (469)-999-2376
OBJECTIVE
EDUCATION
INDUSTRIAL
EXPERIENCE
Looking for Full-time Opportunities in ASIC Static Timing Analysis and SOC Physical Design.
Industrial Experience: 4 Years Work Authorization: STEM OPT on F1 Student VISA
San Jose State University, San Jose, California, U.S. Aug. ‘13 – May ‘15
Master of Science, Electrical Engineering GPA: 3.77/4
Coursework: Digital System Design and Synthesis, Advanced Computer Architecture.
Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT)
Gandhinagar, Gujarat, India. July, 2007 – May, 2011
B.Tech., Information and Communication Technology CGPA: 7.09/10.0
Coursework: Computer Organization, Digital System Architecture, Embedded Hardware Design
Intel Corporation, Chandler, Arizona, USA.
Physical Design Engineer (PDG) June 2015 - Present
Full-Chip Static Timing Analysis.
Guard-Banding methodology for best/worst case timing analysis.
Parametric On-Chip Variation Methodology
Simultaneous Multi Voltage Timing Analysis utilizing Unified Power Format (UPF).
Cross-Talk and Noise Analysis.
Generating constraints, maintaining scripts/methodologies to run STA and analyze the results.
Working with Physical Design Engineers to determine how failing paths should be addressed/fixed
Intel Corporation, Bangalore, India.
Layout Engineer (Contract Worker) May 2013 – July 2013
Section Layout Integration activity for Intel's next generation multi-core processor for servers.
Semiconductors and System Solutions, Wipro Technologies
Bangalore, Karnataka, India.
ASIC Physical Design Engineer June, 2011 – December 2012
Complete Semi-Custom ASIC Physical Design Flow involving Synthesis, Design Planning, IO
Planning, Floor-Planning, Power Planning, Place and Route, Clock Tree Synthesis, Timing Analysis
and Closure.
Knowledge of LEC, Electro-Migration, IR-Drop, Cross talks, Signal Integrity issues, SSO, ESD and IC
Packaging.
ASIC Physical Verification Engineer January, 2013 – April, 2013
Physical Verification at 14nm node involving DRC (Design rule check), LVS (Layout versus
Schematic), ERC (Electrical Rule Check), XOR (Exclusive OR), and Antenna Checks.
Exposure to DFM (Design for Manufacturability) techniques and Double Patterning Technology.
Double Patterning Technology - Impact on VLSI CAD, Cerebration '13, Technical Paper Symposium at
Wipro Technologies, Bangalore, India. April 2013
Programming Languages: C, C++, Verilog (HDL), PERL (Scripting), TCL
VLSI CAD: Synopsys Primetime, Synopsys IC Compiler, Synopsys Design Compiler, ModelSim, Synopsys
VCS, Cadence EDI, Synopsys Astro, Synopsys IC Validator, Matlab, Xilinx Platform Studio, Xilinx ISE.
Full Chip Timing Closure for Cable Modem IC June 2015 – May 2016
Noise Analysis and Scan Corner Closure for the Industry’s first DOCSIS 3.0 modem at 14nm.
ARM Cortex A9 Hardening Using Reference Methodology from Cadence March 2012 – July 2012
CPF driven low power - high performance design flow to achieve the highest possible frequency
exploring multiple options from RTL Synthesis to Detail Routing.
Design Compiler Topographical Synthesis Activity August 2012
Completed the feasibility analysis for migrating the RTL Code from 120MHz to 180MHz for
different Client Libraries exploring the Synopsys IC Design Compiler Topographical Methodology.
Block Level Place and Route for Mobile Communication IC October 2012 – December 2012
Place and Route for a block approximately 2500x2200um with 4M Gates using Synopsys ICC.
TECHNICAL
PRESENT’ION
SKILLS
PROJECTS
2. ACEDEMIC
PROJECTS
Netlist to Post-Route Implementation of LEON-3, Quad-Core Processor for Synopsys 90nm
Technology Generic Library. (Corporate Learning Project) November 2011 – February 2012
Performance Evaluation of Matrix Multiplication on two RTL level designs of Cache Controllers,
designed based on Intel Nehalem and AMD Opteron quad-core Cache architectures.
Master’s Program Project. August 2014 to May 2015
Hardware Design (Verilog) and Synthesis (Design Compiler) of Correlator for Direct Sequence PSK
Spread Spectrum Engine. October 2014 to December 2014
The module is designed to find the frequency and phase of a direct sequence PSK spread spectrum
(SS) signal mixed with several other SS signals below the noise floor. The design block will correlate
the ADC samples to a pseudo random number (PRN) generator. The generator provides a phase
reversal of a sin wave as modulation.
Token Passing Ring Bus Design for a System On Chip (SOC) October 2014 to December 2014
Hardware Design: The project was to connect 6 devices (Different SOC Modules viz. RTC, VIC, SSP)
together on a token passing ring bus. The project has two such rings, with each of them utilized for
different operations.
Image Warping with Affine Transformations using Homographic Matrix to Scale/Shrink/Rotate an
image. October 2014 to November 2014
Hardware Design: Image warping is the process of digitally manipulating an image such that any
shapes portrayed in the image have been significantly distorted. Warping may be used for
correcting image distortion. Image Warping revolves around geometric spatial transformations on
these images to change the position of the pixels so that the effect would be a morphed or a warped
image.
Feature Extraction (Corner Points) using Tomasi and Kanade’s Algorithm for Image Processing
Applications. October 2014 to November 2014
Hardware Design: In pattern recognition and in image processing, feature extraction is a special
form of dimensionality reduction. The project aims to design, synthesize, and simulate the working
of the feature points extraction algorithm based on Tomasi and Kanade’s Algorithm for finding
Corner Points, which is essential in various image processing applications. This algorithm employs
Prewitt Operator, to use it with the edge-detection algorithm.
Full-Search Block Matching Algorithm for Motion Estimation Using SAD (Sum of Absolute
Differences) September 2014 to October 2014
The project aims to design, synthesize, and simulate the working of the full-search block matching
algorithm which is essential in various image and video processing applications including video
stabilization, video compression, and stereo vision. The design was later pipe-lined into three-
stages with parallel SAD units to increase performance.
RGB to YCrCb Color Space Converter (CSC) August 2014 to September 2014
A CSC converts signals from one color space to another color space. The project involved
developing an nxn multiply-and-accumulate (MAC) circuit using Altera MegaWizard. The
multiplier was designed to perform Fixed Point Multiplication, where the input operands to the
MAC engine would be in 2C fractional format. The MAC engine also had a rounding and saturation
logic built in.
Decimation (2) Poly-Phase FIR Filter (Multi-Rate Filter) December 2014
Hardware Design: The Decimation Filter is actually of order of 2; which means Y (n) 2! = Y (2n).
Since, M=2, the decimation factor; the polyphase filter has two sub-filters and where the input data
can be computed paralleling across both the filters and then added for the final result. Each output
Y (n) is generated in one clock cycle employing two sub-filters parallel.
Single Cycle and 5-Stage Pipelined MIPS32 Processor Design and Synthesis, with 4KB Separate Data
and Instruction Cache including Prefetching Support. March 2014 to May 2014
Design of MIPS32 5-Stage Pipelined Processor (with Hazard Detection and Data Forwarding), with
4KB 2-Way Associative Instruction Cache and write-through, no-write allocate Data Cache.
Pipelined Cyclic Redundancy Checker (CRC-9) November 2014
Hardware Design: A Cyclic Redundancy Check (CRC) is the remainder, or residue, of binary division
of a potentially long message, by a CRC polynomial. This project presents implementation of
pipelined Cyclic Redundancy Check (CRC-9) based upon DSP algorithms of pipelining. The
architecture is pipelined to reduce the iteration bound by using novel look-ahead techniques.
Hamming Code (12,8) Encoder and Decoder Design and Synthesis March 2014 to April 2014
Design and Synthesis of Hamming Function (12, 8) to encode a byte of data using 4-parity bits and
decode data, including one-bit error correction.