This document summarizes a research paper that proposes a power gating structure using sleep transistors to reduce subthreshold leakage in a reversible programmable logic array (RPLA). It begins by introducing the concept of reversible logic for reducing power dissipation at the gate level. However, physical implementation with CMOS technology still leads to leakage during inactive periods. The paper then discusses power gating and sleep transistors as a technique to reduce leakage. It proposes a design for an RPLA using reversible AND and OR arrays with sleep transistors in a footer configuration to switch between active and sleep modes. Simulation results show 40.8% energy savings compared to a conventional CMOS design.
An Area Efficient and High Speed Reversible Multiplier Using NS GateIJERA Editor
In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.
Multiple Valued Logic for Synthesis and Simulation of Digital CircuitsIJERA Editor
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.
An Area Efficient and High Speed Reversible Multiplier Using NS GateIJERA Editor
In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
Miniaturization, cost, functionality, complexity and power dissipation are important and necessary design traits which need attention in circuit designing. There is a trade off between miniaturization and power dissipation. Smart technology is always searching for new paradigms to continue improve power dissipation. Reversible logic is one of smart computing deployed to avoid power dissipation. Researchers have proposed many reversible logic-based arithmetic and logic units (ALU). However, the research in the area of fault tolerant ALU is still under progress. The aim of this paper is to bridge the knowledge gap for a new researcher in area of fault tolerance using parity preserving logic gates rather than searching huge data through various sources. This paper also presents a high functionality based novel fault tolerant arithmetic and logic unit architecture. A comparison on optimization aspects is presented in tabular form and results shows that proposed ALU architecture is optimum balance in terms of all aspects of reversible logic synthesis. The proposed ALU architecture is coded in Verilog HDL and simulated using Xilinx ISE design suit 14.2 tool. The quantum cost of all gates used in proposed architecture is verified using RCViewer + tool.
Multiple Valued Logic for Synthesis and Simulation of Digital CircuitsIJERA Editor
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.
Efficient implementation of bit parallel finite eSAT Journals
Abstract Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2m) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation. Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
Efficient implementation of bit parallel finite field multiplierseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Abstract: Latest technological development in VLSI design permits more functions integrated in a single chip. Multipliers are crucially important building structures for advanced computing and as a part of digital processing system. These logic and arithmetic structures should have to be speedy as well as precise enough so that number of such circuits can be integrated along a single chip. Considering this there is advancement in IC fabrication and design is still going on. In VLSI circuit area, power and delay are the parameters which are considered as design parameters. However, there exists a trade-off amongst them for an optimal design. Multipliers have very crucial and important part in designing of microprocessors, multimedia system and digital signal processors etc. Almost 15% of total IC power is consumed by multiplication unit alone. So it becomes very important to have a well organized design in terms of performance, area and its processing speed of multipliers and same as for Booth multiplication algorithm which gives a fundamental platform for such improvements in the designing of high speed multipliers with great performance.
Booth algorithm gives such an efficient encoding scheme of the bits through first steps of the multiplication process. This work is based on configurable logic for 16-bit Booth multiplier using Radix-2 and Radix-4 Method. Booth multiplier can be configured to perform multiplication on 16-bit operands. The multiplier will identify the range of the operands during configuration register. The configuration register can be configured through input ports. The multiplier has been synthesized using Xilinx 14.5 and in this simulation we have achieve minimum combinational delay. Modelsim is used for the simulation part in this work.
Keywords: Radix, XPS, VHDL, Modelsim, IC fabrication, CBM, MAC, RTL, CIAF, CLA.
Title: Implementation of Radix-4 Booth Multiplier by VHDL
Author: Prof. Sneha Singh, Prachi Singh
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
ISSN 2349-7815
Paper Publications
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
Analysis, verification and fpga implementation of low power multipliereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Efficient implementation of 2 bit magnitude comparator using ptIJARIIT
Nowadays the requirements of low power electronics play a vital role in various fields. In this paper we introducing
the novel comparator is one of the fundamental units in VLSI design and also it can be employed in various applications like
Digital Signal Processors (DSP) and Data Processing, Communication Systems, Medical Electronics etc., Comparator is
involved to the most basic arithmetic operation of compression between any two variables either it maybe an equal one or
unequal. In early days, the comparator techniques used to implement energy optimization in low power circuits but the static
power dissipation need to improve the comparator using logic styles. In this paper, the 2-bit comparator has been designed by
using pass transistor logic (PTL). PTL provide good performance by reducing transistor count as well as power because PTL
logic helps in reducing the transistor count compared to other logic operation. The design was implemented in Cadence
virtuoso TMSC 180nm CMOS technology and it’s obtaining the total power dissipation 1.394μw. PTL logic is used to reduce
both transistor count and power dissipation in magnitude comparator is used to improve the good quality performance of this circuit.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
The soap based mechanism for home environment using web services ecij
Recent advancements in smart home systems have increased the utilization of consumer devices and appliances in home environment. However, many of these devices and appliances exhibit certain degree of heterogeneity and do not adapt towards joint execution of operation. Hence, it is rather difficult to perform interoperation especially to realize desired services preferred by home users. In this paper, we propose a new intelligent interoperability framework for smart home systems execution as well as coordinating them in a federated manner. The framework core is based on Simple Object Access Protocol (SOAP) technology that provides platform independent interoperation among heterogeneous
systems. We have implemented the interoperability framework with several home devices to demonstrate
their effectiveness for interoperation. The performance of the framework was tested in Local Area Network(LAN) environment and proves to be reliable in smart home setting1.
Efficient implementation of bit parallel finite eSAT Journals
Abstract Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2m) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation. Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
Efficient implementation of bit parallel finite field multiplierseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Abstract: Latest technological development in VLSI design permits more functions integrated in a single chip. Multipliers are crucially important building structures for advanced computing and as a part of digital processing system. These logic and arithmetic structures should have to be speedy as well as precise enough so that number of such circuits can be integrated along a single chip. Considering this there is advancement in IC fabrication and design is still going on. In VLSI circuit area, power and delay are the parameters which are considered as design parameters. However, there exists a trade-off amongst them for an optimal design. Multipliers have very crucial and important part in designing of microprocessors, multimedia system and digital signal processors etc. Almost 15% of total IC power is consumed by multiplication unit alone. So it becomes very important to have a well organized design in terms of performance, area and its processing speed of multipliers and same as for Booth multiplication algorithm which gives a fundamental platform for such improvements in the designing of high speed multipliers with great performance.
Booth algorithm gives such an efficient encoding scheme of the bits through first steps of the multiplication process. This work is based on configurable logic for 16-bit Booth multiplier using Radix-2 and Radix-4 Method. Booth multiplier can be configured to perform multiplication on 16-bit operands. The multiplier will identify the range of the operands during configuration register. The configuration register can be configured through input ports. The multiplier has been synthesized using Xilinx 14.5 and in this simulation we have achieve minimum combinational delay. Modelsim is used for the simulation part in this work.
Keywords: Radix, XPS, VHDL, Modelsim, IC fabrication, CBM, MAC, RTL, CIAF, CLA.
Title: Implementation of Radix-4 Booth Multiplier by VHDL
Author: Prof. Sneha Singh, Prachi Singh
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
ISSN 2349-7815
Paper Publications
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
IMPLEMENTATION OF EFFICIENT ADDER USING MULTI VALUE LOGIC TECHNIQUEJournal For Research
The digital logic circuits are restricted for the requirement of interconnections. This difficulty overcomes by using a big set of signals over the same chip area. Multiple-valued logic (MVL) designs contain more importance from that perspective. This paper gives the fabrication of a multiple-valued half adder and full adder circuits. This technique advantageous for large scale circuits due to which large power dissipation with increased speed can lead to the development of extremely low energy circuit’s use for the high performance required for number of applications. Multiple-valued logic (MVL) designs are gaining more advantageous from the design of a multiple-valued half adder and full adder circuits. The presented adders are design in Multiple-Valued voltage-Mode Logic (MV-VML). In quaternary half adder, quaternary logic levels are exploited for the intention of addition. Addition operation is executed with minimum number of gates and less depth of net. The design is targeted for the 0.18 μm CMOS technology. Circuit is design by using Advanced Design System software {ADS software}. In this paper we try to find area, power and speed of the design HAq / FAq without any need of conversion, and compare to existing binary circuits [HAb / FAb].
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
Analysis, verification and fpga implementation of low power multipliereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Efficient implementation of 2 bit magnitude comparator using ptIJARIIT
Nowadays the requirements of low power electronics play a vital role in various fields. In this paper we introducing
the novel comparator is one of the fundamental units in VLSI design and also it can be employed in various applications like
Digital Signal Processors (DSP) and Data Processing, Communication Systems, Medical Electronics etc., Comparator is
involved to the most basic arithmetic operation of compression between any two variables either it maybe an equal one or
unequal. In early days, the comparator techniques used to implement energy optimization in low power circuits but the static
power dissipation need to improve the comparator using logic styles. In this paper, the 2-bit comparator has been designed by
using pass transistor logic (PTL). PTL provide good performance by reducing transistor count as well as power because PTL
logic helps in reducing the transistor count compared to other logic operation. The design was implemented in Cadence
virtuoso TMSC 180nm CMOS technology and it’s obtaining the total power dissipation 1.394μw. PTL logic is used to reduce
both transistor count and power dissipation in magnitude comparator is used to improve the good quality performance of this circuit.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
The soap based mechanism for home environment using web services ecij
Recent advancements in smart home systems have increased the utilization of consumer devices and appliances in home environment. However, many of these devices and appliances exhibit certain degree of heterogeneity and do not adapt towards joint execution of operation. Hence, it is rather difficult to perform interoperation especially to realize desired services preferred by home users. In this paper, we propose a new intelligent interoperability framework for smart home systems execution as well as coordinating them in a federated manner. The framework core is based on Simple Object Access Protocol (SOAP) technology that provides platform independent interoperation among heterogeneous
systems. We have implemented the interoperability framework with several home devices to demonstrate
their effectiveness for interoperation. The performance of the framework was tested in Local Area Network(LAN) environment and proves to be reliable in smart home setting1.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
Parallel Processing Technique for Time Efficient Matrix MultiplicationIJERA Editor
In this paper, we have proposed one designs for parallel-parallel input and single output (PPI-SO) matrix-matrix multiplication. In this design differs by high speed area efficient, throughput rate and user defined input format to match application needs. We have compared the proposed designs with the existing similar design and found that, the proposed designs offer higher throughput rate, reduce area at relatively lower hardware cost. We have synthesized the proposed design and the existing design using Xilinx software. Synthesis results shows that proposed design on average consumes nearly 30% less energy than the existing design and involves nearly 70% less area-delay-product than other. Interestingly, the proposed parallel-parallel input and single output (PPI-SO) structure consumes 40% less energy than the existing structure.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Design of area and power efficient half adder using transmission gateeSAT Journals
Abstract This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors. Keywords: Transmission gate (TG), Half adder, CMOS logic gates, Surface area, Power.
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
Reducing power in using different technologies using FSM architectureVLSICS Design
As in today’s date fuel consumption is important in everything from scooters to oil tankers, power consumption is a key parameter in most electronics applications. The most obvious applications for which power consumption is critical are battery-powered applications, such as home thermostats and security systems, in which the battery must last for years. Low power also leads to smaller power supplies, less expensive batteries, and enables products to be powered by signal lines (such as fire alarm wires) lowering the cost of the end-product. As a result, low power consumption has become a key parameter of microcontroller designs . The purpose of this paper is to summarize, mainly by way of examples,what in our experience are the most trustful approaches to lowpower design. In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power esign; rather, we would like to provide insights a designer can rely upon when power consumption is a critical constraint.We will focus on the reduction of power consumption on different technologies for different values of oicapacitance and also compare power saving in technologies.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Electrical & Computer Engineering: An International Journal (ECIJ)ecij
Electrical & Computer Engineering: An International Journal (ECIJ) is a peer-reviewed, open access journal that addresses the impacts and challenges of Electrical and Computer Engineering. The journal documents practical and theoretical results which make a fundamental contribution for the development Electrical and Computer Engineering.
Electrical & Computer Engineering: An International Journal (ECIJ)ecij
Electrical & Computer Engineering: An International Journal (ECIJ) is a peer-reviewed,
open access journal that address the impacts and challenges of Electrical and Computer
Engineering. The journal documents practical and theoretical results which make a fundamental
contribution for the development Electrical and Computer Engineering.
Electrical & Computer Engineering: An International Journal (ECIJ)ecij
Electrical & Computer Engineering: An International Journal (ECIJ) is a peer-reviewed,
open access journal that address the impacts and challenges of Electrical and Computer
Engineering. The journal documents practical and theoretical results which make a fundamental
contribution for the development Electrical and Computer Engineering.
Electrical & Computer Engineering: An International Journal (ECIJ)ecij
Electrical & Computer Engineering: An International Journal (ECIJ) is a peer-reviewed,
open access journal that address the impacts and challenges of Electrical and Computer
Engineering. The journal documents practical and theoretical results which make a fundamental
contribution for the development Electrical and Computer Engineering
This work investigates and evaluates the electric energy interruptions to the residential sector resulting from severe power outages. The study results show that this sector will suffer tangible and intangible losses should these outages occur during specific times, seasons, and for prolonged durations. To reduce these power outages and hence mitigate their adverse consequences, the study proposes practical measures that
can be adopted without compromising the consumers’ needs, satisfaction, and convenience.
GRID SIDE CONVERTER CONTROL IN DFIG BASED WIND SYSTEM USING ENHANCED HYSTERES...ecij
The standard grid codes suggested, that the wind generators should stay in connected and reliable active and reactive power should be provided during uncertainties. This paper presents an independent control of Grid Side Converter (GSC) for a doubly fed induction generator (DFIG). A novel GSC controller has
been designed by incorporating a new Enhanced hysteresis comparator (EHC) that utilizes the hysteresis band to produce the suitable switching signal to the GSC to get enhanced controllability during grid unbalance. The EHC produces higher duty-ratio linearity and larger fundamental GSC currents with
lesser harmonics. Thus achieve fast transient response for GSC. All these features are confirmed through
time domain simulation on a 15 KW DFIG Wind Energy Conversion System (WECS).
Electrical & Computer Engineering: An International Journal (ECIJ)ecij
Electrical & Computer Engineering: An International Journal (ECIJ) is a peer-reviewed,
open access journal that address the impacts and challenges of Electrical and Computer
Engineering. The journal documents practical and theoretical results which make a fundamental
contribution for the development Electrical and Computer Engineering.
PREPARATION OF POROUS AND RECYCLABLE PVA-TIO2HYBRID HYDROGELecij
Nano TiO2, one of the most effective photocatalysts, has extensive usein fields such as air purification,
sweage treatment, water spitting, reduction of CO2, and solar cells. Nowadays, the most promising method to
recycle nano TiO2during the photocatalysis is to immobilize TiO2onto matrix, such as polyvinyl alcohol
(PVA). However, due to the slow water permeability of PVA after cross-linking, the pollutants could not
contact with nano TiO2photocatalyst in time. To overcome this problem, we dispersed calcium carbonate
particles into a PVA-TiO2 mixture and then filmed the glass. PVA-TiO2-CaCO3 films were obtained by
drying. Through thermal treatment, we obtained the cross-linked PVA-TiO2-CaCO3 films. Finally, the
calcium carbonate in the film was dissolved by hydrochloric acid, and the porous PVA-TiO2 composite
photocatalyst was obtained. The results show the addition of CaCO3 has no obvious effect on PVA
cross-linking and that a large number of cavities have been generated on the surface and inside of porous
PVA-TiO2 hybrid hydrogel film. The size of the holes is about 5-15μm, which is consistent with that of
CaCO3.The photocatalytic rate constant of porous PVA-TiO2 hybrid hydrogel film is 2.49 times higher than
that of nonporous PVA-TiO2 hybrid hydrogel film.
4th International Conference on Electrical Engineering (ELEC 2020)ecij
4th International Conference on Electrical Engineering (ELEC 2020)aims to bring together researchers and practitioners from academia and industry to focus on recent systems and techniques in the broad field of Electrical Engineering. Original research papers, state-of-the-art reviews are invited for publication in all areas of Electrical Engineering.
Electrical & Computer Engineering: An International Journal (ECIJ)ecij
Electrical & Computer Engineering: An International Journal (ECIJ) is a peer-reviewed, open access journal that addresses the impacts and challenges of Electrical and Computer Engineering. The journal documents practical and theoretical results which make a fundamental contribution for the development Electrical and Computer Engineering.
4th International Conference on Bioscience & Engineering (BIEN 2020) ecij
4th International Conference on Bioscience & Engineering (BIEN 2020) will provide an excellent International forum for sharing knowledge and results in theory, methodology and applications impacts and challenges of Bioscience and Engineering. The goal of this Conference is to bring together researchers and practitioners from academia and industry to focus on Bioscience and Engineering advancements and establishing new collaborations in these areas. Original research papers, state-of-the-art reviews are invited for publication in all areas of Bioscience and Engineering.
Electrical & Computer Engineering: An International Journal (ECIJ)ecij
Scope & Topics
Electrical & Computer Engineering: An International Journal (ECIJ) is a peer-reviewed, open access journal that addresses the impacts and challenges of Electrical and Computer Engineering. The journal documents practical and theoretical results which make a fundamental contribution for the development Electrical and Computer Engineering.
Electrical & Computer Engineering: An International Journal (ECIJ)
ISSN: 2201-5957
https://wireilla.com/engg/ecij/index.html
Paper Submission
Authors are invited to submit papers for this journal through E-mail: ecijjournal@wireilla.com .
Important Dates
•Submission Deadline: March 28, 2020
Contact US
Here's where you can reach us: ecijjournal@wireilla.com
GRID SIDE CONVERTER CONTROL IN DFIG BASED WIND SYSTEM USING ENHANCED HYSTERES...ecij
The standard grid codes suggested, that the wind generators should stay in connected and reliable active and reactive power should be provided during uncertainties. This paper presents an independent control of Grid Side Converter (GSC) for a doubly fed induction generator (DFIG). A novel GSC controller has been designed by incorporating a new Enhanced hysteresis comparator (EHC) that utilizes the hysteresis band to produce the suitable switching signal to the GSC to get enhanced controllability during grid unbalance. The EHC produces higher duty-ratio linearity and larger fundamental GSC currents with lesser harmonics. Thus achieve fast transient response for GSC. All these features are confirmed through time domain simulation on a 15 KW DFIG Wind Energy Conversion System (WECS).
UNION OF GRAVITATIONAL AND ELECTROMAGNETIC FIELDS ON THE BASIS OF NONTRADITIO...ecij
The traditional principle of solving the problem of combining the gravitational and electromagnetic fields is associated with the movement of the transformation of parameters from the electromagnetic to the gravitational field on the basis of Maxwell and Lorentz equations. The proposed non-traditional principle
is associated with the movement of the transformation of parameters from the gravitational to the electromagnetic field, which simplifies the process. Nave principle solving this task by using special physical quantities found by M. Planck in 1900: - Planck’s length, time and mass), the uniqueness of which is that they are obtained on the basis of 3 fundamental physical constants: the velocity c of light in vacuum, the Planck’s constant h and the gravitational constant G, which reduces them to the fundamentals of the Universe. Strict physical regularities were obtained for the based on intercommunication of 3-th
fundamental physical constants c, h and G, that allow to single out wave characteristic νG from G which is identified with the frequency of gravitational field. On this base other wave and substance parameters were strictly defined and their numerical values obtained. It was proved that gravitational field with the given wave parameters can be unified only with electromagnetic field having the same wave parameters that’s why it is possible only on Plank’s level of world creation. The solution of given problems is substantiated by well-known physical laws and conformities and not contradiction to modern knowledge about of material world and the Universe on the whole. It is actual for development of physics and other branches of science and technique.
USING MACHINE LEARNING TO BUILD A SEMI-INTELLIGENT BOT ecij
Nowadays, real-time systems and intelligent systems offer more and more control interface based on voice recognition or human language recognition. Robots and drones will soon be mainly controlled by voice. Other robots will integrate bots to interact with their users, this can be useful both in industry and entertainment. At first, researchers were digging on the side of "ontology reasoning". Given all the technical constraints brought by the treatment of ontologies, an interesting solution has emerged in last years: the construction of a model based on machine learning to connect a human language to a knowledge
base (based for example on RDF). We present in this paper our contribution to build a bot that could be used on real-time systems and drones/robots, using recent machine learning technologies.
MODELING AND SIMULATION OF SOLAR PHOTOVOLTAIC APPLICATION BASED MULTILEVEL IN...ecij
As the solar market is blooming and forecasted to continue this trend in the coming years. The efficiency and reliability of PV based system has always been a contention among researchers. Therefore, multilevel inverters are gaining more assiduity as it has multitude of benefits. It offers high power capability along with low output harmonics. The main disadvantage of MLI is its complexity and requirement of large
number of power devices and passive components. This paper presents a topology that achieves 37.5% reduction in number of passive components and power devices for five-level inverter. This topology is basically based on H-bridge with bi-directional auxiliary switch. This paper includes a stand-alone PV system in which designing and simulation of Boost converter connected with multilevel inverter for ac load is presented. Perturb and observe MPPT algorithm has been implemented to extract maximum power. The premier objective is to obtain Voltage with less harmonic distortion economically. Multicarrier Sinusoidal
PWM techniques have been implemented and analysed for modulation scheme. The Proposed system is simulated n MATLAB/Simulink platform.
Investigation of Interleaved Boost Converter with Voltage multiplier for PV w...ecij
This paper depicts the significance of Interleaved Boost Converter (IBC) with diode-capacitor multiplierwith PV as the input source. Maximum Power Point Tracking (MPPT) was used to obtain maximum power from the PV system. In this, interleaving topology is used to reduce the input current ripple, output voltage ripple, power loss and to suppress the ripple in battery current in the case of Plugin Hybrid Electric Vehicle (PHEV). Moreover, voltage multiplier cells are added in the IBC configuration to reduce the narrow turn-off periods. Two MPPT techniques are compared in this paper: i) Perturb and Observe (P&O) algorithm ii) Fuzzy Logic . The two algorithms are simulated using MATLAB and the comparison of performance parameters like the ripple is done and the results are verified.
A COMPARISON BETWEEN SWARM INTELLIGENCE ALGORITHMS FOR ROUTING PROBLEMSecij
Travelling salesman problem (TSP) is a most popular combinatorial routing problem, belongs to the class of NP-hard problems. Many approacheshave been proposed for TSP.Among them, swarm intelligence (SI) algorithms can effectively achieve optimal tours with the minimum lengths and attempt to avoid trapping in local minima points. The transcendence of each SI is depended on the nature of the problem. In our studies, there has been yet no any article, which had compared the performance of SI algorithms for TSP perfectly. In this paper,four common SI algorithms are used to solve TSP, in order to compare the performance of SI algorithms for the TSP problem. These algorithms include genetic algorithm, particle swarm optimization, ant colony optimization, and artificial bee colony. For each SI, the various parameters and operators were tested, and the best values were selected for it. Experiments oversome benchmarks fromTSPLIBshow that
artificial bee colony algorithm is the best one among the fourSI-basedmethods to solverouting problems like TSP.
Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAY
1. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
DOI : 10.14810/ecij.2015.4301 1
POWER GATING STRUCTURE FOR REVERSIBLE
PROGRAMMABLE LOGIC ARRAY
Pradeep Singla
Faculty of Engineering,
Asia-Pacific Institute of Information Technology, SD India
ABSTRACT
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of
power dissipation in low power VLSI systems. This paper presented an idea of using the power gating
structure for reducing the sub threshold leakage in the reversible system. This concept presented in the
paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for
the digital systems, the energy can be saved up to the gate level implementation. But at the physical level
designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array
(RPLA) is one of the important parts of the low power industrial applications and in this paper the physical
design of the RPLA is presented by using the sleep transistor and the results is shown with the help of
TINA- PRO software. The results for the proposed design is also compare with the CMOS design and
shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the
switching activity and showing that the proposed design is much better that the modern CMOS design of
the RPLA.
KEYWORDS
Reversible programmable logic array, Sleep Transistors, Power gating, MUX gate, Feynman gate,
Reversible logics, TINA- PRO
1. INTRODUCTION
With the growing demands of the prominence portable systems, there are a rapids and innovative
developments in the low power designs of the very large scale integration chips during the recent
years [7]. The power dissipation or the energy consumption is one of the major obstacles for the
Low power electronic design industries [4] [5]. For a low power digital hardware design, the
researchers/ scientists are struggling for overcoming such a limiting factor/ obstacle and
proposing different ideas and designing methods from the logical level ( Gate Level) to circuitry
level (Physical level) and above[6]. Even after of such a struggle, there is no any universal
method to design to avoid trade-off between delay, power consumption and complexity of the
circuit. Still, the designer is required to opt. appropriate technology for satisfying product need
and applications [6].
In case of the gate level implementation, reversible computing is one of the growing technologies
for reducing the power dissipation [3]. The concept of the reversibility in the digital hardware
2. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
2
design for the low power design basically came from the “Thermodynamics” which taught us the
benefits of the reversible systems over the irreversible systems. The irreversible system design
OR the system designed conventional approach consumes heat of equal to KTln2 on computation
of every bit stated by Rolf Landauer, in 1961. Where K denotes the Boltzmann’s constant which
is equal to numerical value of 1.38 × 10ିଶଷ
m2
kg2
k-1
(J/K) and T is the temperature at which the
logical computation is performed [1]. Even in 1973, Bennet correlate this heat loss with the
information lost and stated the heat can be saved by using the reversible logics which does not
dissipates heat [2]. So, this technique is best suitable for the logical / gate level implementation of
the digital hardware. The ref. [3] showed the reversible design of the Programmable logic array
called RPLA (Reversible programmable logic Array).
For a designing of the hardware, the circuit/ transistor/physical level implementation is further
process of design. Today’s Modern CMOS technology is used to design the system at transistor
level and the scaling down of the feature size of the VLSI chips leads to improve the
performance of the system. But, these technologies of the threshold voltage scaling down and
decreasing feature size leads to the increment in the transistor leakage power with the exponential
rate [9]. As the feature size becomes smaller, the length of the induced channel becomes shorter
resultant sub threshold leakage current when the transistor is off.
Multi-Threshold CMOS OR Power gating technique is one of the prominent techniques by which
the leakage current in the low power circuits in standby mode/ at the time of inactivity can be
reduced[8]. In the design of power gating, multi-threshold CMOS has been introduce with the
low & high threshold Voltage ( V୲୦) unit linked to the ground and to power supply respectively
called sleeps transistors as shown in fig.1 [10]
Figure1. Power gating structure
There are two operational modes of Multi-Threshold CMOS technique for the saving of power or
reducing the power dissipation named active and sleep. In this technique, the low threshold
voltage logic device from power supply and the ground via sleep transistor is used so, this
technique is also known as power gating [10].
The Programmable logic array (PLA) is the one of the yardstick that provides customers a wide
range of voltage characteristics, logic capacity & speed [10]. There of numbers of applications of
PLA’s like ultrasonic flow detection, DSP’s etc. Even the PLA’s are faster than the high speed
DSP’s [11]. The programmable logic array has many applications in the medical and industrial
field also. In the Reference paper 3 written by the same author already showed the cost- effective
design of RPLA for the low power design by using the reversible logics and ensures that design
does not dissipates heat called Reversible programmable logic array (RPLA) [3]. So, with the
huge numbers of benefits of the RPLA (Reversible Programmable logic array) design over the
conventional PLA design, a power efficient design of reversible programmable logic array for the
3. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
3
low power industrial applications by using the multi threshold distributed sleep transistor network
at circuit level implementation is proposing in this paper. In order to make obvious the proposed
architecture of power efficient RPLA, a 3- input RPLA which be capable of performing any 2ଷ
functions using the combination of 8 min terms is also designed and match up to the result with
the conventional CMOS-RPLA by using the simulator TINA-PRO. The proposed low power
reversible PLA be able to implement numbers of Boolean functions like adder/subtractor and it
can be transformed to perform desired function. The transient response or the spikes generation in
the proposed design is also discussed.
2. BACKGROUND
This section provides the complete background of the technology used in the proposed design.
This paper shows the physical design of the RPLA constituting by two major technologies:
Reversible logics and Power gating.
2.1. Overview of Reversible logics
This part of the section 2 provides the brief of the reversible gates used in the reversible
programmable logic design. According to the theory of the reversibility in the digital logics, the
logic must have the equal number of inputs and outputs and they must be bijective. That means,
an p×q of reversible gate consisting of p inputs and q outputs with design of each input
assignment to a unique output assignment and vice versa OR there is one- to- one mapping from
the inputs to the outputs and vice- versa[5] and p=q [4]. There are varieties of the reversible gates
like Feynman gate (FG), Toffolli gate (TG), Fredkin gate (FRG), Peres gate (PG), New gate (NG,
MKG, HNG and TSG, MG) [3]. Without discussing the all reversible gates, this paper describe
only the MUX gate and Feynman gate as both gates with changed configuration are used in the
RPLA.
2.1.1 Feynman Gate
The 2×2 reversible gate shown in Fig.2 called Feynman gate [2]. This gate is also documented as
controlled- not gate (CNOT) having two inputs (A, B) and two outputs (P, Q). The outputs are
defined by P=A, Q=A XOR B .To copy a signal, this gate can be used in the design to remove
fan-out as fan-out is not permitted in reversible logic circuits. Quantum cost of a Feynman gate
is 1.
Fig.2. 2×2Feynman gate structure
2.1.2 MUX Gate
The pictorial representation of 3×3 reversible gate MUX (MG) gate is shown in Fig.3 [3]. This
gate is a conservative gate having three inputs (A, B, C) and three outputs (P, Q, R). The outputs
of the gate are defined by P=A, Q=A XOR B XOR C and R= A’C XOR AB. Its Quantum cost is
4.
4. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
4
Fig.3: 3×3 MUX gate
So, these are the reversible logic gates which have been used in the RPLA design at the gate level
implementation for reducing power consumption.
2.2 Overview of Power gating
This part of the section 2 provides the useful detail to understand the factors by which the power
is dissipated in the systems and the power gating technique to reduce sub threshold leakage.
There are PMOS and NMOS transistors in the CMOS (Complementary metal oxide
semiconductor) design of the circuits as pull-up and pull-down and both the transistors
contributing equally in the circuit operation [5] & the major cause of power dissipation in the
digital circuits are following [5][6][7][10]:
Dynamic or switching power consumption due to capacitance charging and discharging.
Short circuit power consumption due to energy require to charge up the parasitic load capacitance
in the circuit.
The Leakage power consumption :
Static power consumption which is due to circuit present in the system which is other than the
CMOS and providing a current flow from power supply to ground constantly.
The total power dissipation in CMOS digital circuits can be expressed as the sum of four
components,
Pୟ୴. = Pୱ + Pୱ.ୡ. + P୪ୣୟ୩ୟୣ = α→ଵC୪. Vଶ
ୢୢ . fୡ୪୩ + Iୱ.ୡ.. Vୢୢ + I୪ୣୟ୩ୟୣ. Vୢୢ + Iୱ୲ୟ୲୧ୡ. Vୢୢ
In the above equation C୪ is the load capacitance, fୡ୪୩ is the clock frequency, α→ଵ is the
probability that a power consuming when transition occurs, Iୱ.ୡ. is the short circuit current (when
both nmos and pmos active), I୪ୣୟ୩ୟୣ is the leakage current arises from sub threshold effects.
Sleep Transistor
Sleep transistor uses in the design is one of the emergent techniques to reduce the subthreshold
leakage at the time of inactivity of the system OR when the system is not operation [12] [15].
Here the term, Sub threshold leakage which is used for one of the power dissipation whose cause
is the carrier diffusion between the source and the drain region of the transistors in weak
inversion and the amount of the sub threshold current might become considerable when the gate
to source voltage is slighter than but very close to the threshold voltage of the device [12]. A
sleep transistor is generally may be of PMOS or NMOS but with the high threshold voltage (V୲୦)
value. So, the sleep transistor is a PMOS or NMOS transistor of high (V୲୦)which is placed in
series with a low V୲୦ device unit. In the power gating design, circuit operates in two different
modes [12]
Active Mode
In this mode, the sleep transistor used in the design is turned ON and acts as the functional
redundant resistance
5. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
5
Sleep Mode
This is the mode, in which the sleep transistor is turned OFF to reduce dynamic and leakage
power in the standby mode.
When a sleep transistor is placed near Vdd, then called header switch and when a sleep transistor
put near to the ground, called footer switch as shown in fig.5 (a), fig.5 (b).
Fig 5(a) Header Switch
Fig.5 (b) Footer Switch
The figures are for the header and footer configurations and the PMOS is used for implementing
the header switch putted close to Vdd for controlling the supply and the NMOS is to control
GND, putted close to GND. The PMOS transistor is a smaller amount of leaky than the NMOS
transistor and PMOS also has lower drive current than the NMOS transistor [15]. Due to these
situations, PMOS takes more area than the NMOS which is not an interest or expectation for the
very large scale integration. So, with these benefits of the NMOS i.e. footer switch of high drive
current & smaller area over the PMOS, this paper considering the footer switch only for the
proposed design.
Analysis of Footer Switch
This particular subsection describes the connection between ground voltage and the leakage
saving. For the relationship, a footer switch same as shown in fig 5(b) is taken which is biased in
the weak inversion i.e. V<V୲୦ [16]. the leakage of the single transistor provides the leakage of
the logic circuit [11].
So,
I୪ୣୟ୩ୟୣ (circuit) = I୪ୣୟ୩ୟୣ(Footer)
But
6. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
6
I୪ୣୟ୩ୟୣ = I୭ (
) 10
൬ౝష ౪)
൰శ η( ౚ౩)
for the logic circuit
…………….(1)
So, equation becomes
I୭ (
ୡ୧ୡ୳୧୲
) 10
(ష౪ౙ)శ η( ౚౚషౝౚ)
= I୭ (
୭୭୲ୣ୰
) 10
ቀౝష ౪ూ
ቁశ η( ౚ౩)
………….. (2)
Vthc and VthF shows the threshold voltage of the logic circuit and the footer device resp., is the
Drain induced barrier lowering ( a secondary effect) coefficient and ss is the sub threshold slope.
After solving eq 2.
= ……..(3)
The equation 3 shows that Vgnd is proportional to the gate voltage Vg with negative slope. So, if
the footer gate voltage is increased, there is decrease in the ground potential and vice-versa.
To make the trade-off between leakages saving and wakeup- overhead, the control over Vgnd
should be needed. So,
= …..(4)
So, by the above terms, higher Vgnd results in higher leakage saving.
3. PROPOSED IMPLEMENTATION
The RPLA consists of Reversible AND array and Reversible OR arrays shown in fig. 6
Fig 6 Proposed RPLA with Sleep Transistors
7. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
7
This architecture shows the Reversible AND array having n numbers of inputs which will
provide the k product term. The product terms are fed to the Reversible OR array as its inputs and
provide the sum of product. Sleep transistors are used in the internal structure of each array with
footer configuration and by this architecture the user can easily vary this structure according to
the expected Boolean function at any time. In this work, the example of 3- input PLA is taking
into consideration for which three inputs are provided to the Reversible AND array and this will
provide us eight- min terms or product terms. The Reversible OR gate will perform for the 8- min
terms which again provide the sum of those.
3.1 Design of RPLA by sleep transistors
For the proposed design the TINA-PRO simulator is used. TINA Design suit is a great yet
reasonable software package for analyzing, designing and real time testing of analog, digital,
VHDL, and mixed electronic circuits and their layouts. For the simplicity, the macro of the each
component of the RPLA is designed by using the power gating structure. The RPLA has two
basic plane i.e. Reversible AND Plane and OR Plane. These two planes consisting of AND OR
structures of the reversible gates respectively. The reversible AND plane of the RPLA consists of
Feynman and MUX gates and reversible OR plane consists of MUX gate only. These gates
contain the NOT, AND XOR functions. So, in starting the Macros of each gate is defined and
then connected in a predefined manner. The complete Macros of the Feynman gate and MUX
gate is shown in fig. 7.1 & 7.2 respectively.
Fig. 7.1 Macro of Feynman gate with sleep transistor
8. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
8
Fig. 7.2 Macro of MUX gate with sleep transistors
4. POWER CONSUMPTION MEASUREMENT
The wattmeter is used for measurement of the power dissipation in the array. VF1-VF8 is the
output voltages and PM1- PM3 is power measurement wattmeter. The fig.8 (a) shows the
complete structure of power measurement of Reversible AND array. And fig.8 (b) for reversible
OR array.
V55
+
+W
PM2
+
+W
PM3
SL
SL
SL
+
+W
PM1
VF2
VF3
+
VG1
+
VG2
+
VG3
SL'
P
Q
R
A
B
C
Vdd
10. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
10
Fig. 8(b) Power measurement setup for Reversible OR array
5. RESULTS
This section describes the analysis of the performance of the proposed design using TINA- PRO.
For analyzing the parameters like power consumption and transient response, Let consider the
input values A, B, & C are at logic 1 or +5V unit step.
5.1 Power Analysis
For the power analysis, comparison of the results for the sleep transistors RPLA with the RPLA
designed by the conventional CMOS technology is shown in table 1 below.
Table 1 Power consumption comparison between CMOS-RPLA & SL RPLA
Input
Ve
cto
r
ABC
Power Consumed(pW)
CMOS- RPLA
Proposed
SL- RPLA
PM1 PM2 PM3 PM1 PM2 PM3
000 0 0 0 0 0 0
001 0 0 221.91 0 0 90.57
010 0 221.92 0 0 90.57 0
011 0 221.92 221.91 0 90.57 90.57
100 187.71 0 0 90.57 0 0
101 187.71 0 221.91 90.57 0 90.57
110 187.71 221.92 0 90.57 90.57 0
111 187.71 221.92 221.91 90.57 90.57 90.57
The PM1, PM2 & PM3 are the three watt meters connected on the input side at three inputs line
(ABC). From the table we can see that when the input vector is at logic level 1 or high then the
power consumption In the CMOS- RPLA is 187.71- 221.92 and the power consumption in the
11. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
11
RPLA designed by the proposed technology is 90.57. From the analysis table it is apparent that
there is a 40.8% saving of energy by using the power gating in the design.
5.2 Transient Response Analysis
"Transients", a term we'll use for simplicity here, are actually "Transient Voltages". More
familiar terms may be "surges" or "spikes". Basically, transients are momentary changes in
voltage or current that occurs over a short period of time. Generally in the systems, there are two
kinds of analysis:
The DC analysis: Which tells Vout if Vin is constant?
Transient analysis: Which tells Vout(t) if Vin(t) changes.
This analysis used to measure the behavior of the circuits at the time of switching.
The comparable Transient response of the Conventional CMOS RPLA and Proposed SL- RPLA
are shown below.
Fig. 9 (a) Transient Response of the Line A for CMOS- RPLA
Fig. 9 (b) Transient Response of the Line B for CMOS- RPLA
12. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
12
Fig. 9(c) Transient Response of the Line C for CMOS- RPLA
Fig. 9(d) Transient Response of the Line A for Proposed- RPLA
Fig. 9(e) Transient Response of the Line B for Proposed- RPLA
13. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
13
Fig. 9(f) Transient Response of the Line C for Proposed- RPLA
From the Power consumption measurement results of proposed technology against the
conventional CMOS technology, it is clear that the sleep transistor saves the approx. 40.8% of the
energy and from the transient response of the different lines of the proposed RPLA against
CMOS- RPLA, it is conclude that the spikes generates at the time of very short period is approx.
440nW for the SL-RPLA structure and for CMOS- RPLA it is 1.1 uW. So, the less amplitude
spike generates means more stability in the system.
So, by these transient responses and the power consumption measurement, it is clear that the
proposed technology of the multi-threshold transistor or Power gating for the reversible
programmable logic array design is superior and efficient for saving the energy which is
dissipated by the sub-threshold leakage at the time of inactivity.
6. CONCLUSION
Reversible computing is one of the powerful technologies to reduce power consumption at the
gate level implementation but at the physical level design, in nanometer scale CMOS technology,
sub threshold leakage power is also one of the great challenge in front of the circuit designer.
This paper, presented a new circuit design named “Power gating structure” to tackle the leakage
problem which uses the sleep transistors. In this paper, the complete concept of the power gating
with the footer switch has been explained and used this concept for the designing of RPLA at the
transistor level. The design architecture of the RPLA at the transistor level is done by TINA- 8
software. The power consumption comparison for both the technique i.e. CMOS- RPLA and the
SL- RPLA has been also shown in the paper and showing the results for the proposed technique
is better than the CMOS technique. The proposed technique for the physical level design of
RPLA saves the 40.8% of the power consumption as compares to the CMOS technology. For the
analyzing if the switching activity, the transient response has also been shown for the proposed
RPLA. The transient response results for the proposed RPLA show the spikes produced by the
proposed design are less than the CMOS – RPLA. The spikes generates for the proposed
MTCMOS- RPLA is of 440nW which is less comparable to the CMOS-RPLA having 1.20uW.
REFERENCES
[1] Pradeep Singla, “Reversible squaring Circuit for Low Power digital Signal Processing”, Journal of
Engineering Science and Technology Review, Vol.7, Issue 3, pp 50- 54, 2014
[2] Mahshid Tayari, MD.Eshshi, “Design of 3-input reversible programmable logic array” JCcircuit Syst
Comp,Volume 20, Issue 02, April 2011.
14. Electrical & Computer Engineering: An International Journal (ECIJ) Volume 4, Number 3, September 2015
14
[3] R. Landauer, ‘‘Irreversibility and heat generation in the computational process’’, IBM J. Res.
Develop., vol. 5 pp.183-191, 1961.
[4] C. H. Bennet, “Logical reversibility of computation”, IBM J. Res. Develop., vol. 17, no. 6, pp. 525-
532, 1973.
[5] Pradeep Singla and Naveen Kr. Malik, “A cost- effective design of reversible programmable logic
array”,International Journal of Computer applications Vol.41 (15), pp.41-46, 2012.
[6] Majid Haghparast, Majid Mohammadi, Mohammad Eshghi, “Optimized reversible Multiplier
circuit”, Journal of circuits, system and computers, pp 1-13.
[7] G. M. Blair, “Designing low power CMOS “, Electron. Comm... engg. Journal, 1994, Vol.6 (5), pp
229-236.
[8] Y. Taur and T. Ning, “Fundamentals of Modern VLSI Devices”, Cambridge University Press, 1998.
[9] P. Uyemura, Introduction to VLSI Circuits and Systems. New York: Wiley, 2002.
[10] The “International Technology Road map of semiconductor” ITRS, pp 61-66, 2005.
[11] Abdullah A, Fallah F, and Pedram M, (Jan 2007) “ A robust power gating structure and power mode
transition strategy for MTCMOS design” IEEE Trans. Very large Scale integration., vol. 15, No 1,
pp.80-89.
[12] Changbo Long and L. He., “Distributed sleep transistor network for power reduction,” IEEE Trans.
Very large scale integer”, vol. 12, no. 9, pp. 937-946, Sep 2004.
[13] Pradeep Singla, Kamya Dhingra, Naveen Kr. Malik, “ DSTN( Distributed Sleep Transistor Network)
for Low power Programmable logic array design”, International Journal of Computer applications,
Vol.17(15), pp. 41-46, May 2012
[14] Jun Cheol Park, “Sleepy Stack: a New Approach to Low Power VLSI Logic and Memory” , Ph. D
Thesis, Georgia Institute of Technology, August 2005
[15] S. Mutoh et al., “1-V power supply high speed digital circuits technology with multithreshold voltage
CMOS,” JSSC, vol. SC-30, pp. 847-854, Aug. 1995.
[16] Dongwoo Lee, David Blaauw, and Dennis Sylvester, “Gate oxide leakage current analysis and
reduction for VLSI circuits”, - IEEE Trans. VLSI, Vol. 12, No. 2, Feb. 2004
[17] Satoshi Shigematsu et. al., “A 1-V high-speed MTCMOS circuit scheme for power-down application
circuits”,IEEE J.Solid-State Circuits, vol. 32, no. 6, June, 1997
[18] Benton H Calhoun, Frank A Honore and Anantha P Chandrakasan, “A leakage reduction
methodology for distributed MTCMOS”, IEEE J. Solid-State Circuits, vol. 39, no. 5, May, 2004, pp.
818-826
[19] Anand Ramalingam, Bin Zhang, Anirudh Davgan and David Pan, “Sleep Transistor Sizing Using
Timing Criticality and Temporal Currents”, Proc. ASP-DAC, 2005
[20] Kaijian Shi, “Sleep transistor design in 28nm CMOS technology” IEEE 26th Internation SOC
conference, pp 278-283, Sept., 2013
[21] Upadhyay, P. et al, “Low static and dynamic power MTCMOS based 12T SRAM cell for high speed
memorysystem” 11th International joint conference on computer science and software engineering,
pp 212-217, May, 2014.
[22] Rastogi, R. Et al, “Implementing low-power dynamic adders in MTCMOS technology”, 2nd
International conference on Electronics and Communication, pp 782-786, 2015.