This document reviews reversible logic gate design for low power VLSI circuits. It discusses how reversible logic gates can dissipate near-zero power by recovering the output from the input. Common reversible logic gates like Feynman, Fredkin, and Peres gates are described along with their functions. As an example, a full adder circuit is designed using Peres gates to demonstrate how reversible logic can reduce power consumption compared to traditional logic. Simulation results show the reversible adder has lower quantum cost and delay than other reversible adders. In conclusion, reversible logic gates are a promising technique for low-power VLSI design.