An Area Efficient and High Speed Reversible Multiplier Using NS GateIJERA Editor
In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
Design and Performance Analysis of 8 x 8 Network on Chip RouterIRJET Journal
This document describes a study that designed and analyzed the performance of an 8x8 network-on-chip router. The researchers implemented a 2D mesh network-on-chip router with four ports connected in each of the four directions (north, south, east, west) and a fifth port connected to a local processing element. The goal was to improve quality-of-service by employing algorithms like wormhole routing, arbitration, and crossbar switching. The router architecture and modules were designed and synthesized using Xilinx ISE to optimize for lower power consumption while maintaining high throughput and quality-of-service.
An Area Efficient and High Speed Reversible Multiplier Using NS GateIJERA Editor
In digital computer system a major problem has been found that the Power dissipation which leads to bring some research on the methods to decrease this Area efficient, high speed. This is the main cause to give birth to reversible computing systems for digital computers and designs. Reversible computing is the path to future computing technologies, which all happen to use reversible logic. In addition, reversible computing will become mandatory because of the necessity to decrease power consumption. Reversible logic circuits have the same number of inputs and outputs, and have one-to-one mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. Consequently, a computation is reversible, if it is always possible to uniquely recover the input, given the output. Each gate can be made reversible by adding some additional input and output wires if necessary. The main aim of this reversible computing is to lower the power dissipation, area efficient and high speed and some other advantages like security of data and prevention of errors etc... Reversible logic has so many applications low power CMOS, nanotechnology, DNA computing and quantum computing. There are two primary design implementations in this study which are the major spotlights. The first one is reversible design gate and the second one is multiplier design using reversible gates. In this manuscript we have implemented a 8 * 8 reversible design called “NSG(Non linear Sign Flip)”. The total project is implemented in Xilinx 14.7 ISE with Spartan 3E family.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Programmable reversible logic is growing for a potential logic design type
concerning execution around advanced nanotechnology as well as quantum computing
with minimum effect upon circuit temperature production. Current improvements in
reversible logic utilizing additionally quantum computer calculations permit enhanced
computer structure plus arithmetical logic unit layouts. Since reversible circuits
continue to be fairly unique, the most significant study effect is found on the synthesis
of these circuits. Quantum-dot cellular automata (QCA) can be a promising part of
investigating at reversible computing. QCA-based design of the reversible 1-bit full
adder is using the Toffoli and Feynman gates have been achieved in this study. We
develop an improved reversible full adder with overflow detection to enhance
reliability. This component promises to complete the fundamental mathematical
functions of addition, subtraction alongside overflow detection, comparison, along with
logic procedures such as significance. Thus our design is very efficient and versatile
alongside lower quantity of lines as well as quantum cost. This work understands and
nurtures the necessity of reversible full adder for future revolutionary computing
technologies. In this paper, a reversible 1-bit full adder is proposed and compared with
other reversible full adders. Proposed gate performs better than existing methods and
ensures maximum logical operations like the full adder, full with less quantum cost
where other existing gates are not viable.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL A...VLSICS Design
Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.
Design and Performance Analysis of 8 x 8 Network on Chip RouterIRJET Journal
This document describes a study that designed and analyzed the performance of an 8x8 network-on-chip router. The researchers implemented a 2D mesh network-on-chip router with four ports connected in each of the four directions (north, south, east, west) and a fifth port connected to a local processing element. The goal was to improve quality-of-service by employing algorithms like wormhole routing, arbitration, and crossbar switching. The router architecture and modules were designed and synthesized using Xilinx ISE to optimize for lower power consumption while maintaining high throughput and quality-of-service.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
This document summarizes a research paper that proposes a power gating structure using sleep transistors to reduce subthreshold leakage in a reversible programmable logic array (RPLA). It begins by introducing the concept of reversible logic for reducing power dissipation at the gate level. However, physical implementation with CMOS technology still leads to leakage during inactive periods. The paper then discusses power gating and sleep transistors as a technique to reduce leakage. It proposes a design for an RPLA using reversible AND and OR arrays with sleep transistors in a footer configuration to switch between active and sleep modes. Simulation results show 40.8% energy savings compared to a conventional CMOS design.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array (RPLA) is one of the important parts of the low power industrial applications and in this paper the physical design of the RPLA is presented by using the sleep transistor and the results is shown with the help of TINA- PRO software. The results for the proposed design is also compare with the CMOS design and shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the switching activity and showing that the proposed design is much better that the modern CMOS design of the RPLA.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
Review On 2:4 Decoder By Reversible Logic Gates For Low Power ConsumptionIRJET Journal
This document summarizes a research paper that proposes designing a 2:4 decoder using reversible logic gates to reduce power consumption. Reversible logic gates use minimal power by only employing buffers instead of traditional CMOS gates. The document provides background on reversible gates and decoders, reviews previous work on low-power decoder designs, and proposes a reversible gate-based 2:4 decoder design to reduce overall system power consumption compared to a standard CMOS implementation. Simulation results from other studies show reversible gate designs can achieve up to 26% power reduction for instruction decoding. The proposed design aims to lower delay and gate count while minimizing power.
Area Efficient Pulsed Clock Generator Using Pulsed Latch Shift RegisterIJMTST Journal
The document describes a proposed area efficient pulsed clock generator using pulsed latch shift registers. Conventional shift registers use flip-flops which consume more power and area than latches. The proposed design uses pulsed latches instead of flip-flops to reduce power consumption and area. It solves the timing problem of using latches in shift registers by generating multiple non-overlapping delayed pulsed clock signals. Simulation results show the proposed shift register reduces power consumption by 27% and delay by 21% compared to a conventional flip-flop based shift register.
Adiabatic technique based low power synchronous counter designIJECEIAES
The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.
Circuit Approaches for VLSI in Internet-of-Things ApplicationsIRJET Journal
This document discusses circuit approaches for VLSI in Internet-of-Things applications. It describes two proposed circuits: (1) An ultra-compact and robust physically unclonable function (PUF) circuit based on temperature sensors, and (2) A method to transform SRAM arrays into robust analog PUFs with minimal overhead. It also discusses challenges with power management in IoT devices and proposes a capacitor-buffered hybrid energy storage solution for energy harvesting power management units.
IRJET- Sink Mobility based Energy Efficient Routing Protocol for Wireless Sen...IRJET Journal
The document describes a proposed sink mobility based energy efficient routing protocol for wireless sensor networks. The protocol uses both a static centralized sink and a mobile sink that follows a predetermined path with 4 sojourn locations. This is aimed to improve network lifetime by balancing energy load across nodes. Simulation results show that the proposed approach with a mobile sink performs better than the Threshold sensitive Energy Efficient sensor Network (TEEN) protocol alone in terms of number of alive nodes, number of cluster heads, and number of packets sent to the base station over multiple rounds. Using a mobile sink helps scatter the energy load in the network and extends lifetime compared to only using a static sink.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
IRJET- FPGA Implementation of Efficient Muf Gate based MultipliersIRJET Journal
This document discusses the FPGA implementation of efficient multiplier circuits using reversible MUF gates. It begins with background on reversible logic and the benefits of reducing heat dissipation. A reversible MUF gate is proposed that can realize basic logic functions with unique input-output mappings. Array, systolic, and Wallace tree multipliers are designed using the MUF gate in place of conventional adders to reduce area and delay. Simulation results on Xilinx FPGA show the proposed multipliers require fewer gates and have lower delay compared to existing designs, indicating benefits for low power DSP applications.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
IRJET- Internet of Things (IoT) based Smart GridIRJET Journal
1) The document discusses using Internet of Things (IoT) technology to create a smart grid system that can automatically reroute power from one grid station to another if there is a fault, preventing power outages.
2) It describes how sensors would be used in the smart grid system for monitoring grid stations and transformers as well as preventing electricity theft.
3) The system aims to solve the problem of power outages occurring when a grid station fails by connecting customer loads to a backup grid station through IoT technology with a single click.
This document discusses the design of an aware flip-flop circuit with low power variations using P-Spice simulation software. It begins by introducing the challenges of parameter variations in nanometer process technologies, such as increased delay and logic level changes. It then discusses existing approaches to handling variations, such as clock tree optimization and multi-threshold gates. The proposed circuit is an aware flip-flop that can detect and correct timing errors efficiently using a sensor latch, comparator and multiplexer. Simulation results show the proposed circuit has lower power and is more robust than existing approaches.
A Survey Paper on Leakage Power and Delay in CMOS Circuitsijtsrd
Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi "A Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITSVLSICS Design
This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
The document discusses an IoT-based smart energy grid system. It describes how IoT technologies can transform conventional power systems into smarter energy grids by enabling two-way communication between energy providers and consumers. This allows for more efficient, reliable and secure management of energy supply and demand. However, integrating IoT also introduces new security vulnerabilities that must be addressed, such as potential cyberattacks. Advanced technologies like blockchain, machine learning and AI could help secure IoT-enabled energy systems.
What to do when you have a perfect model for your software but you are constrained by an imperfect business model?
This talk explores the challenges of bringing modelling rigour to the business and strategy levels, and talking to your non-technical counterparts in the process.
Unlock the Secrets to Effortless Video Creation with Invideo: Your Ultimate G...The Third Creative Media
"Navigating Invideo: A Comprehensive Guide" is an essential resource for anyone looking to master Invideo, an AI-powered video creation tool. This guide provides step-by-step instructions, helpful tips, and comparisons with other AI video creators. Whether you're a beginner or an experienced video editor, you'll find valuable insights to enhance your video projects and bring your creative ideas to life.
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Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Implementation of Effective Code Converters using Reversible Logic Gates IJERA Editor
The development in the field of nanometer technology leads to minimize the power consumption of logic
circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less
dissipation of heat and low power consumption. In the digital design, the code converters are widely used
process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to
Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is
proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are
available for design. Reversible processor design needs its building blocks should be reversible in this view the
designing of reversible code converters became essential one. In the digital domain, data or information is
represented by a combination of 0’s and 1’s. A code is basically the pattern of these 0’s and 1’s used to
represent the data. Code converters are a class of combinational digital circuits that are used to convert one type
of code in to another. The proposed design leads to the reduction of power consumption compared with
conventional logic circuits
A modular approach for testable conservative reversible multiplexer circuit f...VIT-AP University
Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent
part of any system-level design. In this article, the significant module of a multiplexer, an extended to n:1 is framed with
prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm,
which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing
framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative
reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters
in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count,
quantum cost and unit delay are optimal.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
This document summarizes a research paper that proposes a power gating structure using sleep transistors to reduce subthreshold leakage in a reversible programmable logic array (RPLA). It begins by introducing the concept of reversible logic for reducing power dissipation at the gate level. However, physical implementation with CMOS technology still leads to leakage during inactive periods. The paper then discusses power gating and sleep transistors as a technique to reduce leakage. It proposes a design for an RPLA using reversible AND and OR arrays with sleep transistors in a footer configuration to switch between active and sleep modes. Simulation results show 40.8% energy savings compared to a conventional CMOS design.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array (RPLA) is one of the important parts of the low power industrial applications and in this paper the physical design of the RPLA is presented by using the sleep transistor and the results is shown with the help of TINA- PRO software. The results for the proposed design is also compare with the CMOS design and shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the switching activity and showing that the proposed design is much better that the modern CMOS design of the RPLA.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
Review On 2:4 Decoder By Reversible Logic Gates For Low Power ConsumptionIRJET Journal
This document summarizes a research paper that proposes designing a 2:4 decoder using reversible logic gates to reduce power consumption. Reversible logic gates use minimal power by only employing buffers instead of traditional CMOS gates. The document provides background on reversible gates and decoders, reviews previous work on low-power decoder designs, and proposes a reversible gate-based 2:4 decoder design to reduce overall system power consumption compared to a standard CMOS implementation. Simulation results from other studies show reversible gate designs can achieve up to 26% power reduction for instruction decoding. The proposed design aims to lower delay and gate count while minimizing power.
Area Efficient Pulsed Clock Generator Using Pulsed Latch Shift RegisterIJMTST Journal
The document describes a proposed area efficient pulsed clock generator using pulsed latch shift registers. Conventional shift registers use flip-flops which consume more power and area than latches. The proposed design uses pulsed latches instead of flip-flops to reduce power consumption and area. It solves the timing problem of using latches in shift registers by generating multiple non-overlapping delayed pulsed clock signals. Simulation results show the proposed shift register reduces power consumption by 27% and delay by 21% compared to a conventional flip-flop based shift register.
Adiabatic technique based low power synchronous counter designIJECEIAES
The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.
Circuit Approaches for VLSI in Internet-of-Things ApplicationsIRJET Journal
This document discusses circuit approaches for VLSI in Internet-of-Things applications. It describes two proposed circuits: (1) An ultra-compact and robust physically unclonable function (PUF) circuit based on temperature sensors, and (2) A method to transform SRAM arrays into robust analog PUFs with minimal overhead. It also discusses challenges with power management in IoT devices and proposes a capacitor-buffered hybrid energy storage solution for energy harvesting power management units.
IRJET- Sink Mobility based Energy Efficient Routing Protocol for Wireless Sen...IRJET Journal
The document describes a proposed sink mobility based energy efficient routing protocol for wireless sensor networks. The protocol uses both a static centralized sink and a mobile sink that follows a predetermined path with 4 sojourn locations. This is aimed to improve network lifetime by balancing energy load across nodes. Simulation results show that the proposed approach with a mobile sink performs better than the Threshold sensitive Energy Efficient sensor Network (TEEN) protocol alone in terms of number of alive nodes, number of cluster heads, and number of packets sent to the base station over multiple rounds. Using a mobile sink helps scatter the energy load in the network and extends lifetime compared to only using a static sink.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
IRJET- FPGA Implementation of Efficient Muf Gate based MultipliersIRJET Journal
This document discusses the FPGA implementation of efficient multiplier circuits using reversible MUF gates. It begins with background on reversible logic and the benefits of reducing heat dissipation. A reversible MUF gate is proposed that can realize basic logic functions with unique input-output mappings. Array, systolic, and Wallace tree multipliers are designed using the MUF gate in place of conventional adders to reduce area and delay. Simulation results on Xilinx FPGA show the proposed multipliers require fewer gates and have lower delay compared to existing designs, indicating benefits for low power DSP applications.
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Envi...VIT-AP University
Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
IRJET- Internet of Things (IoT) based Smart GridIRJET Journal
1) The document discusses using Internet of Things (IoT) technology to create a smart grid system that can automatically reroute power from one grid station to another if there is a fault, preventing power outages.
2) It describes how sensors would be used in the smart grid system for monitoring grid stations and transformers as well as preventing electricity theft.
3) The system aims to solve the problem of power outages occurring when a grid station fails by connecting customer loads to a backup grid station through IoT technology with a single click.
This document discusses the design of an aware flip-flop circuit with low power variations using P-Spice simulation software. It begins by introducing the challenges of parameter variations in nanometer process technologies, such as increased delay and logic level changes. It then discusses existing approaches to handling variations, such as clock tree optimization and multi-threshold gates. The proposed circuit is an aware flip-flop that can detect and correct timing errors efficiently using a sensor latch, comparator and multiplexer. Simulation results show the proposed circuit has lower power and is more robust than existing approaches.
A Survey Paper on Leakage Power and Delay in CMOS Circuitsijtsrd
Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi "A Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITSVLSICS Design
This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.
The document discusses an IoT-based smart energy grid system. It describes how IoT technologies can transform conventional power systems into smarter energy grids by enabling two-way communication between energy providers and consumers. This allows for more efficient, reliable and secure management of energy supply and demand. However, integrating IoT also introduces new security vulnerabilities that must be addressed, such as potential cyberattacks. Advanced technologies like blockchain, machine learning and AI could help secure IoT-enabled energy systems.
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Review on Reversible Logic Gates
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