This document presents a new design approach for implementing a binary adder using Quantum-dot Cellular Automata (QCA). A 128-bit adder is implemented using this novel QCA design approach. Simulation results show the 128-bit QCA adder has a delay of 18.77 ns and occupies an area of 129 LUTs. This is an improvement over a traditional 128-bit ripple carry adder, which has a delay of 140.517 ns and occupies an area of 256 LUTs. The new QCA adder design approach reduces delay and area compared to existing adder designs like the ripple carry adder.