In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier

1. G.SAMBASIVA RAO 11KR1A0410
P.KALYANI 11KR1A0424
N.CHAITANYA 11KR1A0418
T.AKHILA 11KR1A0430
Project associated by
Under The Esteemed Guidance Of
Ms.V.MAHESWARI M.Tech.,
Assistant Professor

2. Aim Of The Project
The main of our project is design a 32-bit
multiplier by using either CLAA and CSLA
based on area,delay time and power required
for the multiplier.

3.  Digital computer arithmetic is an aspect of logic design
with the objective of developing appropriate algorithms in
order to achieve an efficient utilization of the available
hardware.
 The basic operation of additions implemented to the
operation of multiplication.
 Multiplications and additions are most widely used arithmetic
computations performed in all digital signal processing
applications.
 In this project we are going to the performance of different
adders implemented to the multipliers based on area and time
needed for calculation.

4. Carry Look A Head Adder:-
ADDER DESIGN
Carry Look Ahead Adder can produce carries faster due to
parallel generation of the carry bits by using additional circuitry. This
technique uses calculation of carry signals in advance, based on input
signals. The result is reduced carry propagation time. For example,
ripple adders are slower but use the least energy.

5. CARRY SELECT ADDER
This adder can be used for the construction of add and shift
multiplier which have lowest area, high speed and minimum
power consumption.

6. Algorithm for array multiplier
 In this algorithm we are using two 4-bits one is multiplier second one is multiplicand.
Example:-
1 0 1 0 multiplier”A”
1 0 1 1 multiplicand “B”
1 0 1 0
1 0 1 0
0 1 1 1 1
0 0 0 0
0 0 1 1 1
1 0 1 0
0 1 1 0 1
0 1 1 0 1 1 1 0

7. Array Multiplier Using CLA &CSA
product register size be 64
bits. Let the
multiplicand registers size be 32
bits. Store the multiplier in least
significant half of the product
register.
Repat the following steps in for
32 times.
A partial schematic of the
multiplier

8. VHDL SIMULATIONS
 The VHDL simulation of the two multipliers is presented
waveforms, timing diagrams and the design summary for both
the CLAA and CSLA based multipliers.
 The VHDL code for both multipliers, using CLAA and CSLA,
are generated.

9. Simulation result

10. PERFORMANCE ANALYSIS:-
Area Analysis
 The performance analysis for the area of CLAA and CSLA based
multipliers are represented in the form of the diagram
CLAA
Area analysis chart

11. Delay Analysis
 The performance analysis for the delay time of CLAA and
CSLA based multipliers are represented in the form of the
diagram.
Delay analysis chart

12. Area Delay Product Analysis:-
The performance analysis for the area delay product of CLAA and
CSLA based multipliers are represented in the form of the diagram.
Area delay product analysis chart

13. Analysis
The analysis of the project in brief is given in
below table
Multiplier
type
Delay(ns) Area Delay area
product
CLAA based
multiplier
98.5 2957
Logic cells
291264.5
CSLA based
multiplier
99.5 2039
Logic cells
202880.5

14. Advantages
 Cost effective compared to other proposed architectures .
 High speed, Low power, Less area .
 Modified CSLA Can be used to implement Wallace tree
Multiplier and Baug- Wooley multiplier.

15. Applications
Data paths in Microprocessors.
Digital Adders are the core block of DSP
processors.
Extensively used in processing units such as
ALU.
Forming dedicated integer and floating point
units.
In Multiply-accumulate (MAC) structures.
Digital Signal processing.
 High speed Integrated circuit.

16.  A design and implementation of a VHDL-based 32 bit unsigned
multiplier with CLAA and CSLA was presented.
VHDL was used to model and simulate our multiplier. Using CSLA
improves the overal performance of the multiplier.
 Thus a 31 % area delay product reduction is possible with the use of
the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32
bit unsigned parallel multiplier.