The document provides an overview of microprocessors and microcontrollers. It discusses the history and evolution of microprocessors from early minicomputers in the 1960s to modern microcontrollers that integrate CPU, memory and I/O onto a single chip. The document outlines common microprocessor components like registers, ALU, buses and control units. It also covers digital logic gates, memory systems, number representations and instruction sets.

1. MICROPROCESSORS
Based Systems II
E442
Professor Dr Ir Mostafa Afifi
mafifi@ieee.org
012 795 2747

2. Scheduled Studies
• Overview of Basics of Binary Operations
• Review of Digital Electronic Components
• Microprocessor and Microcontroller Architectures
• Micro processing Using 8051 Architectures
• Interrupt and Timing Systems
• Real World Interfacing using A/D and D/A
converters, Motors …. Etc.
• Appendices for the 8051 descriptions
• Laboratory Applications

3. Short History
• The first Minicomputers appeared in 1964, PDP-
8, by Digital Equipment Company
• The Microprocessor name appeared in 1972,
using one unit of CPU
• In 1972 the Intel 4 bit, 4004, and the 8 bit, 8008
appeared, using 4 chips, CPU, ROM, RAM and
shift register chip for output Expansions
• In 1991 over 750 Million 8 bit microcontrollers
were delivered by chip manufactures

4. Microcontrollers,
Microprocessors and
Microcomputers
• A Microcontroller is a Microcomputer
with Memory and I/O integrated into one
chip
• The Microcomputer is a
Microprocessor with added Memory and
Input/Output
• The Microprocessor contains the CPU,
the ALU (Arithmetic and Logic Unit) and
the Control Units, with partial memory and

5. The Basic Computer System

6. Registers and an ALU
to ADD or SUBTRACT

7. 8 D-type Latches
to Construct an 8 bit Register

8. Adding Inputs & Outputs
to the Registers and the ALU

9. Information Flow
after the MOV Operation

10. A Program to Input two numbers,
Add them and display the Result

11. THE INFORMATION AGE
• Data Processing is involved in Business
Transactions, Communications, Transportation,
Medical Treatments & Entertainments.
• In Industrial World it is employed in Design,
Manufacturing, Distribution & sales.
• In Science & Engineering it would have not been
developed Otherwise.
• New Processors Emerge after the evidence of
success produced by application of previous
processors

12. Digital Systems Manipulate The
Following Discrete Elements of
Information
• The 10 Decimal Digits
• The 26 Digits of the Alphabet
• The 52 Playing Cards
• The 64 squares of the Chessboard
• Numeric Computations are Major applications using
the digits, and hence the name
DIGITAL PROCESSORS

13. Voltage Range for Binary Signals
High & Low, True & False, or 1 & 0
In MNOR cases True is 0 and False is 1
Reliability of Binary Emerges from Only
Simple 1 and 0 Levels

14. Generic Block Diagram
of a Microprocessor
The CPU (dark area) Includes; the Floating Point Unit
(FPU), The Memory Management Unit (MMU)
and The Internal Cache

15. The Floating Point Unit (FPU)
• Processes Data in the form of the Scientific
Notation 1.234x10N, Permitting the Handling of
Very Large and the Very Small Numbers
• The CPU and the FPU, each contain a data path
and a control path units
• The MMU and the Cache are included in the
Memory Block of the Figure

16. The NUMBER SYSTEMS
Any Number N can be represented in the form
N = k = -r  A k b k ,
m
1. The Decimal (base b = 10)
123.4510 = 1 x 102 +2 x 101 + 3 x 100 + 4 x 10-1 + 5 x10-2,
2. The Binary (base b = 2)
123.4510 = 0x27 + 1x26 + 1x25 + 1x24 + 1x23 + 0x22 + 1x21 + 1x20
+ 0x2-1 + 1x2-2 + 1x2-3 + 1x2-4 + 0x2-5 + 0x2-6 + 1x2-7 + 1x2-8
+ a remainder of 0.0007813
= 01111011.01110011 + 0.0007813 (a 16 bit representation)

17. The OCTAL and the
HEXADECIMAL
3. In the OCTAL (base b = 8), same Number is:
123.4510 = 1x82 + 7x81 + 3x80 + 3x8-1 + 4x8-2 + 6x8-3 + 3x8-4 + 1x8-5 +
0.00002
= 173.346318 + 0.00002
4. In the HEXADECIMAL (BASE B = 16), Same Number is:
123.4510 = 7x161 + Bx160 + 7x16-1 + 3x16-2 + 3x16-3 + 0.000048
= 7B.73316 + 0.0000488
Note that the fraction is not rational, keeping a remainder dependent on the
number of digits used

18. Powers of Two
m 2m m 2m m 2m
0 1 9 512 18 262,144
1 2 10 1,024 19 524,288
2 4 11 2,048 20 1,048,576
3 8 12 4,096 21 2,097,152
4 16 13 8,192 22 4,194,304
5 32 14 16,384 23 8,388,608
6 64 15 32,768 24 16,777,216
7 128 16 65,536 25 33,554,432
8 256 17 131,072 26 67,108,864

19. Binary Coded Decimal (BCD)
Each Octal Digit can be presented by 3 binary digits
0 000 2 010 4 100 6 110
1 001 3 011 5 101 7 111
Each HEXA digit can be presented by 4 binary digits
0 0000 4 0100 8 1000 C 1100 (12)
1 0001 5 0101 9 1001 D 1101 (13)
2 0010 6 0110 A 1010 (10) E 1110 (14)
3 0011 7 0111 B 1011 (11) F 1111 (15)

20. Important Observations
• Shifting the bits left is multiplication by the base
and shifting it right is division by the base (7 is 0111
and 14 is 1110)
• Dividing the binary code to groups of threes yield
the BCD in Octal ( 12310= 1738 or 001111011 =
12310 = 173BCD 8 = 001 111 011)
• Dividing the binary code to groups of Fours yield the
BCD in Hex ( 12310= 7B16 or 001111011 = 12310 =
7BBCD 16 = 0111 1011)

21. BCD ADDITION

22. America Standard Code for
Information Interchange ASCII
52 Low & Upper Case, 32 Extra & 34 Controls

23. Even and Odd Parities
ASCII A = 1000001 = 01000001 for EVEN or =
11000001 for ODD
ASCII T = 1010100 = 11010100 for EVEN or
01010100 for ODD

24. Negative Numbers
N- = 2n – N+
-10010 = 28 – 10010 = 1000000002 – 011001002
= 100111002
For n = 8 bits
–128 ≥ N ≤ 127
N- = Nc+ + 1

25. Digital Logic Gates

26. The NAND & the Inv-In-OR verify
deMorgan’s Theory
110110
1 0 1 NAND 1 0 1
011011
0 0 1 x’ + y’ = (xy)’ 0 0 1

27. Gate Rules and Properties
• AND “ “ and OR “ “ gates are fundamental logic
formations
• Reverse of Inputs and Outputs of one yield the
performance of the other
• CMOS gates (+3 to 15 V) are superior than DL, RTL
or TTL (5V) concerning Low buffering & Delay
• High Speed CMOS (5V) “HCT” is designed to be
compatible with TTL

28. Combinational Logic Design
• Determine the numbers of inputs “n” and
outputs “m” from requirement specifications
• Write the Truth table relating n and m
• Simplify the Boolean functions relating n & m
• Generate the logic diagram
• Verify the correctness of the design

30. The Sum, with sum of the min-
terms and Karnaugh Map

31. The Logic Diagram
of the Full Adder

32. The Carry, with sum of the min-
terms and Karnaugh Map

33. Hardware Description Languages
HDL
• VHDL (Very high speed Integrated Circuits
Hardware Description Language) and
• Verilog (developed by Cadence Design
Systems, Inc)
Both are specified by IEEE to describe and use
Hardware compilers to determine the correctness of
complex Combinational Logic Networks; essentially
applied to design of advanced RISC computers

34. A Four to One Line Multiplexer

35. VHDL Conditional Data Flow
Description Program
of the 4 to 1 Multiplexer

36. Verilog Data Flow Description of
the 4 to 1 Multiplexer
Using Boolean Equations

37. Clocked Sequential Circuit Analysis Use
the VHDL and Verilog Analysis
• Block Diagram of a Sequential Circuit
• Synchronous Clocked Sequential Circuit

38. Standard Graphical Symbols of
Latches and Flip Flops

39. Basic Processing Components
of Microprocessors and Micro controllers
IR instruction Register, MAR memory access register
PC program counter, MDR memory data register

40. BUS Structures
• Simple two Bus structure
• More Flexible Two Bus Structure

41. Memory Block Diagram and Contents
(RAM)

42. Memory Cycle Timing Forms
Chip Select (SC) Read/Write (R/W) Memory Operation 0 X None 1 0
Write to selected word 1 1 Read from selected word

43. Block Diagram of Dynamic Memory
(DRAM)

44. Memory mapping in 8051
• ROM memory map in 8051 family
4k 8k 32k
0000H 0000H 0000H
0FFFH
DS5000-32
1FFFH
8751
AT89C51
8752
AT89C52 7FFFH
from Atmel Corporation
from Dallas Semiconductor

45. Timing for the DRAM R/W Operations

46. Three Instruction Format

47. Memory Representation
of Instructions and Data

48. Three Address Instructions for
(A+B)*(C+D)
ADD T1, A, B M[T1]←M[A] + M[B]
ADD T2, C, D M[T2]←M[C] + M[D]
MUL X, T1, T2 M[X]←M[T1] x M[T2]
Or registers can be used for temporary storage:
ADD R1, A, B R1←M[A] + M[B]
ADD R2, C, D R2←M[C] + M[D]
MUL X, R1, R2 M[X]← R1 x R2

49. TWO Address Instructions for
(A+B)*(C+D)
• MOVE T1, A M[T1]←M[A]
• ADD T1, B M[T1]←M[T1] + M[B]
• MOVE X, C M[X]←M[C]
• ADD X, D M[X]←M[X] + M[D]
• MUL X, T1 M[X]←M[X] x M[T1]

50. ONE Address Instructions for
(A+B)*(C+D)
• LD A ACC←M[A]
• ADD B ACC←ACC + M[B]
• ST X M[X]←ACC
• LD C ACC←M[C]
• ADD D ACC←ACC + M[D]
• MUL X ACC←ACC x M[X]
• ST X M[X]←ACC

51. ZERO Stack Address Instructions
for (A+B)*(C+D)
• PUSH A TOS←M[A]
• PUSH B TOS←M[B]
• ADD TOS←TOS + TOS-1
• PUSH C TOS←M[C]
• PUSH D TOS←M[D]
• ADD TOS←TOS + TOS-1
• MUL TOS←TOS x TOS-1
• POP X M[X] ←TOS

52. Stack Activity for Execution
PUSH A Push B ADD PUSH C PUSH D ADD MUL
A B A+B C D (C+D) (A+B)(C+D)
A A+B C (A+B)
A+B

53. Use Registers Address Instructions
for (A+B)*(C+D)
• LD R1, A R1←M[A]
• LD R2, B R2←M[B]
• ADD R3, R1, R2 R3←R1+R2
• LD R1, C R1←M[C]
• LD R2, D R2←M[D]
• ADD R4, R1, R2 R3←R1+R2
• MUL R1, R4, R3 R1←R1 x R3
• ST X, R1 M[X] ←R1

54. Numerical Example for
Addressing Modes
location in Memory
PC=250 250 Opcode mode
instruction at locations 250-251 251 Add or nr=500
R1=400 252 next instruction
400 700
instruction is 500 800
load to ACC 750 600
800 300
900 200

55. ADDRESSING Modes

56. Typical Programming Instructions
Data Transfer Instructions Arithmetic instructions
Name Mnemonic Name Mnemonics
• Load LD Increment INC
• Store ST Decrement DEC
• Move MOV Add ADD
• Exchange XCH Subtract SUB
• Push PUSH Multiply MUL
• Pop POP Divide DIV
• Input IN Add with Cary ADDC
• Output OUT Subtract with Borrow SUBB
Subtract Reverse SUBR
Negate NEG

57. Typical Programming Instructions
• Logical and Bit Manipulation Shift Instructions
Name Mnemonic Name Mnemonics
• Clear CLR Shift Right SHR
• Set SET Shift Left SHL
• Complement NOT Arithmetic Shift Right SHRA
• And AND Arithmetic Shift Left SHLA
• Or OR Rotate Right ROR
• Exclusive Or XOR Rotate Left ROL
• Clear Carry CLRC Rotate Right with Carry RORC
• Set Carry SETC Rotate Left with Carry ROLC
• Complement Carry COMC

58. Typical Programming Instructions
• Control Instructions Conditional Branching, with PSR
Name Mnemonic Name Mnemonics
• Branch BR Br. If Zero BZ Z=1
• Jump JMP Br. If not Zero BNZ Z=0
• Skip Next Instr. SKP Br if Carry BC C=1
• Call Procedure CALL Br. if no Carry BNC C=0
• Return from Prc. RET Br. If Minus BN N=1
• Comp. (by Sub.) CMP Br. If plus BNN N=0
• Test (by ANDing) TEST Br. If Overflow BV V=1
• Br. If no Overflow BNV V=0

59. Typical Programming Instructions
Conditional Branch Instructions for Unsigned Numbers
Branch Condition Mnemonic Condition Status Bits
• Branch if Higher BH A > B C + Z = 0
• Br If Higher or Equal BHE A ≥ B C = 0
• Branch if Lower BL A < B C = 1
• Br. If lower or Equal BLE A ≤ B C + Z = 1
• Br. If Equal BE A = B Z = 1
• Br. If not Equal BNE A ≠ B Z = 0

60. Typical Programming Instructions
Conditional Branch Instructions for Signed numbers
• Br. If Greater BG A > B (N Ө V) + Z = 0
• Br. If Greater or Equal BGE A ≥ B N Ө V = 0
• Branch if Less BL A < B N Ө V = 1
• Br. If Less or Equal BLE A ≤ B (N Ө V) + Z = 1

61. Block Diagram
External interrupts
On-chip Timer/Counter
Interrupt ROM for
program On-chip Timer 1 Counter
Control RAM Inputs
code Timer 0
CPU
Bus Serial
4 I/O Ports Port
OSC Control
P0 P1 P2 P3 TxD RxD
Address/Data

62. Pin Description of the 8051
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 8051 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7
(8031) 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8) 

63. Port 0 with Pull-Up Resistors
Vcc
10 K
P0.0
Po
DS5000 P0.1 rt
8751 P0.2
P0.3
0
8951 P0.4
P0.5
P0.6
P0.7

64. Port 3 Alternate Functions
P3 Bit Function Pin
P3.0 RxD 10
P3.1 TxD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17 

65. RESET Value of Some 8051 Registers:
Register Reset Value
PC 0000
ACC 0000
B 0000
PSW 0000
SP 0007
DPTR 0000
RAM are all zero.


66. Registers
A
B
R0
DPTR DPH DPL
R1
R2 PC PC
R3
R4 Some 8051 16-bit Register
R5
R6
R7
Some 8-bitt Registers of
the 8051

67. Sequence Controller Allow High
Speed Execution

68. The Sequential State Diagram

69. Wait State is added to allow
Synchronization with Slow devices

70. MOV instruction copies contents

71. ORG, MOV, ADD, END and Label:

72. Operation Codes for MOV, ADD and
Label:

73. DB (Define Byte) and its Label:

74. Assembling and
Running a Program

75. PSW (Program Status Word)
Register

76. Register Banks
and RAM Addresses

77. RAM Addresses are usable instead
of the Register name

78. Selecting Register Bank 2

79. • RAM memory space allocation in the 8051
7FH
Scratch pad RAM
30H
2FH
Bit-Addressable RAM
20H
1FH Register Bank 3
18H
17H
Register Bank 2
10H
0FH (Stack) Register Bank 1
08H
07H
Register Bank 0
00H

80. Stack in the 8051
• The register used to 7FH
access the stack is called
Scratch pad RAM
SP (stack pointer) register.
30H
• The stack pointer in the 2FH
8051 is only 8 bits wide, Bit-Addressable RAM
which means that it can 20H
1FH
take value 00 to FFH. 18H
Register Bank 3
When 8051 powered up, 17H
Register Bank 2
10H
the SP register contains 0FH (Stack) Register Bank 1
value 07. 08H
07H
Register Bank 0
00H

82. Program Interrupts
• Interrupts are initiated at unpredictable
point during program execution
• Address of the interrupt service routine
(ISR) is determined by hardware
procedure
• Interrupt necessitates storage of all or part
of the performing register set (not only the
program counter)

83. Three Major Interrupts
• External Interrupts (from input or output devices
requesting transfer of data or time out of an
event)
• Internal Interrupts (caused by traps of illegal or
erroneous use of instruction or arithmetic
overflow of data)
• Software Interrupts (are initiated by executing
instructions. It is a special call instruction)

84. Response to an Interrupt
• Enable Interrupt (EI=1) flag should be on
• Complete execution of present instruction
• Enabling of Interrupt Acknowledgement output (INTACK)
• Response by providing Interrupt Vector Address (IVAD)
• Typical micro instructions are
SP←SP-1 decrement stack pointer
M[SP]←PC store return address on stack
SP←SP-1 decrement stack pointer
M[SP]←PSR store processor status word on stack
EI←0 Reset Enable Interrupt
INTACK←1 enable interrupt acknowledgment
PC←IVAD transfer interrupt vector address to PC

85. Example of External Interrupt
Configuration

86. Interrupt 6 Vector Table of 8051
Interrupt ROM location Pin
• Reset 0000 9
• Ext. hardware 0 (INT0) 0003 P3.2(12)
• Timer 0 (TF0) 000B
• Ext. hardware 1 (INT1) 0013 P3.3(13)
• Timer 1 (TF1) 001B
• Serial COM (R1 and T1) 0023

87. Interrupt Enable (IE) Register
• EA IE7 Interrupt Enable
• - IE6 reserved for future use
• ET2 IE5 enable or disable timer 2 overflow
• ES IE4 enable or disable serial port Int.
• ET1 IE3 enable or disable timer 1 overflow
• EX1 IE2 enable or disable external Int. 1
• ET0 IE1 enable or disable timer 0 overflow
• EX0 IE0 enable or disable external Int. 0

88. Instructions to enable Interrupts
1.MOV IE, #10010110B ;enable serial, ;timer 0 and Ex1
Intrs
2.CLR IE.1 ;mask (disable) T0
3.CLR IE.7 ;disable all interts.
4.Another way is
SETB IE.7 ;global enable Intr.
SETB IE.4 ;enable serial Intr.
SETB IE.1 ;enable timer o Intr
SETB IE.2 ;enable EX1 Intr.

89. Major Eight Bit Microcontrollers
• Motorola 6811
• Intel 8051
• Zilog Z8
• PIC 16X
They are not compatible, each has its own instruction set

90. Selection Arguments
of Micro controllers
• Application Requirements, including:
o Clock speed, Packaging configurations (DIP
“Dual in line Packaging”, or ADF “Quad flat
Package”, ROM and RAM on the chip, Power
consumption, Number of pins, System
upgrade capability, and Costing…etc
• Supporting Software
Compilers, emulators and Technical Support
• Diversity of Suppliers
Intel.com Atmel.comsci.siemens.com Philips.cm dalsemi.com

91. Intel 8051 Family
Feature 8051 8052 8031
ROM (on-chip) 4K 8K 0K
RAM (Bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt Sourcs 6 8 6

92. Useful Information
• WatchDog is the ultimate application for
restricting and monitoring the time you or
others spend on the computer (Software
example at www.watchdogpc.com)
• Special Function Registers (SFR) are:
A, B, PSW, and DPTR
These can be used by name or address

93. Care for Negative Numbers
• As the 8051 is 8 bit chip Watch
MOV A, #-128 ; A = 1000 0000 (A=80H)
MOV R4, #-2 ; R4=1111 1110 (R4=FEH)
ADD A,R4 ;A =0111 1110 (A=7EH=126)
This result is Wrong, as OV is 1 (for overflow)
OV in the PSW should be then OV=1
• The following case is true, as OV=0

94. Correct Negative Results
• The OV flag need to be zero to know the
correctness of the negative number operations
MOV A, #-2 ;A=1111 1110 (A=FEH)
MOV R1, #-5 ;R1=1111 1011 (R1=FBH)
ADD A,R1 ;A=1111 1001 (A=F9H=-7)
Note that OV=0 of (PSW), indicating the
correctness

95. LOOP and JUMP Instructions
• LOOP is repeating a sequence of
instructions a number of times which is a
widely used action in micro processing. Its
instruction is:
“ DJNZ register, label”
The register is Decremented repeatedly so
long as it is Not Zero and Jumps to the
target address referred to by the label.

96. Example of Repeated Additions
MOV A,#0 ;A=0 or clear A
MOV R2,#10 ;load R2 by 10
AGAIN: ADD A,#03 ;add 3 to A
DJNZ R2,AGAIN ;repeat till R2=0
MOV R5,A ;save A in R5
Here the maximum number of repetitions for 8 bit
registers is 256 as 255 is the maximum number

97. Nested Loops are used
for more than 256 repetitions
Example of 700 Loops
MOV A,#55H ;A is 55H
MOV R3,#10 ;R3 is 10
NEXT: MOV R2,#70 ;R2 is 70
AGAIN: CPL A ;complement A
DJNZ R2,AGAIN ;repeat 70 times
DJNZ R3,NEXT ;repeat 10 times

98. Specialized JUMP Statements
JZ is jump if accumulator A is Zero, and
JNZ is jump if accumulator A is Not Zero
MOV A,R0 MOV A,R5
JZ OVER JNZ NEXT
MOV A,R1 MOV R5,#55
JZ OVER ……………
……………… ……………
OVER: …………….. NEXT: ………..

99. Conditional Jump Instructions
• JZ Jump if A=0, restricted to A
• JNZ Jump if A not 0, restricted
• DJNZ Decrement and Jump if any A
• CJNE A,byte Jump if A is equal to byte
• CJNE reg,#data Jump if byte not equal to #
• JC Jump if CY=1
• JNC Jump if CY=0
• JB JUMP if bit = 1
• JNB Jump if bit = 0
• JBC Jump if bit=1 and clear bit

100. Conditional Jumps can put the low byte
and high byte in two Registers
• Summation of 79H, F5H and E2H
MOV A,#0 ;clear A
MOV R5,A ;clear R5
ADD A,#79H ;A=79H
JNC N_1 ;if no carry add next
INC R5 ;if CY=1 inc R5
N_1: ADD A,#0F5H ;A=6E and CY=1
JNC N_2 ;jump if CY=0
INC R5 ;if CY=1 then increment R5
N_2: ADD A,#0E2H ;A=50 ad CY=1
JNC OVER ;jump if CY=0
INC R5 ;if CY=1, increment R5
OVER: MOV R0,A ;Now R0=50H & R5=02

101. Port Toggle of H-L bit levels
ORG 0 ;Start Location
BACK: MOV A,#55H ;A=55H
MOV P1,A ;P1=55H
LCALL DELAY ;time Delay
MOV A,#0AAH ;A=AAH
MOV P1,A ;P1=AAH
LCALL DELAY ;time delay
SJMP BACK ;Repeat the sequence
Note: LCALL is 3 bytes and ACALL is 2 bytes, it makes no difference which is
used, it only save few bytes of the program size if ADELAY is used

102. The Delay Subroutine
ORG 30H ;put delay at 30H
DELAY: ;nested loop delay
MOV R4,#255 ;R4=FFH
NEXT: MOV R5,#255 ;R5=FFH
AGAIN: DJNZ R5,AGAIN ;repeat till R5=0
DJNZ R4,NEXT ;Decrement R4
;keep loading R5 till R4 is 0
RET

103. RAM configuration of 8051
7FH
Scratch pad RAM
30H
2FH
Bit-Addressable RAM
20H
1FH
Register Bank 3
18H
17H
Register Bank 2
10H
0FH (Stack) Register Bank 1
08H
07H
Register Bank 0
00H

104. STACK in the 8051
• The stack pointer (SP) register (8 bits)
accesses the stack, at address 07 of RAM
• RAM location 08 is first to be used stack
• To load register content to stack use PUSH
• To load a register back from stack use POP
• Pushing data increments the SP by 1, in
contrast to many x86 processors using (-1)
• RAM address is used instead of RAM name
• When using stack do not use R-banks 1 & up

105. EXAMPLES for PUSH
MOV R6,#25H ;SP = 07
MOV R1,#12H ;SP = 07
MOV R4,#0F3H ;SP = 07
PUSH 6 ;SP = 08 = 25H
PUSH 1 ;SP = 09 = 12H & SP-1=25H
PUSH 4 ;SP=0A=F3H, SP-1=09=12H
;and SP-2 = 08 = 25H

106. EXAMPLES for POP
• If the stack is:
0B = 54H, 0A = F9H, 09 = 76H, 08 = 6CH
SP = 0B then the following
POP 3 ;pop into R3, and SP = 0A
POP 5 ;pop into R5, and SP = 09
POP 2 ;pop into R2, and SP = 08
POP 4 ;pop into R4, and SP = 07

107. To AVOID stack & bank 1 conflict
MOV SP,#5FH ;make RAM 60H first
;stack location
MOV R2,#25H ;insert 25H in R2
MOV R1,#12H ;insert 12H in R1
MOV R4,#0F3H ; insert F3H in R4
PUSH 2 ;SP=60 = 25H
PUSH 1 ;SP = 61 =12H & SP-1= 60 = 25H
PUSH 4 ;SP = 62 = F3H, SP-1 = 61 = 12H
;and SP-2 = 60 = 25H

108. Block Diagram of 64Kx16 RAM

109. Block Diagram of 256Kx8 RAM

110. Examples of Fundamental Functions for 8051
INCLUDE 8051.mc
INCLUDE 89S8252.mc
Button1 EQU P3.0
Button2 EQU P3.1
Direction BIT 0H
Start:
MOV PORT1,#FFH
MOV PORT3,#FFH
MOV A,#FEH ;set ACCU to FEH=254=1111110
Running_Light:
MOV PORT1,A
JB Direction,Check_1 ;Jump to “Check_1”, if bit direction is set
RL A
Check_1:
JNB Direction,Check_2
RR A
Check_2:
LCALL Wait
LJMP Running_Light
Wait:
#If NOT DEBUGGING

111. For Addition the Accumulator A
must be involved
MOV A,#0F5H
ADD A,#0BH ;F5H 1111 0101
;+0BH 0000 1011
; 100H 0000 0000
;CY=1, a carry out from D7
;PF=1, number of ones is ZERO (even number)
;AC=1, a carry from D3 to D4.

112. Addition of Individual Bytes
;a sequences of 5 addresses carry 5 numbers
;40=(70), 41=(EB),42=(C5),43=(5B),44=(30)
MOV R0,#40H
MOV R2,#5
CLR A
MOV R7,A
AGAIN: ADD A,@R0
JNC NEXT
INC R7 ;track of carries
NEXT: INC R0
DJNZ R2,AGAIN

113. ADDC, Addition of 16 bit numbers
;Addition of 3C E7 + 3B 8D, addition with carry
CLR C ;make CY=0
MOV A,#0E7H
ADD A,#8DH ;A=74H, and CY=1
MOV R6,A
MOV A,#3CH
ADDC A,#3BH ;3C+3B+1=78H
MOV R7,A ;save the high byte of the sum

114. DA instruction corrects for BCD Addition
MOV A,#47H
MOV B,#25H
ADD A,B ;A=6CH
DA A ;A=6C+6=72H
; 47H 0100 0111
;+25H 0010 0101
; 6CH 0110 1100
0110
0111 0010

115. SUBB is the only subtraction
instruction
CLR C ;make CY=0
MOV A,#3FH
MOV R3,#23H
SUBB A,R3 ;Add 2s comp of ;23 and invert the carry
; 3F 0011 1111 0011 1111
;- 23 0010 0011 1100 1101 2s cmp
1 0001 1100
0 CF=0
CY=0, AC=0 and programmer looks for +ve or –ve flag

116. Registers A and B are the only
registers to handle MUL and DIV
MOV A,#25H
MOV B,#65H
MUL AB ;25H*65H=E99H,
;B=0EH and A=99H
MOV A,#95
MOV B,#10
DIV AB ;A = 09 and B = 05 ;remainder
; CY=0 and OV=0, if number is 0, B=0 and OV=1

117. LOGIC Instructions
ANL is AND, ORL is OR & XRL is XOR
The Destination is normally the Accumulator
MOV A,#35H
ANL A,#0FH ;Now A = 05H
ORL A,#02H ;now A = 07H
XRL A,#0CH ;now A = 0BH
CPL A ;complements A & CJNE A,#99H,NEXT is
compare and jump to NEXT if not equal.

118. RR, RL, RRC & RLC for Accumulator
MOV A,#36H ;A=0011 0110
RR A ;A=0001 1011
RR A ;A=1000 1101
RL A ;A=0001 1011
RRC A ;A=0000 1101, CY=1
RLC A ;A=0001 1011, CY=0
RLC A ;A=0011 0110, CY=0
SWAP A ;A=0110 0011, CY=0
SETB C ;A=0110 0011, CY=1

119. Special Function Register (SFR) Addresses
ACC* Accumulator 0E0H
B* B Register 0F0H
PSW* Program Status Word 0D0H
SP Stack Pointer 81H
DPTR Data Pointer (DPL 82H & DPH 83H)
P0* Port 0 80H
P1* Port 1 90H
P2* Port 2 0A0H
P3* Port 3 0B0H
IP* Interrupt priority control 0B8H
IE* Interrupt enable control 0A8H
TMOD Timer/counter mode control 89H
TCON* Timer/counter control 88H
* Is bit addressable registers

120. Special Function Register (SFR) Addresses
T2CON* Timer/counter 2 control 0C8H
T2MOD Timer/counter Mode control 0C9H
TH0 Timer/counter 0 high byte 8CH
TL0 Timer/counter 0 low byte 8AH
TH1 Timer/counter 1 high byte 8DH
TL1 Timer/counter 1 low byte 8BH
TH2 Timer/counter 2 high byte 0CDH
TL2 Timer/counter 2 low byte 0CCH
RCAP2H T/C 2 capture register high byte 0CBH
RCAP2L T/C 2 capture register low byte 0CAH
SCON* Serial control 98H
SBUF Serial data buffer 99H
PCON Power control 87H

121. PUSH & POP use the addresses
PUSH 06 ;put contents of R6 TOS
PUSH 0E0H ;put contents of A TOP
POP 0F0H ;put TOS in Register B
;contents of B = A
POP 02 ;TOS goes to R2
;now R2 = R6

122. Move Code Byte
MOVC A,@A+DPTR
ORG 100H
MOV DPTR,#200H ;load DPTR
B1: CLR A ;A=0
MOVC A,@A+DPTR ;Data into A
JZ Exit ;exit if char =0
MOV P1,A
INC DPTR
SJMP B1
EXIT: ….
ORG 200H
DT: DB “The Earth is like a ball”, 0
END

123. Moving Data from Table
MOV R3,#9
MOV DPTR,#SQR ;Load pointer
MOV A,R3
MOVC A,@A+DPTR
ORG 100H
SQR: DB 0,1,4,9,16,25,36,49,64,81

124. Move Code Byte
MOVC A,@A+PC
MOV A,R3
INC A
MOVC A,@A+PC
RET
SQR: DB 0,1,4,9,16,25,36,49,64,81
MOVX @DPTR,A ;Bring Bytes from X data memory
MOVX @Ri,A ;bring Byte from X data (i=0 or 1)

125. Moving Data from Table to Port
MOV DPTR,300H (or #SQR)
MOV A,#0FFH ;A=FFH
MOV P1,A ;P1 is input
BACK: MOV A,P1 ;get 0 – x – 9
MOVC A,@A+DPTR
MOV P2,A
SJMP BACK
ORG 300H
SQR: DB 0,1,4,9,16,25,36,49,64,81
END

126. Exercises
1. Write a program to add the following data and
store the result in RAM location 36H
ORG 30H
DT: DB 06,09,02,05,07
2. Write a program to calculate y = x2 + 2x + 5,
where x is between 0 and 9.

127. Solution of Exercise 1
MOV A,#0 ;clear A
MOV R3,A ;clear R3
MOV R0,#30H ;set the data address
MOV R2,#5 ;counter for data pnts
AGAIN: ADD A,@R0 ;put data point to A
JNC NEXT ;go to carry count
INC R3 ;move to next data
NEXT: INC R0 ;record the carry
DJNZ R2,AGAIN ;go to next addition
ORG #30H ;start address of data
DT: DB 06,09,02,05,07 ;data sequence in M
END ;end statement

128. Exercise 2 (y = x2+2x+5)
MOV R4,#9 ;set counter for data x points
MOV DPTR,#30H ;set locations of y in memory
AGAIN: MOV R2,#0 ;starting value of x
MOV A,R2 ;put x in the accumulator
MOV B,R2 ;put x in B
MUL AB ;get a value for x2
MOV R3,A ;put x2 in R3
CLR A ;clear A
MOV A,#2 ;put 2 in A
MUL AB ;2x is now in A
ADD A,R3 ;x2 + 2x is now in A
ADD A,#5 ; x2 + 2x + 5 is now in A
MOV @DPTR,A ;store the value in #30H
INC DPTR ;increment the pointer
INC R2 ;increment x
DCR R4 ;decrement the counter
DJNZ R4,AGAIN ;calculate another point
END

129. 8051 Serial Communications
• Parallel port communications (where data is transferred in parallel, one
byte or more at a time, using 10 or more parallel wires, to short
distances) is now obsolete
• Serial communications (one bit at a time) is now the way, using the serial
port RS232 (started 1960 by Electronics Industries Association “EIA”),
and applying the HyperTerminal of modern PCs. Parallel in, Serial out
shift registers are applied. For large distances D/A conversion is also
needed
• Synchronous communications transfer blocks of data at a time, while
Asynchronous communications transfer single bytes at a time
• USART (Universal Synchronous Asynchronous receivers-transmitters)
and UART (Universal Asynchronous receiver-transmitter), which is
included in 8051 chips, are used to do the transformations
• Full Duplex data communications are common, at least for short
distances. The ASCII 8 bit codes (with even or odd parities) are framed
by start bit (0) and stop (1) bit (or two bits))

130. Serial Connection and Programming
• The serial connection RS232 uses 15 connecting
pins, and used to have 25 or 9 connecting pins
• The supply potentials are –3 to –25V for 1 and 3
to 25V for 0. It needs another IC converter to
generate the TTL values for the 1 and 0
• The chip MAX232 (16 pin) or MAX233 (20 pin)
(not pin compatible) is used to transfer the
voltages
• The bit rate and the Baud rate are different, the
baud rate is modem terminology (signal changes
per Second) with standards of 2400,…
9600,……56Kbps….

131. Baud rate setting
• Machine Cycle Frequency = Xtal frequency / 12
=11.0592 / 12 = 921.6 KHz
• UART to timer 1 = 921.6 / 32 = 28.8 KHz
• a) 28.8 / 3 = 9.6 K ;with –3=FDH loaded TH1
• B) 28.8 /12=2.4 K ;with –12=F4H loaded TH1
• SBUF register is the one responsible for serial
MOV SBUF, # ‘D’ ;load SBUF=44H, ASCII for „D‟
MOV SBUF, A ; copy from accumulator
MOV A, SBUF ; copy reception to accumulator

132. SCON Serial Control Register
• SM0 SCON.7 ;serial port mode specifier
• SM1 SCON.6 ;serial port mode specifier
• SM2 SCON.5 ;multiprocessor comm (0)
• REN SCON.4 ;set/clear to enable/disable Rx
• TB8 SCON.3 ;not widely used
• RB8 SCON.2 ;not widely used
• TI SCON.1 ;Tx interrupt flag, must be clr
• RI SCON.0 ;Rx interrupt flag, must be clr
TI flag is important to monitor to insure proper
transmission when adding the stop bit to the 8 bit

133. Serial Mode Code
SM0 SM1
0 0 ;Serial Mode 0
0 1 ;SM 1, 8 b, 1 start bit ; & 1 stop bit
1 0 ;Serial Mode 2
1 1 ;Serial Mode 3

134. Transfer „YES‟ Serially
MOV TMOD,#20H ;timer1, mode2
MOV TH1,# -3 ;9.6 K Baud
MOV SCON,#50H ;8bit,stpb,REN enb
SETB TR1 ;start timer 1
AGAIN: MOV A,#”Y” ;transfer Y
ACALL TRANS
MOV A,#”E” ;transfer E
ACALL TRANS
MOV A,#”S”
ACALL TRANS
SJMP AGAIN ;keep sending YES
TRANS: MOV SPUF,A ;load SPUF
HERE: JNB T!,HERE ;wait for last bit transfer
CLR TI ;get ready for next byte
RET

135. 8051 Programming to Receive
Data serially
MOV TMOD,#20H ;timer 1, Mode2, ;Auto Reload
MOV TH1,#-6 ;4800 baud
MOV SCON,#50H ;8 bit,1 stop,REN
SETB TR1 ;start timer 1
HERE: JNB RI,HERE ;wait for char in
MOV A,SBUF ;save in byte to A
MOV P1,A ;send to port 1
CLR RI ;get ready to Rc next byte
SJMP HERE ;keep getting data

136. Serial PC Communications,
LEDs at P1and SW at P2 - 1
ORG 0
MOV P2, #0FFH ;make P2 input
MOV TMOD, #20H ;Timer 1 Mode 2, ;Auto Reload
MOV TH1,#0FAH ;4800 Baud
MOV SCON,#50H ;8 bit, 1 stp, REN
SETB TR1 ;start timer 1
MOV DPTR, #MYDATA ;Load PTR
H_1: CLR A
MOVC A,@A+DPTR ;get the character
JZ B_1 ;if last character get out
ACALL SEND ;otherwise call transfer
INC DPTR ;next one
SJMP H_1 ;Stay in loop

137. Serial PC Communications,
LEDs at P1and SW at P2 - 2
B_1: MOV A,P2 ;Read on P2
ACALL SEND ;Transfer Serially
ACALL RECV ;get serial data
MOV P1,A ;Display on LEDs
SJMP B_1 ;Stay in loop
;………….Serial data transfer from ACC
SEND: MOV SBUF,A ;load data
H_2: JNB T1,H_2 ;stay here till last bit
CLR T1 ;get ready for next char
RET ;return to caller

138. Serial PC Communications,
LEDs at P1and SW at P2 - 3
;………….Receive data serially in ACC
RECV: JNB RI,RECV ;wait for char
MOV A,SBUF ;send to AC CLR RI ;get ready for
char
RET ;return to caller
;…………the Message
MYDATA: DB “we are ready”,0
END

139. Use of PCON register D7 (SMOD)
to double the BAUD rate
PCON is not a bit addressable then:
MOV A,PCON ;copy PCON to ACC
SETB ACC, 7 ;make D7 = 1
MOV PCON,A ;now SMOD=1
;mach cycle frequency = 11.0592/12 = 921.6 KHz
;Baud rate = 921.6 / 16 = 57.6 KHz (was 28.8 KHz)

140. Example for serial transmission
MOV A,PCON ;A=PCON
SETB ACC,7 ;make D7=1
MOV PCON,A ;SMOD=1, Double baud
MOV TMOD,#20H ;timer1 mode2, ;auto reload
MOV TH1,-3 ;Baud rate 19.2 KHz
MOV SCON,#50H ;8 bit, 1 stop, RI En
SETB TR1 ;start timer 1
MOV A,#”B” ;transfer letter B
A_1: CLR T1 ;make sure T1=0
MOV SBUF,A ;transfer it
H_1: JNB T1 H_1 ;stay till last bit is gone
SJMP A_1 ;keep sending B

141. Registers of Timers
TH0-TL0 2 8 bit registers at addresses 8C-8AH
TH1-TL1 2 8 bit registers at addresses 8D-8BH
TH2-TL2 2 8 bit registers at Addresses CD-CCH
TMOD 8 bit register at 89H address, 4H bits for T1 and
4L bits for T0, (GATE), (C/T),(M1),(M0)
M1,M0 determine the 4 modes 0 13 bit timer
Most usable 1 16 bit timer
GATE = 0, using TRx bit SET or CLR 2 8 bit timer
GATE = 1, using ext time intr(p3.4,3.5) 3 split mode
C/T is counter/timer modes, the first uses external clock

142. TCON timer/counter register
• TF1 TCON.7 overflow flag for T1
• TR1 TCON.6 Timer 1 run control bit
• TF0 TCON.5 overflow flag for T0
• TR0 TCON.4 Timer 0 run control bit
• IE1 TCON.3 External Interrupt 1 edge Flg
• IT1 TCON.2 Interrupt 1 type control bit
• IE0 TCON.1 External Interrupt 0 edge Flg
• IT0 TCON.0 Interrupt 0 type control bit
Bit addressable register at address 88H

143. Data from P1 sent to P2 and serial
port data sent to P0, xtl 11.0591 M
ORG 0
LJMP MAIN
ORG 23H
LJMP SERIAL ;jump to serial ISR
ORG 30H
MAIN: MOV P1,#0FFH ;P1 input
MOV TMOD,#20H ;timer 1 mod 2, aut
MOV TH1,#0FDH ;9600 baud rate
MOV SCON,#50H ;8bit, 1 stop, REN En
MOV IE,#10010000B ;enable serial inter
SETB TR1 ;start timer1

144. Data from P1 sent to P2 and serial
port data sent to P0, xtl 11.0591 M
BACK: MOV A,P1 ;read from P1
MOV P2,A ;send data P2
SJMP BACK ;stay in loop
;…………..Serial Port ISR
ORG 100H
SERIAL: JB TI,TRANS ;jump if TI high
MOV A,SBUF ;otherwise due Rx
MOV P0,A ;send to P0
CLR RI ;CPU not clearing
RETI ;return from ISR
TRANS: CLR TI ;CPU not clearing
RETI ;return from ISR
END