Computer archi&mp

Computer Architecture and Microprocessor

Session I Number System Conversions Binary Operations Code Logic Gates Boolean Algebra Registers & Counters Computer Languages

Number System Systematic representation of data in Numerical Format Decimal Number System  0 to 9 Binary Number System  0 and 1 Octal Number System  0 to 7 Hexa Decimal Number System  0 to 9 and A to F

Decimal Number System Uses digits from 0 to 9. Has a base of 10 Value of digit corresponds to its position in the number number X (base) position-1 Example : 495 10 , 84 10

Binary Number System Computer uses the Binary Number System Consists of numbers 0 and 1 Bit ( B inary dig it ) Byte (8 - bits) Example: 1010 2 , 1110 2

Octal Number System Uses the digits from 0 to 7. Has a base of 8 can be represented by a group of 3 bits Example: 123 8 , 435 8

Hexa Decimal Number System Uses the digits from 0 to 15. Numbers from 10 to 15 represented by alphabets A through F Has a base of 16 Can be represented by a group of 4 bits. Example: B3A1 16 , 98C 16

Number System Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hexa Decimal Number System Octal Number System Binary Number System Decimal Number System

Conversion of decimal Number to Hexadecimal Number To convert, divide the decimal number by 16 successively Example To convert 540 to decimal 16 540 16 33 -12 2 - 1 The decimal equivalent of 540 10 = 21C 16

Conversion from Hexadecimal to Decimal Multiply the digits of the number by the powers of 16 and add Example To convert 21C 16 to its decimal equivalent 2 1 C C X16 0 = 12 X 1 = 12 1 X16 1 = 1 X 16 = 16 2 X16 2 = 2 X 256= 512 540

Conversion of Hexadecimal to Binary Number The binary equivalent of each digit is used Example To convert 5B 16 to binary equivalent: 5 B 01011011 2 To convert B316 to binary equivalent: B 3 10110011 2

Conversion of Binary to Decimal Number Sum of product of each digit with 2 raised to the power of positional value Example: To find the decimal equivalent of 1011 2 :

Conversion from Octal to Decimal Multiply the digits of the number by the powers of 8 and add Example To convert 215 8 to its decimal equivalent 2 1 5 5 X 8 0 = 5 X 1 = 5 1 X 8 1 = 1 X 8 = 8 2 X 8 2 = 2 X 64= 128 141

9’s Complement Difference of each digit of a number from 9 Example: To find 9’s complement of 54 : 9 9 5 4 4 5

10’s Complement Equivalent to the negative of a number Obtained by adding 1 to the 9’s complement of a number Example: To find 10’s complement of 54 = 9’s complement of 54 + 1 = 45 + 1 = 46

1’s Complement of binary number Similar to 9’s complement of decimal number Obtained by subtracting each digit from 1 Example To find 1’s complement of 101 1 1 1 1 0 1 0 1 0

2’s complement of a binary number Equivalent to 10’s complement of a decimal number Represents the negative equivalent of that number Example To find the 2’s complement of 1010 = 1’s complement of 1010 + 1 = 0101 + 1 = 0110

Binary Subtraction To subtract 1010 from 1100 Find 2’s complement of 1010 Number : 1010 1’s complement : 0101 2’s complement : 0110 Add 2’s complement of 1010 with 1100 1100 0110 0010

BCD Each digit is represented by four bits 00010101 15 00010100 14 00010011 13 00010010 12 00010001 11 00010000 10 00001001 9 00001000 8 BCD Decimal Number 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 0000 0 BCD Decimal Number

Gray Code Only one bit changes for each consecutive numbers 1000 15 1001 14 1011 13 1010 12 1110 11 1111 10 1101 9 1100 8 Gray Code Decimal Number 0100 7 0101 6 0111 5 0110 4 0010 3 0011 2 0001 1 0000 0 Gray Code Decimal Number

ASCII Codes American Standard Code for Information Interchange 7 bit code Represents upto 128 characters First 3 bits-zone bits Second 4 bits-numeric bits

ASCII Codes Character ASCII Code DLE 10 S0 0F S1 0E CR 0D FF 0C VT 0B LF 0A HT 09 BS 08 BEL 07 ACK 06 ENQ 05 EOT 04 ETX 03 STX 02 SOH 01 NUL 00 Character ASCII Code ! 21 SP 20 US 1F RS 1E GS 1D FS 1C ESC 1B SUB 1A EM 19 CAN 18 ETB 17 SYN 16 NAK 15 DC4 14 DC3 (X-off) 13 DC2 (Tape) 12 DC1 (X-on) 11

ASCII Code 1 31 0 30 / 2F . 2E - 2D , 2C + 2B * 2A ) 29 ( 28 ‘ 27 & 26 % 25 $ 24 # 23 “ 22 Character ASCII Code A 41 @ 40 ? 3F > 3E = 3D < 3C ; 3B : 3A 9 39 8 38 7 37 6 36 5 35 4 34 3 33 2 32 Character ASCII Code

U 55 T 54 S 53 R 52 Q 51 P 50 O 4F N 4E M 4D L 4C K 4B J 4A I 49 H 48 G 47 F 46 E 45 D 44 C 43 B 42 Character ASCII Code j 6B i 6A Characters ASCII h 69 g 67 f 66 e 65 d 64 c 63 b 62 a 61 - ( ) 5F ^ ( ) 5E ] 5D \ 5C [ 5B Z 5A Y 59 X 58 W 57 V 56

DEL 7F ~ 7E } 7D | 7C { 7B z 7A y 79 x 78 w 77 v 76 u 75 t 74 s 73 r 72 q 71 p 70 o 6F n 6E m 6D l 6C k 6B Character ASCII Code

ASCII -8 Code Uses 8 bit code Represents upto 256 characters First 4 bits-zone bits Second 4 bits-numeric bits

Logic Gates NOT gate or Inverter output is opposite of input Truth Table I/P 0/P 0 1 1 0 I/P O/P

AND Gate Truth Table I/P1 I/P2 O/P 0 0 0 0 1 0 1 0 0 1 1 1 I/P1 I/P2 O/P

NAND Gate Truth Table I/P1 I/P2 O/P 0 0 1 0 1 1 1 0 1 1 1 0 I/P1 I/P2 O/P

OR Gate Truth Table I/P1 I/P2 O/P 0 0 0 0 1 1 1 0 1 1 1 1 I/P1 I/P2 O/P

NOR Gate Truth Table I/P1 I/P2 O/P 0 0 1 0 1 0 1 0 0 1 1 0 I/P1 I/P2 O/P

XOR Gate Truth Table I/P1 I/P2 O/P 0 0 0 0 1 1 1 0 1 1 1 0 I/P1 I/P2 O/P

XNOR Gate Truth Table I/P1 I/P2 O/P 0 0 1 0 1 0 1 0 0 1 1 1 I/P1 I/P2 O/P

Boolean Algebra Algebra of binary values(1 & 0) Types of operations OR (+) AND ( . ) NOT (- or ‘ ) Minimizes the basic circuits to perform digital operations

Algebraic Theorems OR Laws A + 0 = A A + 1 =1 A + A = A A + A = 1 AND Laws A . 0 = 0 A . 1 = A A . A = A A . A = 0

Laws of Complementation A = A 1 = 0 0 = 1 If A=0, then A =1 If A=1, then A = 0 Commutative Laws A + B = B + A A .B = B .A Associative Laws (A + B) + C = A + (B + C) = A + B + C (A.B).C = A.(B.C) = A.B.C

Distributive Laws A . (B+C) = A .B + A .C A + B.C = (A + B) . (A + C) Other Expressions A + AB = A A . (A + B) = A A + AB = A + B A . (A + B) = AB AB + AB = A (A + B)(A + B) = A AB + AC = (A + C) . (A + B) (A + B) ( A + C) = AC + AB AB + AC + BC = AB + AC (A + B)(A + C)(B + C) = (A + B)(A + C)

Half Adder Has two inputs (the bits to be summed) Has two outputs (the sum bit and the carry bit) AB CD 00 01 10 11 00 10 10 01

Full Adder – Truth Table a n b n c n s n c n+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

7 Segment LED Display – Truth Table 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 INPUTS X Y Z W A B C D E F G OUTPUT L E G A L D I G I T S 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 E R R O R

TTL Circuit Stands for transistor - transistor logic. Operates between cut-off and saturation. Advantages: Speed good fan – in and fan – out easy interface with other digital circuitry

Flip Flop Stores a binary digit Stable till a signal switches it Types of Types of flip flop S-R flip flop J-K flip flop D flip flop T flip flop

Registers Group of flip-flops Connected in parallel D flip-flop commonly used Shift Register Shifts content unchanged Temporary storage Types: Serial-in, serial-out Serial-in, parallel-out Parallel in, serial-out Parallel in, parallel out

Counters Counts no. of pulses Modulus of Counter Binary Counter Decade Counter Pre settable Counter Binary Counter CLK 3 2 1 0 J k Q Q J k Q Q J k Q Q J k Q Q

Types of Counters Up Counter Down Counter Up-Down Counter Controlled Counter Ring Counter Synchronous Asynchronous

Computer Languages Machine Language – 0 and 1 Assembly Language – mnemonics – assembler High Level Language – English like language – Interpreters and Compilers

Execution of Assembly Language program One to One Translation Source Program Assembler Object Program Loader Floppy Disk Floppy Disk

Execution of High Level Language Source Code Translator Object Code 1 Object Code 2 Object Code 3 One to Many Translation

Compiler & Interpreter Interpreter translates line by line - Slower Compiler translates the entire code - faster

Session II Microprocessor – an Introduction General Architecture of Microprocessor Memory I/O Architecture of 8085 Microprocessor

Microprocessor – An Introduction Programmable Logical device Functionality manipulates data Controls timing of various operations communicates with peripherals Applications Automation & Control

Architecture & Operations of MPU Architecture - Logical design of microprocessor Types of Operations Microprocessor initiated operations Internal Data Operations Peripheral initiated Operation

Microprocessor initiated operations Communications Operations Memory Read Memory Write I/O Read I/O Write Steps involved Location Identification Transfer of data Providing Timing or synchronization signals

Requirement Address Bus Unidirectional Arbitrary number – (commonly used 16) Capable of Addressing 2 n Data Bus Bidirectional Decides the range of data being handled Determines the word length and the register size

Control Bus A number of Single lines Provides timing signals Communication Process To Read an instruction Location is identified by placing the address in Address Bus A pulse for initiating a READ is sent Data Bus brings the data to MPU

Internal Data Operations Processing of Data and its Storage Arithmetic & Logical Operation Condition Testing Order of Execution Storing of Data Requirement Accumulator Flag Register General purpose Registers Program Counter Stack

(8085 Microprocessor) Accumulator Performs Arithmetic and logical Operations 8 bit Register Flag Register Used for Decision Making 5 Flags – Carry, Zero, Auxiliary Carry, Sign, Parity Program Status Word

Registers Stores Data during Execution 6 8-bit registers – B, C, D, E, H and L Register Combination – BC, DE and HL Program Counter (PC) 16 Bit Memory Pointer Sequences the Execution Stack Pointer (SP) 16 Bit Memory Pointer Points to location in R/W Memory

Peripheral initiated Operation Operations initiated by external devices Reset Program Counter is cleared Interrupt Normal Execution interrupted to execute Service Routine Ready Synchronizes MPU operations with Peripherals Hold Peripherals takes Control of Buses

Memory Stores Binary Values Types Read Write Memory (R/W M) Read Only Memory (ROM) R/W Memory (Random Access Memory) Volatile processes data Types:- Static & Dynamic

Static R/W Memory Flip-flops Stored as Voltage Dynamic R/W Memory MOS Transistor Stored as charges Faster Refreshing Circuit

ROM Memory Non Volatile Used for subroutines Cheap & Dense Types: - Masked ROM PROM (Programmable Read Only Memory) EPROM (Erasable Programmable Read Only Memory) EEPROM (Electrically Erasable PROM)

Memory Organization A memory requires: Chips containing Registers Chip Select line R/W line Address lines I/O lines Memory Map Assigning a unique address for each register

Size of Memory Number of Register Number of I/O lines CS Control Logic A D D R E S S D E C O D E R R/W D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A 2 A 1 A 0 110 110 101 100 011 010 001 000

Input / Output Communicates to the external world Methods of Communication Peripheral or Direct I/O Memory-Mapped I/O

Peripheral or Direct I/O IN/OUT Transfers data 8 Address Lines - 256 devices – Port Numbers Uses Control Lines – IOW & IOR Memory-Mapped I/O 16 Address Lines Memory Map is shared Uses Control Lines – MEMW & MEMR

Interfacing Devices Tri-State Device 3 stages – logic 1, logic 0 and high impedance Buffer Logic circuit which amplifies the current Latch a D flip-flop Types :- Transparent Latch Positive Edge Triggered D G Q Q D CK Q Q PR CLR

Decoder Displays an output based on the combination of input Encoder Outputs a code based on the input Output Output Input Input 2 to 4 Decoder 2 to 4 Encoder

8085 Microprocessor Features 8 bit Has 40 pins Multiplexed Address/ Data Bus

8085 PINOUT X 1 X 2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 V SS V cc HOLD HLDA CLK(OUT) RESET IN READY IO/M S1 RD WR ALE S0 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

+5V GND Serial I/O Ports Interrupts & Externally Initiated Signals External Signal Acknowledgement Control And Status Signals 8085 Signals RESET CLK OUT OUT X1 X2 Vcc Vss ALE S0 S1 IO/M RD WR SID SOD TRAP RST 7.5 RST 6.5 RST 5.5 INTR READY HOLD RESET IN INTA HLDA High-Order Address Bus Multiplexed Address/Data Bus A 15 A 8 AD 7 AD 0

8085 Microprocessor Signal Groups Address Bus UniDirectional 8 Higher Order Address Bus Multiplexed Address/Data Bus BiDirectional Bus Multiplexing Latching of Low - order Address Bus – ALE

Control and Status Signal ALE (Address Latch Enable) Generated in the beginning of each operation Latches low - order address from the multiplexed bus RD (Read) Active low Control Signal Reads from Memory / IO WR (Write) Active low Control Signal Writes to selected Memory / IO

IO/M RD 8085 WR A 15 A 8 ALE AD 7 AD 0 EN LATCH A 15 A 8 A 7 A 0 D 7 D 0 Data Bus MEMR MEMW IOR IOW Control Signals

IO/M High – IO Operation Low – Memory Operation S 1 and S 0 Status Signal – rarely used Identifies various operations S1 So Desc. 0 0 HALT 0 1 WRITE 1 0 READ 1 1 FETCH

Power Supply and Clock Frequency +5V power supply (Vcc) 3 MHz clock (X1 & X2) CLK – Used as System Clock for other devices Interrupts and Externally Initiated Operations Interrupts transfer the program control to specific memory location INTR (Interrupt Request) A general-purpose interrupt . INTA (Interrupt Acknowledge) Acknowledges an interrupt

RST 7.5 (Restart Interrupt) Highest priority Vectored Interrupt RST 6.5 (Restart Interrupt) Vectored interrupt with a priority less than RST 7.5, but more than RST 5.5 and INTR. RST 5.5 (Restart Interrupt) Vectored interrupt with the least priority among Restart Interrupts but more priority than INTR signals. TRAP (Input) A non-maskable restart interrupt. highest priority of any interrupt. Externally initiated signals are instantiated by an external device

HOLD Indicates a peripheral’s request to use address and data buses. HLDA ( Hold Acknowledge) Acknowledges the HOLD request. READY Delays microprocessor’s operation to work in pace with the slow peripherals connected to it. RESET IN Sets program counter to zero The buses are tri-stated and MPU is reset. RESET OUT Indicates MPU is being reset Can be used to reset other devices.

Serial I/O Ports SID (Input) Serial input data Line The data on SID is loaded into accumulator when a RIM instruction is executed. SOD (output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Address Buffer Temp Reg. (8) Arithmetic Logic Unit (ALU) (8) Flag (5) Flip-flops Data Address Buffer (8) Multiplexer Timing and Control CLK Reset GEN Control Status DMA Reg. Select Serial I/O Control SID Interrupt Control TRAP RST 7.5 RST 6.5 RST 5.5 INTA INTR SOD Ready RD WR ALE S 0 S 1 IO/M HLDA RESET OUT RESET IN HOLD A 15 – A 8 Address Bus AD 7 – AD 0 Address/Data Bus X1 x2 Register Array Accumulator (8) Instruction Decoder and Machine Cycle Encoding Instruction Register (8) W Temp. Reg. Z Temp. Reg. B Reg. D Reg. H Reg. Stack Program Counter C Reg. E Reg. L Reg. Address Latch (16)

Registers Has the Memory Pointer Address SP (Stack Pointer) 16 Bits Has the Program Pointer Address PC (Program Counter) 16 Bits H & L combined to form 16 Bits L 8 Bits H 8 Bits D & E combined to form 16 Bits E 8 Bits D 8 Bits B & C combined to form 16 Bits C 8 Bits B 8 Bits Arithmetic Operations Logical Operations A (Accumulator) 8 Bits

Flags D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CY P AC Z S Set – Carry Exists Reset – No Carry exists Carry CY Set – Even Reset – Odd Parity P Set – Carry From D3 to D4 Reset – No Carry From D3 to D4 Auxiliary Carry AC Set – Zero Reset – Non-Zero Zero Z Set – Positive Reset – Negative Sign S

Bus Timings Sequence of operations called instruction cycle executes an instruction Instruction Cycle is divided into few basic machine cycles Machine cycles are in turn divided into System Clock Period. Example: To fetch a data 10101010 from a location 2005H

T1 T2 T3 CLK A 15 – A 8 AD 7 –AD 0 ALE IO/M RD Low -Order Memory Address Memory Contents M High –Order Memory Address

ALU Instruction Decoder Control Logic Address Bus Data Bus Memory B D H Stack Program Counter C E L

Instruction Set of 8085 Instruction A command to perform a given task. A binary pattern designed inside a microprocessor to perform a specific function on a specified data. Instruction Set Entire group of instructions that determines what functions the microprocessor can perform. Parts of Instruction: Task to be performed – operation code (opcode) Data to be operated on – operand.

Classification Instruction Word Size One-word or 1-byte instructions Two-word or 2-byte instructions Three-word or 3-byte instructions Functionality Data transfer (copy) operations Arithmetic operations Logical operations Branching operations Machine-control operations.

ONE-BYTE INSTRUCTIONS Includes opcode and operand in single byte. Operand(s) are internal register Example: MOV C,A Both operand registers are specified. ADD B The operand B is specified and the accumulator is assumed. CMA Accumulator is assumed to be the implicit operand

TWO-BYTE INSTRUCTIONS Uses two-bytes First byte specifies the operation code Second byte specifies the operand. Source operand is a data byte Example MVI A, 32H THREE-BYTE INSTRUCTION First byte specifies the opcode Following two bytes specify the 16-bit address. second byte – low-order address or data third byte is the high-order address or data Example JMP 2085H, LXI H, 2050H

DATA TRANSFER (COPY) OPERATIONS Copies data from a location called a source to another location called a destination Contents of source not modified Types of data transfer : Between Registers. Specific data byte to a register or a memory location. Between a memory location and a register Between an I/O device and the accumulator.

MOV Copies data from one register to another Syntax: MOV R d , R s Example: MOV A, B MVI Copies 8 Bit data to a specific register Syntax: MVI Rd, D Example: MVI C, 5

OUT Copies the Contents of Accumulator to Port Syntax: OUT PortNo. Example: OUT 56 IN Copies the Contents of the Port to Accumulator Syntax: IN PortNo. Example: IN 57

Between Registers Between Registers and Memory 1 Bytes Copies data From Source Register Rs to Destination Register Rd Rd, Rs MOV Description Operand OP Code Description Bytes Operand OP Code Copies data From memory M to Destination Register Rd 1 Rd, M MOV Copies data From Source Register Rs to Memory M 1 M, Rs MOV

Data to/from Register, Memory or I/O Port Copies the content of the Register L to memory location pointed out by 16 bit address and content of Register H to next memory location 3 16 Bit Address SHLD Copies the content of the memory location pointed out by 16 bit address to Register L and content of next memory location to Register H 3 16 Bit Address LHLD Loads the Data to the Specified Register 2 R, Data (8 Bits) MVI Copies data From Accumulator A to Specified port Address 2 8 Bit Port Address OUT 2 Bytes Copies data From Specified port Address to Accumulator A 8 Bit Port Address IN Description Operand OP Code

Data to/from Register, Memory or I/O Port Contents of Register H is exchanged with Register D and Contents of Register L is exchanged with Register E 1 None XCHG Loads the 16 bit data into the Register Pair 3 RP, 16 Bit Data LXI Copies the content of Memory Location Accumulator A to Specified in Register Pair B or D 1 RP B/D STAX Copies the content of Accumulator A to Memory location specified by 16 bit address 3 16 Bit Address STA Copies the content of Memory Location Specified in Register Pair B or D to Accumulator A 1 RP B/D LDAX 3 Bytes Copies the content of Memory location specified by 16 bit address to Accumulator A 16 Bit Address LDA Description Operand OP Code

ARITHMETIC OPERATIONS Performs addition, subtraction, increment and decrement. Addition Adds an 8-bit data to the accumulator Carry Flag is set if the sum exceeds 8-bits ADD Adds a register’s content to the accumulator Syntax: ADD R ADI Adds an 8-bit data to the accumulator Syntax: ADI 8-bit Data

Subtraction Subtracts an 8-bit data to the accumulator and the stores the difference in it. Performed in 2's complement method SUB Subtracts a register’s content from the accumulator Syntax: SUB R SUI Subtracts an 8-bit data from the accumulator Syntax: SBI 8-bit Data

Increment/Decrement Increments/Decrements 8-bit content by 1. Increments/Decrements 16-bit contents of a register pair (such as BC) INR Increments the content of a register Syntax: INR B DCR Decrements the content of a register Syntax: DCR B

Arithmetic Operations The content of the specified Register or Memory is decremented by 1 1 R/M DCR The content of the specified Register or Memory is incremented by 1 1 R/M INR 8 Bit Data is subtracted from the content of Accumulator and the result is stored in Accumulator 2 8 Bit Data SUI 8 Bit Data is added to the Accumulator content and stores the result in Accumulator 2 8 Bit Data ADI Content of the Register or Memory is subtracted from the content of Accumulator and the result is stored in Accumulator 1 R/M SUB 1 Bytes Content of the Register or Memory is added to the content of Accumulator and the result is stored in Accumulator R/M ADD Description Operand OP Code

LOGICAL OPERATIONS Performs logical operations with accumulator content AND, OR, Exclusive-OR Performed on an 8-bit data and accumulator content AND Logically AND the Register Content with Accumulator Content Syntax: AND R ANI Logically ANd Immediately 8-Bit Data with Accumulator Content Syntax: ANI 14

ORA Logically OR contents of Register with Accumulator Syntax: ORA C ORI Logically OR Immediately 8 Bit Data with Accumulator Syntax: ORI D

XRA Logically Exclusive - OR the contents of Register with Accumulator Syntax: XRA C XRI Logically Exclusively - OR immediately 8 Bit Data with Accumulator Syntax: XRI 6

CMA Complements the contents of accumulator No Flags are affected Syntax: CMA Rotate Shifts Bits in the accumulator either left or right Compare Compares an 8-bit data with accumulator content

BRANCHING OPERATIONS Alters program execution sequence either conditionally or unconditionally. Jump Conditional jump Alters program sequence when condition test is true Unconditional jump Alters program sequence without condition checking Call Changes sequence of a program by calling a subroutine Return Changes sequence of a program by returning from a subroutine

Unconditional jump JMP The program control is transferred to a particular memory address Syntax: JMP Address Example: JMP F200

Conditional Jump Based on Condition of the flags All Instructions are followed by a 16-Bit address JC Transfers program control to a particular address if Carry Flag is Set JNC Transfers program control to a particular address if Carry Flag is not Set JZ Transfers program control if Zero Flag is Set JNZ Transfers program control if Zero Flag is not Set

JP Transfers program control if Sign Flag is not Set JM Transfers program control if Sign Flag is Set JPE Transfers program control if Parity Flag is Set JPO Transfers program control if Parity Flag is not Set

MACHINE CONTROL OPERATIONS Controls machine functions Examples: Halt, Interrupts, No Operation Halt Processor Stops Executing Syntax: HLT No Operation No Operation is performed Syntax: NOP

8085 ADDRESSING MODES Addressing Modes specifies various formats for operands a register, an input/ output port, or an 8-bit number Types: Immediate addressing. Register addressing. Direct addressing. Indirect addressing.

Immediate Addressing Data is present in the instruction Example: MVI R,data Register addressing Data is provided through the registers. Example: MOV Rd, Rs

Direct addressing Accepts data from or sends data to the outside device. Example: IN 00H or OUT 01H Indirect Addressing Effective Address is calculated by the processor The contents of the address (and the one following) is used to form a second address where the data is stored

Assembly Language Programming Memory Address 16 bit address of System Memory Machine Code Hexadecimal entered in System Memory Opcode Abbreviated Symbols specified by manufacturer Operand Item to be processed Comments Documentation explaining purpose of instructions used

Assembly Language Program Program to accept and display a number Task Mnemonics Load Register B with 4EH MVI B, 4EH Copy the Number to Accumulator MOV A, B Sent the Number to Output Port OUT, Port1 End of the Program HLT

Programming Format End of the Program None HLT Sends 37H to Port ‘ Port1 ’ Port1 OUT Copies Content of Register B to Accumulator A, B MOV Loads 37H to Register B B, 37H MVI Description Operand OP Code

Arithmetic Operations The content of the specified Register or Memory is decremented by 1 1 R/M DCR The content of the specified Register or Memory is incremented by 1 1 R/M INR 8 Bit Data is subtracted from the content of Accumulator and the result is stored in Accumulator 2 8 Bit Data SUI 8 Bit Data is added to the content of Accumulator and the result is stored in Accumulator 2 8 Bit Data ADI Content of the Register or Memory is subtracted from the content of Accumulator and the result is stored in Accumulator 1 R/M SUB 1 Bytes Content of the Register or Memory is added to the content of Accumulator and the result is stored in Accumulator R/M ADD Description Operand OP Code

Loops Executes a set of instructions repeatedly Types Continuous Loop Conditional Loop Continuous Loop Uses unconditional jump Conditional Loop Uses Conditional Jump

Counter Executes certain set of instructions a specified number of times Uses the concept of conditional loop Can be incremented or decremented

First Program Load a number to Register B and display the output in Port1 Steps: 1. Load register B with a Number 2. Send to Output to Port1 Algorithm Start Input Number In Register Output Number Stop

Setting up a Counter Executes certain set of instructions a specified number of times A Register is Loaded with a number Using INR (Increment) or DCR (Decrement) the number is Incremented or Decremented Uses the concept of conditional loop Time delay required If the register reaches the final count the loop is terminated

Flowchart Start Initialize Update Is the Final Count End No Yes

T - States One Subdivision of the operation performed in one clock period Frequency & Time/Clock Period Frequency in the Processing Speed of a Processor Time Period = (Frequency) -1 Time Period = 1 Frequency

Time Delay Uses the concept of counter No. of Counts depends on T-States. Calculation of Time for Execution: Clock Period = 1/frequency Time for Execution of Instruction = No. of T-States X Clock Period

Simple Time Delay Program MVI B, 77H - 7 T-States Loop: DCR B - 4 T-States JNZ LOOP - 10/7 T-States HLT - 5 T-States

Time Delay Time Delay in executing the Loop T L = (Time Period T X Loop T-States X Equivalent Decimal Number N 10 ) Total Time Delay in executing the Loop T LA = T L – Time Adjustment

Time Delay for the Program Let us Assume the Frequency of the Processor is 2MHz f = 2 MHz T = 1/f T = 1/2 MHz T = 0.5 µSec. Count FFH = 255 10 T-States Inside the Loop DCR B - 4 JNZ LOOP - 10 Total = 14 T-States Outside the Loop MVI B, FFH - 7 HLT - 5 Total = 12

Time Delay Inside the Loop T L = T x T States x N 10 T L = 0.5 µSec. x 14 x 255 T L = 1785 µSec. T L = 1.785 mSec. Total Time T LA = 1.785 mSec. - (10-7) x 0.5 µSec. T LA = 1.785 mSec. - 0.0015 mSec. T LA = 1.7835 mSec.

Total Time Delay Time to Execute the instruction outside the loop T D = + Time taken to execute the instruction inside the loop T D = T O + T LA Where T O = T-States Outside the loop X Time Period

Total Time Delay T O = 12 x 0.5 µSec. T O = .006 mSec. T D = T O + T LA T D = 0.006 mSec + 1.7835 mSec. T D = 1.7895 mSec. T D ≈ 1.8 mSec. Total Time Required to execute the program is 1.8 milli Seconds (Approx.)

Note: Time Delay can be Varied by changing the Count number FFH. To Increase the time delay more the 1.8 mSec. the user should use the Additional Instruction or Register Pair.

Time Delay Using Register Pair Program LXI B, FFFFH - 10 T-States Loop: DCX B - 6 T-States MOV A, C - 4 T-States ORA B - 4 T-States JNZ Loop - 10/7 T-States HLT - 5 T-States

Time Delay Let us Assume the Frequency of the Processor is 2MHz f = 2 MHz T = 1/f T = 1/2 MHz T = 0.5 µSec. T-States Inside the Loop DCX B - 6 MOV A,C - 4 ORA B - 4 JNZ LOOP - 10 Total = 24 T-States Outside the Loop LXI B, FFFFH - 10 HLT - 5 Total = 15 Count FFFFH = 65535 10

Time Delay in the Loop T L = T x T States x N 10 T L = 0.5 µSec. x 24 x 65535 T L = 786420 µSec. T L = 786.42 mSec. Total Time T LA = 786.42 mSec. - (10-7) x 0.5 µSec. T LA = 786.42 mSec. - 0.0015 mSec. T LA = 786.4185 mSec.

Total Time Delay T O = 15 x 0.5 µSec. T O = .0075 mSec. T D = T O + T LA T D = 0.0075 mSec + 786.4185 mSec. T D = 786.426 mSec. T D ≈ 786.4 mSec. Total Time Required to execute the program is 786.4 milli Seconds (Approx.)

Flowchart Start Initialize Loop2 Update Is the Final Count End Initialize Loop1 Update Is the Final Count No No Yes Yes

Time Delay Using Loop within a Loop Program MVI B, FFH - 10 T-States Loop2: MVI C, FFH - 10 T-States Loop1: DCR C - 6 T-States JNZ Loop1 - 10/7 T-States DCR B - 6 T-States JNZ Loop2 - 10/7 T-States HLT - 5 T-States L1 L2

Time Delay Let us Assume the Frequency of the Processor is 2MHz f = 2 MHz T = 1/f T = 1/2 MHz T = 0.5 µSec. T-States Inside the Loop1 DCR C - 4 JNZ Loop1 - 10 Total = 14 T-States Inside the Loop2 DCR C - 4 JNZ Loop1 - 7 DCR B - 4 JNZ Loop2 - 10 Total = 21 Count Loop1 Count = FFH = 255 10 Loop2 Count = FFH = 255 10 T-States Outside the Loops MVI B, FFH - 7 MVI C, FFH - 7 HLT - 5 Total = 19

Time Delay in the Loop1 T L1 = T x T States x N 10 T L1 = 0.5 µSec. x 14 x 255 T L1 = 1785 µSec. T L1 = 1.785 mSec. Total Time T LA1 = 1.785 mSec. - (10-7) x 0.5 µSec. T LA1 = 1.785 mSec. - 0.0015 mSec. T LA1 = 1.7835 mSec.

Time Delay in the Loop2 T L2 = (T LA1 + T-States X Time Period) X Count N 10 T L2 = (1.7835 mSec. + 21 x 0.5 µSec.) x 255 T L2 = 457470 µSec. T L2 = 457.47 mSec. Total Time T LA2 = 457.47 mSec. - (10-7) x 0.5 µSec. T LA1 = 457.47 mSec. - 0.0015 mSec. T LA1 = 457.4685 mSec.

Total Time Delay T O = 19 x 0.5 µSec. T O = .0095 mSec. T D = T O + T LA2 T D = 0.0095 mSec + 457.4685 mSec. T D = 457.478 mSec. T D ≈ 457.5 mSec. Total Time Required to execute the program is 457.5 milli Seconds (Approx.)

Sample Program Write a program to count continuously in hexadecimal from FFH to 00H in a system with a clock period of 0.5 µSec. Use Register D to setup one millisecond delay between each count and display the count in one of the Output Ports Note: To Count from FFH the register to be initialized with 0OH Separate Time Delay Loop to be Set The Count to be Displayed in Output Port

Program MVI E, 00H - 7 T-states Count: DCR E - 4 T-states MVI D, Count No. - 7 T-states Delay: DCR D - 4 T-states JNZ Delay - 10/7 T-states MOV A, B - 4 T-states OUT Port - 10 T-states JMP Count - 10 T-states

To Calculate Time Delay Count No. T = 0.5 µSec. T L = (T-States x T) x Count No. T L = (14 x 0.5 µSec.) x Count No. T L = 0.007 mSec. x Count No. T LA = (0.007 mSec. x Count) - 0.0015 mSec. T O = 35 x 0.5 µSec. = 0.0175 mSec . T D = (0.007 mSec. x Count) - 0.0015 mSec. + 0.0175 mSec. 1 mSec. = (0.007 mSec. x Count) + 0.016 mSec. 1 mSec. – 0.016 mSec. Count No . = = 140.571 ≈ 141 10 ≈ 8CH 0.007 mSec.  Count No. = 8CH, 8CH should be loaded into register D to set 1 millisecond delay

Stack Set of Memory Locations in R/W memory Used to store binary information temporarily during the execution of a program Beginning of Stack is defined using LXI SP, 16 bit Address Stack pointer is decremented by one The byte stored to stack with the address specified in Stack Pointer The Storage & Retrieval on stack follows LIFO (Last in First Out)

Storing Register Pair Content to Stack Using Inst. PUSH the contents of a Register Pair can be copied to stack Using Inst. POP the contents from the stack is copied to Register Pair Description Bytes Operand OP Code Copy the content of the stack which is pointer by stack pointer to lower order register (C, E, L, Flags) and increment the stack pointer by one then Copy the content of the stack which is pointer by stack pointer to higher order register (B, D, H, A) 1 Rp. POP Decrement the Stack Pointer by one the content of higher order (B, D, H, A) is copied into stack then the Stack Pointer is again decremented the lower order (C, E, L, Flags) is copied into stack 1 Rp. PUSH

Stack Instructions PUSH B - From Rp. BC to Stack PUSH D - From Rp. DE to Stack PUSH H - From Rp. HL to Stack PUSH PSW - From Accumulator & Flags to Stack POP B - From Stack to Rp. BC POP D - From Stack to Rp. DE POP H - From Stack to Rp. HL POP PSW - From Stack to Accumulator & Flags Note: PSW stands for Program Status Word

Example: Program: 1 LXI SP, 2000H 2 LXI H, 4253H 3 PUSH H 4 NOP 5 POP B 6 HLT

Register Contents after executing first 2 Instructions A B D H SP Register Contents after executing PUSH Instructions X X 2000 53 42 A B D 1FFE H 1FFF SP 2000 X X 2000 53 42 X 42 53 Memory

Register Contents after executing POP Instructions A Flags B C D E H L SP 53 42 2000 53 42 X 42 53 Memory

Program to Clear all Flags , Load 00H in the accumulator and demonstrate the zero flag is not affected by data transfer instruction. Logically OR the accumulator with itself to set the zero flag, and display the flag at Port1 or store all the flags on the stack. LXI SP, 2000H - Initialize Stack Pointer MVI L, 00H PUSH H To Clear Flags POP PSW MVI A, 00H - Loading Accumulator with 00H A Data Transfer Instruction PUSH PSW Getting Flag content to Reg. L POP H

MOV A, L Display Flags OUT Port1 ORA A - Reset CY & AC PUSH PSW Getting Flag content to Reg. L POP H MOV A, L ANI 40H Masking all flags except Z & Display OUT Port1 HLT - End of the Program

Subroutine It is group of Instructions written separately from the main program to perform a function no. of times in the main program. If a Time Delay is required for no. of times in a main program, to avoid repetition of same delay instruction, Subroutine is used Instruction Description Bytes Operand OP Code The Program Sequence is transferred from subroutine to calling program. 1 None RET The Program Sequence is transferred to the specified 16 bit address 3 16 bit address CALL

CALL & RET Call Inst. Saves the contents of Program Counter on the stack Jumps unconditionally to the memory location specified by 16 bit address (Note: Conditional Call Statements are also there) RET inst. Copies the content in the top two location of the stack Unconditional Return from Subroutine (Note: Conditional Return Statements are also there)

Example End of Subroutine RET 3002H Instructions of Subroutine Inst. 3001H Instructions of Subroutine Inst. 3000H End of Main Program HLT 2008H Other Instructions Inst. 2007H Calling the subroutine at 3000H CALL 3000H 2004H Initialize the stack pointer with 2400H LXI SP, 4000H 2000H Description Instruction Mem. Add.

Flow of Subroutine Main Program 2000H Subroutine … 2004H 3000H Start 2005H 3001H 2006H 3002H End … … … … …

Data Transfer During CALL Instruction 30 2006H 00 2005H CD 2004H Code (H) Mem. Add.

PC, Stack & SP during CALL Inst. CALL Program Counter Stack Pointer Register 3FFE 3FFF 4000 STACK 2007 2006 2005 2004 XX 20 07 3FFE 3FFF 4000

Data Transfer During CALL Instruction 20 07 (W) (Z) 2007 (W) (Z) M 1 Opcode Fetch 20 20 (Stack – I) 3FFF 4000 M 3 Opcode Fetch 07 07 (Stack) 3FFE 3FFF M 2 Opcode Fetch - C9 Opcode 3003 3002 3FFE M 1 Opcode Fetch Internal Registers (W) (Z) Data Bus (DB) Program Counter Address Bus (AB) Stack Pointer 3FFE Machine Cycles

Traffic Signal Controller Program to provide given on/off timer to three traffic lights (Green, Yellow, and Red) and two pedestrian signs (WALK and DON’T WALK). The signal lights and signs are turned on/off by the data bits of an output port as shown below: Lights Data Bits On Time 1. Green D0 15 seconds 2. Yellow D2 5 seconds 3. Red D4 20 seconds 4. WALK D6 15 seconds 5. DON’T WALK D7 25 seconds The traffic and pedestrian flow are in the same direction; the pedestrian should cross the road when the Green light is on.

The problem is primarily concerned with providing various time delays for a complete sequence of 40 seconds. The on/off times for the traffic signals and pedestrian signs are as follows:

The Green light and the WALK sign can be turned on by sending data byte 41H to the output port. The 15-second delay can be provided by using a 1-second subroutine and a counter with a count of 1510. Similarly, the next two bytes, 84H and 90H, will turn on/off the appropriate lights/signs as shown in the flowchart. The necessary time delays are provided by changing the values of the count in the counter.

Main Program LXI SP, XX99 - Initialize Stack Pointer with XX99H START: MVI A, 41H - Loading Accumulator with Pattern for Green & Walk OUT PORT1 - Turn on corresponding lights MVI B, 0FH - Reg. B is used to count 15 seconds CALL DELAY - Call subroutine of one second delay MVI A, 90H - Loading Accumulator with Pattern OUT PORT1 - Turn on corresponding lights MVI B, 05 - Reg. B is used to count 5 seconds CALL DELAY - Call subroutine of one second delay MVI A, 90H - Loading Accumulator with Pattern OUT PORT1 - Turn on corresponding lights MVI B, 14H - Reg. B is used to count 20 seconds CALL DELAY - Call subroutine of one second delay JMP START - Go to START to repeat the Sequence

Subroutine Delay: PUSH D Save the contents of DE & Accumulator PUSH PSW Sec: LXI D, COUNT No. - Load Rp. DE with Count No. Loop: DCX D - Decrement Rp. DE by one MOV A, D Check Rp. DE is Zero ORA E JNZ Loop - Jump to Loop if Zero Flag is not Set DCR B - Decrement Reg. B JNZ Sec - Jump to Sec if Zero Flag is not Set POP PSW POP D Retrieve contents of saved Registers RET - Returning to Main Program

BCD – Binary Coded Decimal 86 10 = (8 x 10) + 2 Converting a 2-digit BCD number into its binary equivalent requires the following steps: Separate an 8-bit packed BCD number into two 4-bit unpacked BCD digits: BCD1 and BCD2. Convert each digit into its binary value according to its position. Add both binary numbers to obtain the binary equivalent of the BCD number.

Example Convert (86)BCD into its binary equivalent Solution: 86 10 = 1000 0110 BCD 0111 0010 00000110 Unpacked BCD1 00001000 Unpacked BCD2 Multiply BCD2 by 10 (8 x 10) Add BCD1 to the answer in Step 2.

2 Digit BCD to Binary Conversion A BCD number between 0 and 99 is stored in a R/W memory location called the Input Buffer. Write a main program and a conversion subroutine (BCDBIN) to convert the BCD number into its equivalent binary number. Store the result in a memory location defined as the Output Buffer. LXI SP, “STACK” - Initialize stack LXI H, “INBUF” - Initialize Input Location LXI B, “OUTBUF” - Initialize Output Location MOV A, M - Input of BCD No. CALL BCDBIN - Calling Subroutine STAX B - Storing Binary No. to Output Buf. HLT - End of the Program Main Program

Subroutine BCDBIN; BCD to Binary ; I/P: packed BCD in Acc. ; O/P: Binary in Acc. PUSH B - Save Rp. MOV B, A - Copies Acc. Contents to Reg. B ANI 0FH - ANDing (A) with 0FH to mask MSB MOV C, A - Copies Acc. Contents to Reg. C MOV A, B - Copies Reg. B contents to Acc. ANI F0H - ANDing (A) with F0H to mask LSB RRC RRC Making MSB as LSB RRC RRC MOV D, A - Copies Acc. Contents to Reg. D XRA A - Clearing Acc. & Flags Cont.

MVI E, 0AH - Load Reg. E with 0AH = 10 10 Sum: ADD E - Add (E) to (A) DCR D - Decrement (D) by one JNZ Sum - Jump to location Sum in Zero flag is reset ADD C - Add (C) to (A) POP B - Retrieve (BC) RET - Returning to Main Program Cont.

Binary to BCD A binary number is stored in memory location BINBYT. Convert the number into BCD, and store each BCD as unpacked BCD digits in the Output Buffer. To perform this task, write a main program and two subroutines: one to supply the powers of ten, and the other to perform the conversion. Main Program START :LXI SP, STACK - Initialize stack pointer LXI H, BINBYT - Point HL index where binary number is stored MOV A, M - Transfer byte CALL PWRTEN - Call subroutine to load powers of 10 HLT - End of the Program

Subroutine PWRTEN PWRTEN ; Loads the powers of 10 in register B and calls the binary to BCD ;I/P: Binary number in the accumulator ;O/P: Powers of ten and store BCD 1 in the first Output-Buffer ;Calls BINBCD routine and modifies register B : LXI H, OUTBUF - Point HL index to Output-Buffer memory MVI B, 64H - Load 100 in register B CALL BINBCD - Call conversion MVI B, 0AH - Load 10 in register B CALL BINBCD - Calls BINBCD subroutine MOV M, A - Store BCD 1 RET - Returning to Main Program

Subroutine BINBCD BINBCD ;Converts a binary number into BCD and stores BCD2 and ;BCD3 in the Out put Buffer. ;I/P: Binary number in accumulator and powers of 10 in B ;O/P: BCD2 and BCD3 in Output Buffer ;Modifies accumulator contents :MVI M, FFH - Load buffer with (0 -1) NB: INR M - Clear buffer and increment for each subtraction SUB B - Subtract power of 10 from binary number JNC NB - Is number > power of 10? If yes, add 1 to buffer ADD B - If no, add power of 10 to get remainder INX H - Go to next buffer location RET - Returning to Subroutine PWRTEN

BCD to 7 Segment Display Write a main program and two subroutines, called UNPAK and LEDCOD, to unpack the BCD numbers and select an appropriate seven-segment code for each digit. The codes should be stored in the Output-Buffer memory. Main Program LXI SP, STACK - Initialize stack pointer LXI H, XX50H - Point HL index where BCD digits are stored MVI D, 03H - Number of digits to be converted is placed in D CALL UNPAK - Call subroutine to unpack BCD numbers HLT - End of Program

Subroutine UNPACK UNPAK; This subroutine unpacks the BCD number into two single digits. ;I/P: Starting memory address of the packed BCD numbers in HL ;registers: Number of BCDs to be converted in register D ;O/P: Unpacked BCD into acc. and Output Buffer address in BC ;Calls subroutine LEDCOD LXI B, BUFFER - Point BC index to the buffer memory NBCD : MOV A, M - Get packed BCD number ANI F0H - Masked BCD1 RRC Rotate four times to place BCD2 as RRC unpacked single digit BCD RRC RRC

Subroutine UNPACK CALL LEDCOD - Find seven-segment code INX B - Point to next buffer location MOV A, M - Get BCD number again ANI 0FH - Separate BCD1 CALL LEDCOD - INX B - INX H - Point to next BCD DCR D - Conversion complete, reduce BCD count JNZ NBCD - If all BCDs are not yet converted, go back to convert next RET - Return to Main Program

Subroutine LEDCOD LEDCOD ;This subroutine converts an unpacked BCD into its seven-segment ; LED code ;I/P: An unpacked BCD in accumulator ;Memory address of the buffer in BC register ;O/P: Stores seven-segment code in the output buffer : PUSH H - Save HL contents of the caller LXI H, CODE - Point index to beginning of 7-segment code ADD L - Add BCD digit to starting address of code MOV L, A - Point HL to appropriate code MOV A, M - Get seven-segment code STAX B - Store code in buffer POP H - Retrieve (HL) Rp. RET - Return to Subroutine UNPACK

Binary to ASCII Write a program to Transfer the byte to the accumulator, Separate the two nibbles (as 09 and 0F). Call the subroutine to convert each nibble into ASCII Hex code and Store the codes in memory locations XX60H AND XX61H. Write a subroutine to convert a binary digit (0 to F) into ASCII Hex code.. An 8-bit binary number (e.g., 9FH) is stored in memory location XX50H. Main Program LXI SP, STACK - Initialize stack pointer LXI H, XX50H - Point index where binary number is stored LXI D, XX60H - Point index where ASCII code is to be stored MOV A, M - Transfer byte MOV B, A - Save byte RRC Shift high-order nibble to the position of low- RRC order nibble RRC RRC

Binary to ASCII Main Program – Cont. CALL ASCII - Call conversion routine STAX D - Store first ASCII Hex in XX60H INX D - point to next memory location, get ready to store next byte MOV A, B - Get number again for second digit CALL ASCII STAX D HLT

Binary to ASCII Subroutine – ASCII ASCII ; Converts a binary digit between 0 and F to ASCII Hex code ;Input: Single binary number 0 to F in the accumulator ;Output: ASCII Hex code in the accumulator :ANI 0FH - Mask high-order nibble CIP 0AH - Is digit less than 1010? JC CODE - If digit is less than 1010, go to CODE to add 30H ADI 07H - Add 7H to obtain code for digits from A to F CODE: ADI 30H - Add base number 30H RET - Return to Main Program

ASCII to Binary Write a subroutine to convert an ASCII Hex number into its binary equivalent. A calling program places the ASCII number in the accumulator, and the subroutine should pass the conversion back to the accumulator. Subroutine ASCBIN ;This subroutine converts an ASCII Hex number into its binary ;Input: ASCII Hex number in the accumulator ;Output: Binary equivalent in the accumulator :SUI 30H - Subtract 0 bias from the number CPI 0AH - Check whether number is between 0 and 9 RC - If yes, return to main program SUI 07H - If not, sub. 7 to find number between A & F RET - Return to Main Program

BCD Multiplication A multiplicand is stored in memory location XX50H and a multiplier is stored in location XX51H. Write a main program to transfer the two numbers from memory locations to the HL registers and store the product in the Output Buffer at XX90H. Write a subroutine to Multiply two unsigned numbers placed in registers H and L and Return the result into the HL pair. Main Program LXI SP, STACK LHLD XX50H - Place contents of XX50 in L register and contents of XX51 in H register XCHG - Place multiplier in D and multiplicand in E CALL MLTPLY - Multiply the two numbers SHLD XX90H - Store the product in locations XX90 and 91H HLT - End of the Program

BCD Multiplication Subroutine - MLTPLY MLTPLY:MOV A, D - Transfer multiplier to accumulator MVI D, 00H - Clear D to use in DAD instruction LXI H, 0000H - Clear HL MVI B, 08H - Set up register B to count eight rotations NXTBIT:RAR - Check if multiplier bit is 1 JNC NOADD - If not, skip adding multiplicand DAD D - If multiplier is 1, add multiplicand to HL and place partial result in HL NOADD:XCHG - Place multiplicand in HL DAD H - And shift left XCHG - Retrieve shifted multiplication DCR B - One operation is complete, decrement counter JNZ NXTBIT - Go back to next bit RET - Return To Main Program

Interfacing Peripherals Primary Function of MPU is to accept and send data from I/P & to O/P Devices These I/O & O/P Devices are called peripherals or I/Os Interfacing is to enable the MPU to communicate with the peripherals.

Classification of Interfacing Communication Synchronous – Both transmitter & Receiver aer synchronized by same clock pulse Asynchronous – Both of Irregular Intervals Transfer of Data Parallel – Entire word is transmitted at a time Serial – One bit at a time over single line I/O Types Peripheral I/O – Identified with 8 bit address Memory mapped I/O – Identified with 16 bit address

Interrupt A computer input that temporarily suspends the normal sequence of operations and transfer control to a special routine. Interrupt Process is controlled by Interrupt Enable flip-flop, which can be set or reset by using software Instruction. INTR (pin 10) goes high the Microprocessor is interrupted, which is maskable & can be disabled Microprocessor also has additional vectored interrupt signals.

Vectored Interrupt Maskable RST 7.5 - 003CH RST 6.5 - 0034H RST 5.5 - 002CH Non-maskable TRAP - 0024H

Interrupt Instruction RST Instruction Description Bytes Operand OP Code The Interrupt Enable flip-flop is reset and all the interrupts except TRAP are disabled 1 None DI The Interrupt Enable flip-flop is set and all the interrupts are enabled 1 None EI 0038H FF RST 7 0030H F7 RST 6 0028H EF RST 5 0020H E7 RST 4 0018H DF RST 3 0010H D7 RST 2 0008H CF RST 1 0000H C7 RST 0 Call Location Hex Code Mnemonics

Real Time Example to Interrupt Interrupt Process is to compare it to a telephone line with a blinking light instead of ring when you are reading a book. If the line INTR is high and the interrupt is enabled, the microprocessor completes the current instruction, disables the Interrupt Enable flip-flop and sends a signal called INTA – Interrupt Acknowledge (active low). The processor cannot accept any interrupt requests until the interrupt flip-flop is enabled again. If you see a blinking light, you should pick up the receiver, say hello, and wait for a response. Once you pick up the phone, the line is busy, and no more calls can be received until you replace the receiver. Step 3: When the microprocessor is executing a program, it checks the INTR line during the execution of each instruction. Have glance at the light at certain intervals to check whether someone is calling Step 2: The interrupt process should be enabled by writing the instruction EI The Telephone System should be enabled Step 1:

Assuming that the task to be performed is written as a subroutine at the specified location, the processor performs the task. This subroutine is known as a service routine You replace the receiver on the hook Step 6: It saves the memory address of the next instruction on the stack and the program is transferred to the CALL location. You insert a bookmark on the page you are reading Step 5: The signal INTA is used to insert an instruction, preferably, a restart (RST) instruction, through additional hardware. The RST instruction is a 1-byte call instruction that transfers the program control to a specific memory location on page 00H and restarts the execution at that memory location after executing Next Step Assuming that the caller is you roommate, the request may be: It is going to rain today. Will you please shut all the windows in my room? Step 4:

To implement Step 4 in the interrupt process, insert one of RST instructions in the microprocessor by using external hardware and the signal INTA (Interrupt Acknowledge) At the end of the subroutine, the RET instruction retrieves the memory address where the program was interrupted and continues the execution. You go back your book, find your mark, and start reading again Step 8: The service routine should include the instruction EI to enable the interrupt again. This is similar to putting the receiver back on the hook You shut your roommate’s windows Step 7:

8085 Interrupt & Vector Locations

Instruction to Read & Write Interrupts SIM Data Bytes Serial Output data Serial Data Enable 1 = Enable 0 = Disable Don’t Care Reset RST 7.5 If D 4 = 1 Mask Set Enable D 3 = 1 Mask Interrupts If bits = 1 Description Bytes Operand OP Code Multipurpose Instruction and used to read the 8085 interrupts and Serial Data Input 1 None RIM Multipurpose Instruction and used to implement the 8085 interrupts and Serial Data Output 1 None SIM M5.5 M6.5 M7.5 MSE R7.5 XXX SDE SOD D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

RIM Data Bytes Serial Input Data Pending Interrupts 1 = Pending Interrupt Enable 1 = Enable Interrupt Masks 1 = Masked Instruction Set to enable all the interrupts of 8085 EI ;Enable Interrupts MVI A, 08H ;Load bit pattern to enable RST 7.5, 6.5 and 5.5 SIM ;Enable RST 7.5, 6.5 and 5.5 5.5 6.5 7.5 IE I 5 I 6 I 7 SID D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

Assuming the microprocessor is completing an RST 7.5 interrupt request, check to see if RST 6.5 is pending. If it is pending, enable RST 6.5 without affecting any other interrupts; otherwise, return to the main program. RIM ;Read interrupt mask. MOV B,A ;Save mask information ANI 20H ;Check whether RST 6.5 is pending JNZ NEXT EI RET ;RST 6.5 is not pending, return to main program. NEXT: MOV A, B ;Get bit patter, RST 6.5 is pending. ANI 0DH ;Enables RST 6.5 by setting D1 = 0. ORI 08H ;Enable SIM by setting D3 = 1 SIM JMP SERV ;Jump to service routine for RST 6.5

Serial I/O I/O requirements I/O Mapped & Memory Mapped Transmission Synchronous Vs. Asynchronous Simplex & Duplex (Half or Full) Parity Check (Odd or Even) with bit D 7 = 1: Even BAUD No. of Signals / Second Modem FSK (Send bits according to frequency)

8155/8156 Programmable I/O & Timer Features 40 Pins 256 Bytes of R/W Memory 3 Programmable I/O Ports Two 8-bit parallel I/O ports (A and B) One 6-bit port (C) Programmable 14 bit binary counter / Timer Multiplexed Address & Data Buses

Pin Configuration PC 3 PC 4 TIMER IN RESET PC 5 TIMER OUT IO/M CE RD WR ALE AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 V ss V cc PC 1 PC 2 PC 0 PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 8155 / 8156 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Block Diagram 8155 256 X 8 Static RAM A B C Timer 8 8 6 Port A Port B Port C PA 0-7 PB 0-7 PC 0-5 AD 0-7 IO/M CE ALE RD WR RESET Timer CLK TIMER OUT Vcc (+5V) Vss (0V)

Expanded Block Diagram AD 7 AD 0 Port A Port B Port C Timer LSB Timer MSB Data Bus Control Register 5 4 Internal 3 Decoder 2 1 0 Internal Latch A 1 A 2 A 3 Timer MSB Timer MSB Port C Port B Port A Control Register A 7 CE

Port Address A 15 – A 8 is duplicated by A 7 – A 0 A 15 & A 14 are Active Low Enable A 13 , A 12 & A 11 are give as input to 8205 decoder O 4 is give to the chip enable of 8155 Timer MSB 1 0 1 Timer LSB 0 0 1 Port C 1 1 0 Port B 0 1 0 Port A 1 0 0 Control Register 0 0 0 Control A 0 A 1 A 2

To enable o4 of 8205 A 13 =1, A 12 =0, A 11 =0 The Following table give the address of Ports of 8155 25H 24H 23H 22H 21 H 20 H HEX Code 1 1 1 1 1 1 A 13 0 0 0 0 0 0 A 12 0 0 0 0 0 0 A 11 Timer MSB 1 0 1 Timer LSB 0 0 1 Port C 1 1 0 Port B 0 1 0 Port A 1 0 0 Control Register 0 0 0 Control A 0 A 1 A 2

Control Register 00 NOP 01 STOP/NOP 10 STOP after TC 11 START IE A IE B 1 – Enable 0 – Disable Port A Port B 0 – Input ; 1 - Output D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 INTR A BF A STB A INTR B BF B STB B 0 1 INTR A BF A STB A O O O 1 0 O O O O O O 1 1 I I I I I I 0 0 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 D 2 D 3

Interfacing 7 segment LED Display Design 2 7-segment LED displays using Ports A & B of 8155 to display the data bytes. Solution HP 5082/7340 are inbuilt decoders- is attached to Port A 9370 decoder & 7-segment LEDs is attached with Port B The Data Byte separated into nibbles and displayed

Control Word Program MVI A, 03H ; Initialize ports A and B as output ports. OUT 20H MVI A, BYTE1 OUT 21H ; Display BYTE1 at port A. MVI A, BYTE2 OUT 22H ; Display BYTE2 at port B. HLT = 03H No Effect on Timer Not Applicable Port C Is not Being used Port B As O/P Port A As O/P 1 1 0 0 0 0 0 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

Timer in 8155 Two 8bit Registers 14 bits are used for counters 2 bits for Timer Mode Timer can be stopped At midst of Terminal Count At end of Terminal Count

Timer T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12 T 13 M 1 M 2 Continuous Pulse upon every TC 1 1 Single Pulse upon TC 0 1 Continuous Square Wave 1 0 One Square Wave 0 0 Description M 1 M 2

Example for using Timer The System Clock is connected to Timer IN of 8155. The clock has 3MHz Frequency. Write a program to produce continuous square wave with a frequency of 1KHz. Includes a start timer command, disable the port interrupts, make Port B&C as O/P ports and make Port A as I/P port. LSB Timer MSB Timer Control Word Timer 3000 10 = 0BB8H Timer M 2 , M 1 = 0,1 (Continuous Square Wave) Control Word D0, D1, D2 & D3 = 0,1,1&1 respectively (Port A is I/P & Port B&C are O/P D6, D7 = 1, 1 (Start the Timer) 0 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 1 1

Program MVI A, B8H - Setting LSB of Timer OUT 24H - Loading LSB Timer MVI A, 4BH - Setting MSB Timer OUT 25H - Loading MSB Timer MVI A, CEH - Setting Control Word OUT 20H - Loading Control Word

8355 / 8755 2K memory of EPROM 2 8-bit I/O Ports Data Direction Register

Pin Configuration CE 1 CE 2 CLK RESET N.C. READY IO/M IOR RD IOW ALE AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 V ss V cc PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 A 10 A 9 A 8 8355 / 8755 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Block Diagram 8355/8755 2K X 8 EPROM A B 8 8 Port A Port B PA 0-7 PB 0-7 AD 0-7 READY CE 2 ALE RD IOW RESET Prog/CE 1 V DD V CC V SS CLK IOR IO/M A 8-10

Address Bits DDR B 1 1 X 0 0 0 0 0 DDR A 0 1 X 0 0 0 0 0 Port B 1 0 X 0 0 0 0 0 0 AD 0 Port A Selected Register 0 X 0 0 0 0 0 AD 1 AD 2 A 11 /AD 3 A 12 /AD 4 A 13 /AD 5 A 14 /AD 6 A 15 /AD 7

Example Write initialization instructions to configure port A and port B as output ports, and display 32H at port A Program: MVI A, FFH ; Control word to set up all bits as output bits OUT 02H ; Initialize port A as output OUT 03H ; Initialize port B as output MVI A, 32H OUT 00H ; Display 32H at port A HLT

8279 Programmable Keyboard / Display Interface Simultaneous Keyboard Display Operation 8 character keyboard FIFO 2-key lockout or N-Key Roll over Dual 8 or 16 numerical Display Single 16 character display Right or Left Entry 16 Byte display RAM

Major Segments Keyboard Connected to 64 contact key matrix Entries are stored in FIFO Interrupt sent for every entry Display Has 16 characters scanned display 16 character memory

Pin Configuration RL 2 RL 3 CLK IRQ RL4 RL5 RL6 RL7 RESET RD WR DB 0 DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 V ss V cc RL 1 RL 2 CTRL/STB SHIFT SL 3 SL 2 SL 1 SL 0 OUT B 0 OUT B 1 OUT B 2 OUT B 3 OUT A 0 OUT A 1 OUT A 2 OUT A 3 BD CS A 0 8279 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Logical Symbol IRQ RL 0-7 Data Bus SHIFT RD CNTL/STB WR CS SL 0-3 A 0 OUT A 0-3 RESET OUT B 0-3 CLK BD 8 8 4 4 4 V cc V ss Scan Display Data Key Data CPU Interface

Pin Names Interrupt Request Output O IRQ Buffer Address I A0 Write Input I WR Read Input I RD Chip Select I CS Reset Input I RESET Clock Input I CLK Data Bus (Bi Directional) I/O DB 0-7 Blank Display Output O BD Display (B) Outputs O OUT B 0-3 Display (A) Outputs O OUT A 0-3 Control Strobe Input I CNTL/STB Shift Input I SHIFT Return Lines I RL 0-3 Scan Lines O SL 0-3

Different Sections Keyboard Section Scan Section Display Section MPU Interface Section

Programming 8279 left or right entry and key rollover. clock frequency prescaler. starting address and incrementing mode of the FIFO RAM. RAM address to read and write data and incrementing mode. blanking format.

Circuit The 8279 Programmable Keyboard / Display Interface A Matrix keyboard with 22 keys Six seven-segment LEDs: DS1-DS6 74LS156 decoder with open collector outputs. Transistors as current Drivers 8205 decoder for the decoding logic

Port Address Keyboard/Display Mode MVI A, 00H Control word to set mode: Left 0 0 0 D D K K K entry, 8-character, 2-key lockout encoded scan keyboard STA 1900H Initialize 8279

PUSH H PUSH PSW Read FIFO RAM: Control Word LXI H, 1900H Keyboard control 0 1 0 A1 X A A A register address MVI M, 40H Control word to read from keyboard DCR H Data Port Address 1800H MOV A, M Read data Data Format D7 D6 D5 D4 D3 D2 D1 D0 ANI 3FH Mask D7 and D6. CNTL SHFT ROW COL CNTL, Shift keys are not being used STA IBUFF Store in R/W memory POP PSW POP H RET

8254 Programmable Interval Timer 40 Pin 3 independent Counters 5 Modes of Operations

Modes of Operations Mode 0 Interrupt on Terminal Count Count Begins one clock pulse after the count has been written in to counter GATE 0 = 1, then counter 0 counts down CLK 0 pulse then the counter decrements by 1 GATE 0 = 0. then counts inhibited The operation is same for all the 3 counters

Program MVI A, CWR1 ;Get 8255A #1command word OUT CR1 MVI A, CWR2 ;Get 8255A #2 command word OUT CR2 MVI A, BLMSET ;Get byte to blank the LIMIT SET lamp. OUT PORTC2 ;Send to port C of 8255 #2 CALL RALARM ;Reset alarms. CALL STCNTR0 ;Start counter 0. EI ;Enable interrupts RET ;End of subroutine.

Temperature Monitoring System General Controls µprocessor based system is designed to control the temperature of a water bath, by controlling a heater ON or OFF Accuracy of  1º C Temperatures can be set by switches 7 segment Display is used to display the temperature This involves both hardware & software design

Hardware Design A transducer is used to convert temperature into an equivalent analog electrical quantity The analog signal is converted in digital by A/D Converters A relay is used to switch heater ON & OFF Two digit 7-segment display is used to display the temperature All these hardware are interface to MPU through I/O ports EPROM is used to store the Software

Block Diagram of Hardware Design Address, Data & Control Busses MPU EPROM 8 Bit I/O Port Relay Driver & Relay 8 bit I/O Port 8 Bit I/O Port Temp. Transducer & Buffer A/D Converter 7-segment Displays Switches SOD SID

Memory No RAM is necessary EPROM 2716 is used to used (2KB of Memory) I/O Port System requires 26 I/O lines (17 O/P & 9 I/P) 8255 (24 Ports) with SID & SOD A/D Converter ADC chips are quite costlier when compared to DAC. As fast conversion is not necessary ADC can be implemented by using an external DAC and a comparator with MPU as Controller

LED Display 2 7-segment display is used Switches One Thumb wheel Switch is used(4 toggle switches) Transducer & Buffer A thermistor with 5K  is used at 25 ºC Relay & relay driver Temperature of Bath is controlled by immersion heater ON or OFF Immersion heater is ON or OFF by a relay This controlled by SID & SOD of MPU

Software Design (Algorithm) Initialize I/O port of 8255. ADC is performed by successive approximation Getting Temperature for Bath. Display measured temperature in LED Display Read the desired temperature from Switches Comparing measured temp. with desired temp. & making SOD low or high Generate a delay of 2 Second

Flowchart Start Initialize I/O ports A/D Converter Get Desired Temp. Display measured Temp Read Desired Temp. Make Relay OFF .5 Sec Delay Make Relay ON Is MT = DT Yes NO

Program Get temp. from Table MOV A, M MVI H, 02H Table starts from 0200H MOV L, C NEXT: JMP REP Send next Digital Value INR C COUNTD: Check for Equality JMP NEXT JNC COUNTD Check for non-Equality RAL Get Comparator O/P RIM JNZ LOOP DCR D Wait for DAC MVI D, 08H Send to DAC OUT 00H MOV A, C REP: AGAIN: Initial Data Value MVI C,00H OUT 03H Initialize Port A & B as O/P, C as I/P MVI A, 89H

Program Switching OFF relay Else ON relay MVI A, 40H ON: SIM JMP DELAY Goto AGAIN to repeat the steps JMP AGAIN JNZ L2 DCR D JNZ L1 DCR E L1: MVI E, 00H L2: Time Delay MVI D, 00H DELAY: SIM MVI A, C0H OFF: JZ OFF If Temp. is High or Equal OFF relay JC OFF Compare Temp. in Mem. & Acc. CMP M Get switch setting IN 02H Display it OUT 01H

Computer archi&mp

More Related Content

What's hot

Viewers also liked

Similar to Computer archi&mp

Recently uploaded

Computer archi&mp