This document provides an overview of computer architecture and microprocessor concepts including: 1. It discusses different number systems such as binary, decimal, hexadecimal and their conversions. It also covers logic gates, Boolean algebra and other digital logic concepts. 2. It introduces microprocessors and their general architecture. It discusses microprocessor operations such as memory reads/writes and I/O reads/writes. 3. It covers computer languages from machine language to assembly and high-level languages. It also discusses compilers and interpreters.

1. Computer Architecture and Microprocessor

8. Number System Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hexa Decimal Number System Octal Number System Binary Number System Decimal Number System

22. ASCII Codes Character ASCII Code DLE 10 S0 0F S1 0E CR 0D FF 0C VT 0B LF 0A HT 09 BS 08 BEL 07 ACK 06 ENQ 05 EOT 04 ETX 03 STX 02 SOH 01 NUL 00 Character ASCII Code ! 21 SP 20 US 1F RS 1E GS 1D FS 1C ESC 1B SUB 1A EM 19 CAN 18 ETB 17 SYN 16 NAK 15 DC4 14 DC3 (X-off) 13 DC2 (Tape) 12 DC1 (X-on) 11

23. ASCII Code 1 31 0 30 / 2F . 2E - 2D , 2C + 2B * 2A ) 29 ( 28 ‘ 27 & 26 % 25 $ 24 # 23 “ 22 Character ASCII Code A 41 @ 40 ? 3F > 3E = 3D < 3C ; 3B : 3A 9 39 8 38 7 37 6 36 5 35 4 34 3 33 2 32 Character ASCII Code

24. U 55 T 54 S 53 R 52 Q 51 P 50 O 4F N 4E M 4D L 4C K 4B J 4A I 49 H 48 G 47 F 46 E 45 D 44 C 43 B 42 Character ASCII Code j 6B i 6A Characters ASCII h 69 g 67 f 66 e 65 d 64 c 63 b 62 a 61 - ( ) 5F ^ ( ) 5E ] 5D 5C [ 5B Z 5A Y 59 X 58 W 57 V 56

25. DEL 7F ~ 7E } 7D | 7C { 7B z 7A y 79 x 78 w 77 v 76 u 75 t 74 s 73 r 72 q 71 p 70 o 6F n 6E m 6D l 6C k 6B Character ASCII Code

39. Full Adder – Truth Table a n b n c n s n c n+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

40. 7 Segment LED Display

42. 7 Segment LED Display – Truth Table 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 INPUTS X Y Z W A B C D E F G OUTPUT L E G A L D I G I T S 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 E R R O R

72. 8085 PINOUT X 1 X 2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 V SS V cc HOLD HLDA CLK(OUT) RESET IN READY IO/M S1 RD WR ALE S0 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

73. +5V GND Serial I/O Ports Interrupts & Externally Initiated Signals External Signal Acknowledgement Control And Status Signals 8085 Signals RESET CLK OUT OUT X1 X2 Vcc Vss ALE S0 S1 IO/M RD WR SID SOD TRAP RST 7.5 RST 6.5 RST 5.5 INTR READY HOLD RESET IN INTA HLDA High-Order Address Bus Multiplexed Address/Data Bus A 15 A 8 AD 7 AD 0

76. IO/M RD 8085 WR A 15 A 8 ALE AD 7 AD 0 EN LATCH A 15 A 8 A 7 A 0 D 7 D 0 Data Bus MEMR MEMW IOR IOW Control Signals

82. Address Buffer Temp Reg. (8) Arithmetic Logic Unit (ALU) (8) Flag (5) Flip-flops Data Address Buffer (8) Multiplexer Timing and Control CLK Reset GEN Control Status DMA Reg. Select Serial I/O Control SID Interrupt Control TRAP RST 7.5 RST 6.5 RST 5.5 INTA INTR SOD Ready RD WR ALE S 0 S 1 IO/M HLDA RESET OUT RESET IN HOLD A 15 – A 8 Address Bus AD 7 – AD 0 Address/Data Bus X1 x2 Register Array Accumulator (8) Instruction Decoder and Machine Cycle Encoding Instruction Register (8) W Temp. Reg. Z Temp. Reg. B Reg. D Reg. H Reg. Stack Program Counter C Reg. E Reg. L Reg. Address Latch (16)

83. Registers Has the Memory Pointer Address SP (Stack Pointer) 16 Bits Has the Program Pointer Address PC (Program Counter) 16 Bits H & L combined to form 16 Bits L 8 Bits H 8 Bits D & E combined to form 16 Bits E 8 Bits D 8 Bits B & C combined to form 16 Bits C 8 Bits B 8 Bits Arithmetic Operations Logical Operations A (Accumulator) 8 Bits

84. Flags D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 CY P AC Z S Set – Carry Exists Reset – No Carry exists Carry CY Set – Even Reset – Odd Parity P Set – Carry From D3 to D4 Reset – No Carry From D3 to D4 Auxiliary Carry AC Set – Zero Reset – Non-Zero Zero Z Set – Positive Reset – Negative Sign S

86. T1 T2 T3 CLK A 15 – A 8 AD 7 –AD 0 ALE IO/M RD Low -Order Memory Address Memory Contents M High –Order Memory Address

87. ALU Instruction Decoder Control Logic Address Bus Data Bus Memory B D H Stack Program Counter C E L

95. Between Registers Between Registers and Memory 1 Bytes Copies data From Source Register Rs to Destination Register Rd Rd, Rs MOV Description Operand OP Code Description Bytes Operand OP Code Copies data From memory M to Destination Register Rd 1 Rd, M MOV Copies data From Source Register Rs to Memory M 1 M, Rs MOV

96. Data to/from Register, Memory or I/O Port Copies the content of the Register L to memory location pointed out by 16 bit address and content of Register H to next memory location 3 16 Bit Address SHLD Copies the content of the memory location pointed out by 16 bit address to Register L and content of next memory location to Register H 3 16 Bit Address LHLD Loads the Data to the Specified Register 2 R, Data (8 Bits) MVI Copies data From Accumulator A to Specified port Address 2 8 Bit Port Address OUT 2 Bytes Copies data From Specified port Address to Accumulator A 8 Bit Port Address IN Description Operand OP Code

97. Data to/from Register, Memory or I/O Port Contents of Register H is exchanged with Register D and Contents of Register L is exchanged with Register E 1 None XCHG Loads the 16 bit data into the Register Pair 3 RP, 16 Bit Data LXI Copies the content of Memory Location Accumulator A to Specified in Register Pair B or D 1 RP B/D STAX Copies the content of Accumulator A to Memory location specified by 16 bit address 3 16 Bit Address STA Copies the content of Memory Location Specified in Register Pair B or D to Accumulator A 1 RP B/D LDAX 3 Bytes Copies the content of Memory location specified by 16 bit address to Accumulator A 16 Bit Address LDA Description Operand OP Code

101. Arithmetic Operations The content of the specified Register or Memory is decremented by 1 1 R/M DCR The content of the specified Register or Memory is incremented by 1 1 R/M INR 8 Bit Data is subtracted from the content of Accumulator and the result is stored in Accumulator 2 8 Bit Data SUI 8 Bit Data is added to the Accumulator content and stores the result in Accumulator 2 8 Bit Data ADI Content of the Register or Memory is subtracted from the content of Accumulator and the result is stored in Accumulator 1 R/M SUB 1 Bytes Content of the Register or Memory is added to the content of Accumulator and the result is stored in Accumulator R/M ADD Description Operand OP Code

116. Programming Format End of the Program None HLT Sends 37H to Port ‘ Port1 ’ Port1 OUT Copies Content of Register B to Accumulator A, B MOV Loads 37H to Register B B, 37H MVI Description Operand OP Code

117. Arithmetic Operations The content of the specified Register or Memory is decremented by 1 1 R/M DCR The content of the specified Register or Memory is incremented by 1 1 R/M INR 8 Bit Data is subtracted from the content of Accumulator and the result is stored in Accumulator 2 8 Bit Data SUI 8 Bit Data is added to the content of Accumulator and the result is stored in Accumulator 2 8 Bit Data ADI Content of the Register or Memory is subtracted from the content of Accumulator and the result is stored in Accumulator 1 R/M SUB 1 Bytes Content of the Register or Memory is added to the content of Accumulator and the result is stored in Accumulator R/M ADD Description Operand OP Code

121. CA & µP Unit IV

123. Flowchart Start Initialize Update Is the Final Count End No Yes

124. Time Delay

138. Flowchart Start Initialize Loop2 Update Is the Final Count End Initialize Loop1 Update Is the Final Count No No Yes Yes

151. Register Contents after executing first 2 Instructions A B D H SP Register Contents after executing PUSH Instructions X X 2000 53 42 A B D 1FFE H 1FFF SP 2000 X X 2000 53 42 X 42 53 Memory

152. Register Contents after executing POP Instructions A Flags B C D E H L SP 53 42 2000 53 42 X 42 53 Memory

157. Example End of Subroutine RET 3002H Instructions of Subroutine Inst. 3001H Instructions of Subroutine Inst. 3000H End of Main Program HLT 2008H Other Instructions Inst. 2007H Calling the subroutine at 3000H CALL 3000H 2004H Initialize the stack pointer with 2400H LXI SP, 4000H 2000H Description Instruction Mem. Add.

159. Data Transfer During CALL Instruction 30 2006H 00 2005H CD 2004H Code (H) Mem. Add.

160. PC, Stack & SP during CALL Inst. CALL Program Counter Stack Pointer Register 3FFE 3FFF 4000 STACK 2007 2006 2005 2004 XX 20 07 3FFE 3FFF 4000

161. Data Transfer During CALL Instruction 20 07 (W) (Z) 2007 (W) (Z) M 1 Opcode Fetch 20 20 (Stack – I) 3FFF 4000 M 3 Opcode Fetch 07 07 (Stack) 3FFE 3FFF M 2 Opcode Fetch - C9 Opcode 3003 3002 3FFE M 1 Opcode Fetch Internal Registers (W) (Z) Data Bus (DB) Program Counter Address Bus (AB) Stack Pointer 3FFE Machine Cycles

163. The problem is primarily concerned with providing various time delays for a complete sequence of 40 seconds. The on/off times for the traffic signals and pedestrian signs are as follows:

189. Interrupt Instruction RST Instruction Description Bytes Operand OP Code The Interrupt Enable flip-flop is reset and all the interrupts except TRAP are disabled 1 None DI The Interrupt Enable flip-flop is set and all the interrupts are enabled 1 None EI 0038H FF RST 7 0030H F7 RST 6 0028H EF RST 5 0020H E7 RST 4 0018H DF RST 3 0010H D7 RST 2 0008H CF RST 1 0000H C7 RST 0 Call Location Hex Code Mnemonics

191. Assuming that the task to be performed is written as a subroutine at the specified location, the processor performs the task. This subroutine is known as a service routine You replace the receiver on the hook Step 6: It saves the memory address of the next instruction on the stack and the program is transferred to the CALL location. You insert a bookmark on the page you are reading Step 5: The signal INTA is used to insert an instruction, preferably, a restart (RST) instruction, through additional hardware. The RST instruction is a 1-byte call instruction that transfers the program control to a specific memory location on page 00H and restarts the execution at that memory location after executing Next Step Assuming that the caller is you roommate, the request may be: It is going to rain today. Will you please shut all the windows in my room? Step 4:

192. To implement Step 4 in the interrupt process, insert one of RST instructions in the microprocessor by using external hardware and the signal INTA (Interrupt Acknowledge) At the end of the subroutine, the RET instruction retrieves the memory address where the program was interrupted and continues the execution. You go back your book, find your mark, and start reading again Step 8: The service routine should include the instruction EI to enable the interrupt again. This is similar to putting the receiver back on the hook You shut your roommate’s windows Step 7:

193. Buffer to enable RST 5

194. 8085 Interrupt & Vector Locations

195. Instruction to Read & Write Interrupts SIM Data Bytes Serial Output data Serial Data Enable 1 = Enable 0 = Disable Don’t Care Reset RST 7.5 If D 4 = 1 Mask Set Enable D 3 = 1 Mask Interrupts If bits = 1 Description Bytes Operand OP Code Multipurpose Instruction and used to read the 8085 interrupts and Serial Data Input 1 None RIM Multipurpose Instruction and used to implement the 8085 interrupts and Serial Data Output 1 None SIM M5.5 M6.5 M7.5 MSE R7.5 XXX SDE SOD D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

196. RIM Data Bytes Serial Input Data Pending Interrupts 1 = Pending Interrupt Enable 1 = Enable Interrupt Masks 1 = Masked Instruction Set to enable all the interrupts of 8085 EI ;Enable Interrupts MVI A, 08H ;Load bit pattern to enable RST 7.5, 6.5 and 5.5 SIM ;Enable RST 7.5, 6.5 and 5.5 5.5 6.5 7.5 IE I 5 I 6 I 7 SID D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

200. Pin Configuration PC 3 PC 4 TIMER IN RESET PC 5 TIMER OUT IO/M CE RD WR ALE AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 V ss V cc PC 1 PC 2 PC 0 PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 8155 / 8156 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

201. Block Diagram 8155 256 X 8 Static RAM A B C Timer 8 8 6 Port A Port B Port C PA 0-7 PB 0-7 PC 0-5 AD 0-7 IO/M CE ALE RD WR RESET Timer CLK TIMER OUT Vcc (+5V) Vss (0V)

202. Expanded Block Diagram AD 7 AD 0 Port A Port B Port C Timer LSB Timer MSB Data Bus Control Register 5 4 Internal 3 Decoder 2 1 0 Internal Latch A 1 A 2 A 3 Timer MSB Timer MSB Port C Port B Port A Control Register A 7 CE

206. Control Register 00 NOP 01 STOP/NOP 10 STOP after TC 11 START IE A IE B 1 – Enable 0 – Disable Port A Port B 0 – Input ; 1 - Output D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 INTR A BF A STB A INTR B BF B STB B 0 1 INTR A BF A STB A O O O 1 0 O O O O O O 1 1 I I I I I I 0 0 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 D 2 D 3

211. Timer T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T 12 T 13 M 1 M 2 Continuous Pulse upon every TC 1 1 Single Pulse upon TC 0 1 Continuous Square Wave 1 0 One Square Wave 0 0 Description M 1 M 2

215. Pin Configuration CE 1 CE 2 CLK RESET N.C. READY IO/M IOR RD IOW ALE AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 V ss V cc PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 A 10 A 9 A 8 8355 / 8755 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

216. Block Diagram 8355/8755 2K X 8 EPROM A B 8 8 Port A Port B PA 0-7 PB 0-7 AD 0-7 READY CE 2 ALE RD IOW RESET Prog/CE 1 V DD V CC V SS CLK IOR IO/M A 8-10

218. Address Bits DDR B 1 1 X 0 0 0 0 0 DDR A 0 1 X 0 0 0 0 0 Port B 1 0 X 0 0 0 0 0 0 AD 0 Port A Selected Register 0 X 0 0 0 0 0 AD 1 AD 2 A 11 /AD 3 A 12 /AD 4 A 13 /AD 5 A 14 /AD 6 A 15 /AD 7

219. Interfacing 8755 I/O Ports

223. Pin Configuration RL 2 RL 3 CLK IRQ RL4 RL5 RL6 RL7 RESET RD WR DB 0 DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 V ss V cc RL 1 RL 2 CTRL/STB SHIFT SL 3 SL 2 SL 1 SL 0 OUT B 0 OUT B 1 OUT B 2 OUT B 3 OUT A 0 OUT A 1 OUT A 2 OUT A 3 BD CS A 0 8279 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

224. Logical Symbol IRQ RL 0-7 Data Bus SHIFT RD CNTL/STB WR CS SL 0-3 A 0 OUT A 0-3 RESET OUT B 0-3 CLK BD 8 8 4 4 4 V cc V ss Scan Display Data Key Data CPU Interface

225. Pin Names Interrupt Request Output O IRQ Buffer Address I A0 Write Input I WR Read Input I RD Chip Select I CS Reset Input I RESET Clock Input I CLK Data Bus (Bi Directional) I/O DB 0-7 Blank Display Output O BD Display (B) Outputs O OUT B 0-3 Display (A) Outputs O OUT A 0-3 Control Strobe Input I CNTL/STB Shift Input I SHIFT Return Lines I RL 0-3 Scan Lines O SL 0-3

226. Logic Block Diagram

234. Signals of 8254

236. Read/Write Operations

237. Control Word

238. Memory, Port & Timer Address

239. Control Word for 8255A#1

240. Control Word for 8255A#2

241. Control Word for 8254

245. Block Diagram of Hardware Design Address, Data & Control Busses MPU EPROM 8 Bit I/O Port Relay Driver & Relay 8 bit I/O Port 8 Bit I/O Port Temp. Transducer & Buffer A/D Converter 7-segment Displays Switches SOD SID

246. Detailed Block Diagram

251. Flowchart Start Initialize I/O ports A/D Converter Get Desired Temp. Display measured Temp Read Desired Temp. Make Relay OFF .5 Sec Delay Make Relay ON Is MT = DT Yes NO

252. Program Get temp. from Table MOV A, M MVI H, 02H Table starts from 0200H MOV L, C NEXT: JMP REP Send next Digital Value INR C COUNTD: Check for Equality JMP NEXT JNC COUNTD Check for non-Equality RAL Get Comparator O/P RIM JNZ LOOP DCR D Wait for DAC MVI D, 08H Send to DAC OUT 00H MOV A, C REP: AGAIN: Initial Data Value MVI C,00H OUT 03H Initialize Port A & B as O/P, C as I/P MVI A, 89H

253. Program Switching OFF relay Else ON relay MVI A, 40H ON: SIM JMP DELAY Goto AGAIN to repeat the steps JMP AGAIN JNZ L2 DCR D JNZ L1 DCR E L1: MVI E, 00H L2: Time Delay MVI D, 00H DELAY: SIM MVI A, C0H OFF: JZ OFF If Temp. is High or Equal OFF relay JC OFF Compare Temp. in Mem. & Acc. CMP M Get switch setting IN 02H Display it OUT 01H