Karthik Babu is a systems engineer with over 9 years of experience in areas like board design, validation, debugging issues, and factory support. He has extensive experience in the full product development cycle from component selection to testing. Some of his areas of expertise include automatic test equipment design, integration, and testing as well as cPCI and customized board design. He has successfully debugged and resolved complex design and process issues.
Verilog code for design a specific processor to down sample a given image via a math-lab by using SPARTAN-6 FPGA. Math-lab code, results also included.
Verilog code for design a specific processor to down sample a given image via a math-lab by using SPARTAN-6 FPGA. Math-lab code, results also included.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
Three-phase ac motors have been the workhorse of industry since the earliest days of electrical engineering. They are reliable, efficient, cost-effective and need little or no maintenance. In addition, ac motors such as induction and reluctance motors need no electrical connection to the rotor, so can easily be made flameproof for use in hazardous environments such as in mines.
In order to provide proper speed control of an ac motor, it is necessary to supply the motor with a three phase supply of which both the voltage and the frequency can be varied. Such a supply will create a variable speed rotating field in the stator that will allow the rotor to rotate at the required speed with low slip. This ac motor drive can efficiently provide full torque from zero speed to full speed, can overspeed if necessary, and can, by changing phase rotation, easily provide bi-directional operation of the motor. A drive with these characteristics is known as a PWM (Pulse Width Modulated) motor drive.
Drives and motors are an integral part of industrial equipment from packaging,robotics, computer numerical control (CNC), machine tools, industrial pumps,and fans. Designing next-generation drive systems to lower operating costs requires complex control algorithms at very low latencies as well as a flexibleplatform to support changing needs and the ability to design multiple-axis systems.
Traditional drive systems based on ASICs, digital signal processors (DSPs), and microcontroller units lack the performance and flexibility to address these needs. Altera’s family of FPGAs provides a scalable platform that can be used to offload control algorithm elements in hardware. You may also integrate the whole drive system with industry-proven processor architectures while supporting multipletypes of encoders and industrial Ethernet protocols. This “drive on a chip” system reduces cost and simplifies development.
Confabulation and segregation about different Virtex FPGA families of XILINX is presented. Starting with the features of latest Spartan-6 FPGA followed by Spartan-3A-DSP, 3AN, 3A, 3E and Spartan-3 are correlated, contrasted accordingly and the changes over these generations are also deliberated. For every family, Introduction and ordering information, Functional description, DC and switching characteristics and Pin out descriptions are mentioned and elucidated.
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
MIPI DevCon 2016: Effective Verification of Stacked and Layered ProtocolsMIPI Alliance
Pre-silicon verification of UniPro devices is challenging, demanding and may require significant effort. The layered structure of the specification and the rapid pace of new revisions and features require a flexible, modular and advanced test bench that is well beyond the ability of the traditional directed testing verification schemes that most designers employ. This presentation by Ofir Michaeli of Cadence Design Systems will discuss practical guidelines for defining a proper verification plan; how to design a verification test bench, a scoreboard and a reference model; the pros and cons of standalone verification vs. full stack verification; and a review of real-world verification environments used in actual verification of UFS/UniPro/M-PHY devices.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
Three-phase ac motors have been the workhorse of industry since the earliest days of electrical engineering. They are reliable, efficient, cost-effective and need little or no maintenance. In addition, ac motors such as induction and reluctance motors need no electrical connection to the rotor, so can easily be made flameproof for use in hazardous environments such as in mines.
In order to provide proper speed control of an ac motor, it is necessary to supply the motor with a three phase supply of which both the voltage and the frequency can be varied. Such a supply will create a variable speed rotating field in the stator that will allow the rotor to rotate at the required speed with low slip. This ac motor drive can efficiently provide full torque from zero speed to full speed, can overspeed if necessary, and can, by changing phase rotation, easily provide bi-directional operation of the motor. A drive with these characteristics is known as a PWM (Pulse Width Modulated) motor drive.
Drives and motors are an integral part of industrial equipment from packaging,robotics, computer numerical control (CNC), machine tools, industrial pumps,and fans. Designing next-generation drive systems to lower operating costs requires complex control algorithms at very low latencies as well as a flexibleplatform to support changing needs and the ability to design multiple-axis systems.
Traditional drive systems based on ASICs, digital signal processors (DSPs), and microcontroller units lack the performance and flexibility to address these needs. Altera’s family of FPGAs provides a scalable platform that can be used to offload control algorithm elements in hardware. You may also integrate the whole drive system with industry-proven processor architectures while supporting multipletypes of encoders and industrial Ethernet protocols. This “drive on a chip” system reduces cost and simplifies development.
Confabulation and segregation about different Virtex FPGA families of XILINX is presented. Starting with the features of latest Spartan-6 FPGA followed by Spartan-3A-DSP, 3AN, 3A, 3E and Spartan-3 are correlated, contrasted accordingly and the changes over these generations are also deliberated. For every family, Introduction and ordering information, Functional description, DC and switching characteristics and Pin out descriptions are mentioned and elucidated.
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
MIPI DevCon 2016: Effective Verification of Stacked and Layered ProtocolsMIPI Alliance
Pre-silicon verification of UniPro devices is challenging, demanding and may require significant effort. The layered structure of the specification and the rapid pace of new revisions and features require a flexible, modular and advanced test bench that is well beyond the ability of the traditional directed testing verification schemes that most designers employ. This presentation by Ofir Michaeli of Cadence Design Systems will discuss practical guidelines for defining a proper verification plan; how to design a verification test bench, a scoreboard and a reference model; the pros and cons of standalone verification vs. full stack verification; and a review of real-world verification environments used in actual verification of UFS/UniPro/M-PHY devices.
System Development for Verification of General Purpose Input OutputRSIS International
In SoC no. of IP block inside it depends upon specific
application, increase in the Ip block increases no. of digital
control lines causes increase in the size of the chip. GPIO helps
internal IP blocks to share digital control lines using MUX and
avoids additional circuitry. Since design productivity cannot
follow the pace of nanoelectronics technology innovation, it has
been required to develop various design methodologies to
overcome this gap. In system level design, various design
methodologies such as IP reuse, automation of platform
integration and verification process have been proposed. GPIO
configuration register decides in which mode system has to work
GPIO has four modes i.e input, output, functional, interrupt. As
per operation particular mode is selected and the operation get
performed. Devices with pin scarcity like integrated circuits such
as system-on-a-chip, embedded and custom hardware, and
programmable logic devices cannot compromise with size can
perform well without additional digital control line circuitry.
1. KARTHIK BABU J J
Chennai jjkarthikbabu@yahoo.co.in
+91-9003771928
OBJECTIVE
Challenging opportunities in areas of System & Board development, signal integrity,
Integration and Testing.
EXPERIENCE SUMMARY
9.5 years of systems engineering experience including board design, validation, debug issues &
factory support.
PROFESSIONAL SUMMARY
Experience in complete product cycle of Hardware design from component selection, Circuit
design, Schematic capture, Test procedure preparation, Testing and validation
Strong experience in Automatic Test Equipment design, Integration and Testing
Exposure in cPCI based and customized board design.
Proven track record of debugging and resolving complex design and process issues
Investigate design reuse feasibility for time to market and cost, cost optimization proposals
for existing designs
Driven, self-starter accustomed to prioritize multiple deliverables in order to meet project and
team milestones
Exposure to factory support activities during for mass production and familiar with Technical
proposals
EXPERIENCE SUMMARY
Senior Engineer, Indus Teqsite Private Limited from November 2008 to till date
Hardware Engineer, Ordyn Technologies –Bangalore, from April 2008 to October 2008
Hardware Engineer, Avitronics Systemtech Pvt. Ltd., Bangalore, from July 2005 to March
2008
TECHNICAL SKILLS
Domain : Board Design, ATE Design, Integration and Testing
Processor : 32 Bit PLX controller, Micro Controller
Interfaces : PCI, RS232/422/485, I2C, 1553B, ARINC429/717,
ETHERNET
Debugger : JTAG Debugger
Development tools : ORCAD for schematic capture, PADS for CAD files, Altera
MaxplusII & Xilinx Navigator for CPLD & FPGA Programming
Test Equipment : Signal Generator, Spectrum Analyzer, High Bandwidth
Oscilloscope
Karthikbabu Page 1
2. Devices Used : ADC, DAC, Frequency Synthesizer
EDUCATION
B.E in Electronics and Communication Engineering from K.L.N COLLEGE OF
ENGINEERING, Madurai with 74.29% in the year 2004
HSC Passed with 85.17% from Sourashtra higher secondary school, Madurai in the year
2000
SSLC Passed with 81.4% from Sourashtra higher secondary school, Madurai in the
year 1998
PROFESSIONAL EXPERIENCE
PROJECT 1:
System Name : ATE for Smart Cockpit Display System
Client : HAL, Bangalore
Organization : Indus Teqsite Private Limited
DESCRIPTION:
The system is a ground station equipment to test and validate the functionality of the
cockpit systems of Light Utility Helicopter. This test system tests and validates the Smart
Multi-Function Display unit and Data Interface Unit. This is a self-calibrated system which
simulates and acquires various types of signals like Analog, Digital, RS232, RS422, RS485,
ARINC429, ARINC717 & 1553B of the unit under test.
ROLES & RESPONSIBILITIES:
A. System configuration.
B. System design, Integration and Testing.
PROJECT 2:
System Name : ATE of Imaging RF Seeker
Client : DRDL, Hyderabad
Organization : Indus Teqsite Private Limited
DESCRIPTION:
The system is a ground station equipment to test and validate the functionality of the
Seeker sub systems namely RF and Digital, Gimbal and Transmitter which operates on X-Band.
System simulates and measures the input and output requirements to validate the units. System
is configured with a Signal Generator, Spectrum Analyzer and Power Meter. RF signals (9GHz)
are generated using signal generator and response signals from Seeker sub systems are
measured and validated by using Spectrum analyzer and Power meter using RF relays.
ROLES & RESPONSIBILITIES:
A. System configuration.
B. System design, Integration and Testing.
C. Project Management.
Karthikbabu Page 2
3. PROJECTS HANDLED
PROJECT 3:
System Name : Checkout Equipment for Missile
Client : Brahmos, Hyderabad
Organization : Indus Teqsite Private Limited
SYSTEM DESCRIPTION:
This system is ground station equipment which is used to test and validate the
functionality of the Missile which carries Onboard Electrical Equipment and Onboard Control
system. The checkout system simulates various signals to the missile and monitors critical
signals.
ROLES & RESPONSIBILITIES:
A. System configuration
B. System design, Integration and Testing.
PROJECT 4:
System Name : Onboard ATE
Client : IISU, Trivandrum
Organization : Indus Teqsite Private Limited
SYSTEM DESCRIPTION:
This system is a 16U height rugged mini rack which is going to be fixed on the rails of
low altitude beach aircrafts. It consists of 2 similar sets of modules called PRIME and
REDUNDANT unit. Each set contains a 4U – 6 Slot backplane cPCI chassis, 1U size display
unit and Compact System Interface Adapter modules with the common power distribution
panel. The system operates on 28V DC Power.
ROLES & RESPONSIBILITIES:
A. System configuration.
B. System design, Integration and Testing.
C. Project management.
PROJECT 5:
System Name : Digital CSA Checkout System
Client : IISU, Trivandrum
Organization : Indus Teqsite Private Limited
SYSTEM DESCRIPTION:
This system is a 36U height ground station equipment which was developed to simulate
and test the Ceramic servo accelerometer units. It consists of a 4U – 6 Slot backplane cPCI
chassis, 1U display unit and the instruments with GPIB interface.
ROLES & RESPONSIBILITIES:
A. System configuration.
B. System design, Integration and Testing.
C. Project management.
Karthikbabu Page 3
4. BOARDS HANDLED
BOARD 1:
Title : cPCI based Analog Output & Digital Input Output board
Client : HAL, Korwa, U.P
Device used : 32 bit PLX Controller (PCI 9054), DAC7744, PPI (82C55), FPGA &
EEPROM
Tools used : ORCAD, Pspice Simulator, Pads Power PCB
Organization : Avitronics Systemtech (India) Pvt. Ltd.,
BOARD DESCRIPTION:
Analog output board is a cPCI based board, which generates 24 channels of analog
signals with the resolution of μVolts by using 16bit Quad voltage output Digital to analog
converter. Each DAC can generate four channels of analog signals. All the control signals for
the DAC are given by the FPGA. Output voltage of each channel can be controlled by
programming the 16bit parallel input data.
Digital input and output board is a CPCI based one, which is used to generate all the
discrete signals required by the LRU’s of SSFDR. This board can generate 192 channels of TTL
signals by using PPI (82C55). 8 numbers of PPI’s are present in this board and each can
generate 24 channels of TTL signals. Each PPI has one 8bit programmable input port and three
8bit output port (24 programmable I/O pins). All the control signals for the PPI are generated by
the FPGA present in the same board.
ROLES & RESPONSIBILITIES:
A. Schematic design.
B. Involved in preparation of the hardware related documents like BOM, Net list,
Hardware requirement specification & Hardware Design Document.
Karthikbabu Page 4
5. BOARDS HANDLED
BOARD 2:
Title : Microcontroller interface card
Client : HAL, Korwa, U.P
Device used : Micro controller (89C58), Opto couplers (MCT2E) & OEN Relay
Tools used : ORCAD, Pspice Simulator & Pads Power PCB
Organization : Avitronics Systemtech (India) Pvt. Ltd.,
BOARD DESCRIPTION:
Microcontroller interface board is used to condition the signals generated by the
Digital I/O board and to interface the Software Integration Rig system with the LRU’s (DAU,
RU & CIU) of SSFDR. All the TTL signals generated by the DIO board are converted the
levels of +28V & +5V by using Opto couplers present in the interface board. Microcontroller
has been used to read the status of the LRU signals and to control the switching of the relays
present in the interface board.
ROLES & RESPONSIBILITIES:
A. Schematic design.
B. Involved in preparation of the hardware related documents like BOM, Net list,
Hardware requirement specification & Hardware Design Document.
BOARD 3:
Title : CPCI DPFS Board – CPCI based Digitally programmable Frequency Synthesizer.
Client : CABS, Bangalore
Device used : 32 bit PLX Controller (PCI 9054) & Frequency Synthesizer (AD9850),
EEPROM & EPLD.
Tools used : ORCAD, Pspice, Pads Power PCB & MAX PLUS II.
Organization : Avitronics Systemtech (India) Pvt. Ltd.,
PROJECT DESCRIPTION:
This board is developed to generate the 8 numbers of differential sine waves. Optional
output is given to choose single ended or differential. This board can generate the frequency till
300 KHz with the resolution of 1Hz. Frequency synthesizer AD9850, supports programmable
frequency modification.
ROLES & RESPONSIBILITIES:
A. Board design.
B. Involved in preparation of the hardware related documents like BOM, Net list,
Hardware requirement specification & Hardware Design Document.
Karthikbabu Page 5
6. PERSONAL DETAILS
Date of Birth : 13.05.1983
Gender : Male
Nationality : Indian
Marital Status : Married
Passport Number : G327612
Languages known : English, Hindi, Kannada, Tamil & Sourashtra.
DECLARATION:
I hereby declare that all the above information given by me is true to the best of my knowledge
and belief.
Place: Chennai KARTHIK BABU J J
Karthikbabu Page 6
7. PERSONAL DETAILS
Date of Birth : 13.05.1983
Gender : Male
Nationality : Indian
Marital Status : Married
Passport Number : G327612
Languages known : English, Hindi, Kannada, Tamil & Sourashtra.
DECLARATION:
I hereby declare that all the above information given by me is true to the best of my knowledge
and belief.
Place: Chennai KARTHIK BABU J J
Karthikbabu Page 6