Pre-silicon verification of UniPro devices is challenging, demanding and may require significant effort. The layered structure of the specification and the rapid pace of new revisions and features require a flexible, modular and advanced test bench that is well beyond the ability of the traditional directed testing verification schemes that most designers employ. This presentation by Ofir Michaeli of Cadence Design Systems will discuss practical guidelines for defining a proper verification plan; how to design a verification test bench, a scoreboard and a reference model; the pros and cons of standalone verification vs. full stack verification; and a review of real-world verification environments used in actual verification of UFS/UniPro/M-PHY devices.

1. Effective verification
of stacked and layered protocols
Ofir Michaeli
MIPI VIP R&D Team Leader
Cadence Design Systems, Inc.

2. Overview

3. MIPI M-PHY overview
• MIPI M-PHY is a mature Protocol. Current version is M-
PHY 4.0 and the WG is working on version 4.1.

4. MIPI UniPro overview

5. MIPI UniPro overview
• UniPro is a mature Protocol. Current version is UniPro 1.61
(bound to MPHY 3.1) and the WG is working on version 1.8.
• Vast infrastructure support –
• Application notes with Q&As.
• CTS (Conformance Test Suite).
• IOT (Interoperability) events.
• IPs, VIPs, Test equipment and protocol analyzers.
• Key Features –
• Low footprint on power and area.
• Bi-directional.
• Application agnostic.
• Easy to use!
• Guaranteed and in-order delivery of payload.

6. UFS overview
• UFS stands for Universal Flash Storage.
• UFS is high performance storage interface designed for
use in computing and mobile systems requiring low
power consumption (smart phones, tablets, etc.)

7. VIP core
Pre-Silicon Verification
User feeds the DUT’s specific
Configura:on through PureView GUI
Configura)on File
SOMA/UVM Class
BFM
Monitor
PureSpec UI
DUT
TestSuite
Native Coverage
e/SV
NL
Tests
TL
Tests
DME
Tests
PA
Tests
DLL
Tests
DUT
specific
info is
created
VIP
configured
per SOMA,
ready
to test
DUT
vPlan, Coverage
and TestSuite
are filtered
per SOMA parameters

8. • Interfaces – Verifying connection to Upstream/Downstream
Layers:
• RMMI – Physical Layer (M-PHY)
• CPort interface – Application Layer (UFS/ CSI3)
• UniPro DME interface.
• Backward compatibility – Verifying compatibility with designs
implementing older versions of the specification.
• Verifying new features or features that changed between
version.
• Unclear/ Vague Spec. description (for example Deep SAVE
state).
• Running with different configurations or with different set of
supported features.
Verification Challenges

9. Capability Exchange
• New PACP introduced:
• How does a device behave if no
PACP_CAP_EXT1_ind is received or
silently discarded.
• TX_LCC_Enable and LINE-CFG
behavior at the end of burst.

10. Interfaces
• RMMI (Reference M-PHY MODULE Interface) –
• Optional. Described in M-PHY Annex
• UniPro SAPs (Service Access Points) VS. M-PHY Signaling
Interface
• CPort interface –
• Informative. Described in UniPro Annex.
• DME interface – SAPs only.

11. How can a VIP help?
• Checks protocol compliance as per protocol specification.
• Provides full coverage model.
• Generates and drives test sequences.
• VIP interface is flexible –
• No constraints to vendor capabilities.
• Can be configured with different feature
support/ capability settings.
• Developed independently from DUT.
• Make vs. Buy:
• man years of development.
• reused across many designs.
Test
Sequences
State
Machines
Protocol
Checks
Coverage
Model
Verifica)on
Plan
ConfigurationDebug
Methodology-Independent I/F
Mul:-Language
Testbench I/F
Core
VIP
DUT

12. So how do we verify effectively?
Test
Plan
Verification
Plan
Test
And
Debug
Coverage
AnalysisVerification
Environment

13. Verification should start
as early as possible!
13

14. Verification Plan
• Mapping each line in the specification to a verification
item.
• Mapping each item in the plan to a coverage item in the
model.

15. Understand what you
want to test and how to
test it!
15

16. • How much is enough? How much is too much?
• PA Hibernate description – 3 pages, 32 Test scenarios,
Thousands of Test cases.
Test Plan

17. Choose verification
languages and
methodologies wisely!
17

18. Verify all interfaces!
18

19. UniPro VIP
Data Link (L2)
PHY Adapter (L1.5)
PHY (L1)
Partial UniPro DUT connected to DLL+PA
only UniPro VIP using RMMI
DeviceManagementEntity
(DME)
UniPro DUT
MP
MP
MP
RMMI

20. UniPro VIP
UFS MM
Transport (L4)
Network (L3)
Data Link (L2)
PHY Adapter (L1.5)
PHY (L1)
UniPro DUT connected to UFS Device VIP using
RMMI and UniPro Application VIP using CPort
DeviceManagementEntity
(DME)
UniPro DUT
MP
MP
MP
MP
MP
MP
MP
MP
RMMI
UniPro Application
CPort

21. UniPro VIP
UFS MM
Transport (L4)
Network (L3)
Data Link (L2)
PHY Adapter (L1.5)
PHY (L1)
UFS Host DUT connected to UFS Device VIP
using RMMI
DeviceManagementEntity
(DME)
UFS Host DUT
(full stack)MP
MP
MP
MP
MP
MP
MP
MP
RMMI

22. UFS MM
Transport (L4)
Network (L3)
Data Link (L2)
PHY Adapter (L1.5)
PHY (L1)
UFS Host DUT connected to UFS Device VIP
using Serial interface
DeviceManagementEntity
(DME)
UFS Host DUT
(full stack)
UniPro VIP
DPDN
MP
MP
MP
MP
MP
MP
MP
MP

23. M-PHY DPDN VIP
M-PHY DUT connected to M-PHY VIP using
RMMI and Serial interface
MPHY DUT
RMMI
DPDN
M-PHY RMMI VIP

24. Use a PASSIVE agent!
24

25. Verification Environment
Verifica:on test bench
Ac:ve
Master
VIP
Agent
Passive
Slave
VIP
Agent
Slave
DUT
Protocol Lines
Protocol checking and coverage
collec:on configura:on of passive
agent must match DUT configura:on
Genera:on of protocol traffic

26. Invest in tools!
26

27. Test and Debug

28. Test and Debug

29. Always make sure you’re
covered!
29

30. Coverage analysis

31. Effective verification
of stacked and layered protocols
Ofir Michaeli
MIPI VIP R&D Team Leader
Cadence Design Systems, Inc.