This document details the modeling, simulation, and implementation of a non-coherent binary frequency shift keying (BFSK) receiver-transmitter integrated into an FPGA, aimed at addressing data transfer issues with the SINCGARS RT-1523C manpack variant. The study reveals the design processes and parameters used, alongside the successful FPGA implementation that demonstrates minimal hardware utilization with potential for further expansion. Recommendations for subsequent work include bit-error analysis and modifications for enhanced functionality using real SINCGARS equipment.

1. MODELING, SIMULATION AND IMPLEMENTATION OF A NON-COHERENT BINARY FREQUENCY SHIFT KEYING (BFSK) RECEIVER-TRANSMITTER INTO A FIELD PROGRAMMABLE GATE ARRAY (FPGA) Juan P Svenningsen Capt USMC Advisor: H.H. Loomis Co-Advisor: F.E. Kragh Sponsored by MCTSSA

2. Agenda Background Design Approach Design parameters Designs Results Conclusions Recommendations

3. Background Single Channel Ground and Airborne Radio System (SINCGARS) MCTSSA requested that research be done regarding the SINCGARS (RT-1523C) manpack variant’s ineffectiveness in data transfer when in foot-mobile operations Reports via data reduce channel traffic Orders via data increase speed of info exchange Networking of foot mobile units SINCGARS ground radio has been enhanced for vehicle and stationary operations, the foot-mobile variant was only expected to perform voice communications RT-1523C antennas have been identified as a weakness in the system (PRC-77 legacy, never updated)

4. Background Single Channel Ground and Airborne Radio System (SINCGARS) RT-1523C Characteristics: Carrier Sense Multiple Access (CSMA) channel access algorithm Binary Frequency Shift Keying (BFSK) modulation Frequency Hopping Waveform Non-coherent detection R b = 16 kbps f c = 12.5 MHz Allocated Channel BW = 25 kHz Frequency range: 30 – 87.975 MHz Reed-Solomon Coding

5. Background Programmable Devices The programmable logic market started with the programmable logic array device (PLA) and worked it’s way to the FPGA and complex programmable logic devices ( CPLDs ) that we see today. FPGA s are Integrated Circuits (ICs) that are made of many small programmable logic blocks and a fully programmable distribution network that dominates the area of the chip; in contrast CPLDs arrange logic elements into PLDs and link the PLDs with a programmable switch matrix FPGAs have a denser logic element count than CPLDs and are volatile in nature, so when the chip is power down it loses it’s programmed definition CPLDs are permanent or semi-permanent programmable devices that once programmed, they hold their logic definition until it is reprogrammed (if possible, it depends on the device)

6. Stratix FPGA

7. PLD

8. Stratix FPGA Logic Element

9. Background Programmable Devices Due to nature of FPGAs and CPLDs, it is possible to create systems that use both; the CPLD can be programmed to recall the hardware definition from memory in order to program the FPGA at system start-up If a system start-up CPLD is not used, the FPGA must be reprogrammed each time the system is powered down FPGAs tend to be larger in area and more expensive than CPLDs

10. Background MCTSSA Request for Work MCTSSA provided two Altera Stratix Edition DSP Development Boards , with a Stratix FPGA onboard, for the purpose of implementing the RT-1523C onto the boards for testing and system examination purposes MCTSSA requested a solution that would at least implement the RT-1523C modulation and lessons learned for further work with the DSP boards

11. Altera DSP Development Board

12. Design Approach Design Flows

13. Design Approach Stair Step Approach Design and evaluate in software: OOK Transmitter BFSK Transmitter BFSK Receiver BFSK RT Program into hardware: 8-bit counter (hardware familiarization) OOK Tx BFSK Tx BFSK Rx BFSK RT

14. Design Approach Software Design Tools MATLAB Simulink DSP Builder : installed in Simulink via the MATLAB command window. It allows for the use of Simulink as the design input method by using the Simulink environment and the DSP Builder blocks that are installed in the DSP Builder library within the Simulink library SignalCompiler : a DSP builder block that allows for the use of Quartus II directly from the Simulink environment; allows design analysis, synthesis and programming file creation from Simulink Altera Quartus II Device Programmer

15. Design Parameters System Diagram and Parameters 7.5 MHz BW n2n 1.25 Mbps R b 800 ns T b 10 MHz f 1 5 MHz f 0 80 MHz f clock

16. Designs OOK Tx

17. Designs BFSK Tx

18. Noncoherent BFSK Receiver

19. Designs BFSK Rx Receiver Detector

20. Designs BFSK RT

21. Results – OOK Tx

22. Results – BFSK Tx

23. Results – BFSK RT

24. FPGA Fitter Results Average fan-out 5.40 Total fan-out 10537 Maximum fan-out 1110 Maximum fan-out node clock SERDES receivers 0 / 152 ( 0 % ) SERDES transmitters 0 / 152 ( 0 % ) Fast regional clocks 0 / 32 ( 0 % ) Regional clocks 0 / 16 ( 0 % ) DSP block 9-bit elements 40 / 176 ( 22 % ) Total RAM block bits 626,688 / 7,427,520 ( 8 % ) Total memory bits 557,056 / 7,427,520 ( 7 % ) M-RAMs 0 / 9 ( 0 % ) M4Ks 136 / 364 ( 37 % ) M512s 0 / 767 ( 0 % ) Global signals 13 Clock pins 1 / 20 ( 5 % ) I/O pins 57 / 692 ( 8 % ) Virtual pins 0 User inserted logic elements 0 Logic elements in carry chains 617 Total LABs 209 / 7,904 ( 2 % ) Total logic elements 1,721 / 79,040 ( 2 % )

25. Conclusions A non-coherent BFSK RT was successfully implemented into an FPGA Hardware usage was minimal and has space for possible expansion The use of industry provided intellectual property (IP) is becoming more and more useful and commonplace… research and development efforts should not shy away from it because it saves time and maybe even money

26. Recommendations For follow-on work Conduct bit-error analysis on this implementation and compare the FPGA results to the RT-1523C results, and make changes to the system to evaluate the effects of different parameters Analyze this system using actual SINCGARS equipment (antennas) in a wireless channel and make changes to the implementation to evaluate the effects of different parameters Modify this design to perform Reed-Solomon coding/decoding and Frequency-Hopping and maybe even interface with the computer to transmit certain messages that can be input to the hardware via Simulink

27. Sources U.S. Department of Defense. U.S. Marine Corps. MCRP 6-2.2.2 Talk II – SINCGARS: Multiservice Communications Procedures for the Single-Channel Ground and Airborne Ra-dio System , Washington D.C.: GPO, 1996. ITT Industries. “SINCGARS: Evolution to Revolution”, Ft Wayne, Indiana, No Date Given. Hamilton, Bradley J. “SINCGARS System Improvement Pro-gram (SIP) specific radio improvements”, Tactical Commu-nications Conference, 1996: 397-406. Green, Max. “SINCGARS Signal Output Power Test: Test Report - DRAFT”, MCTSSA, Camp Pendelton CA, 18 August 2004. “ Joint Tactical Radio System – JTRS”, [http://jtrs.army.mil/index.htm], last accessed on March 05, 2005. Wakerly, John, F. Digital Design: Principles and Practices , Prentice Hall, New Jersey, 2001. Barr, Michael. "Programmable Logic: What's it to Ya?", Embedded Systems Programming, June 1999, pp. 75-84. Altera Corp. “Stratix Device Handbook”, San Jose, CA, September 2004. Altera Corp. “Stratix EP1S80 DSP Development Board Data Sheet”, San Jose, CA, July 2003. Altera Corp. “DSP Builder User Guide”, San Jose CA, August 2004. Altera Corp. “Application Note 320: OpenCore Plus Evaluation of Megafunctions”, San Jose CA, June 2004. Atera Corp. “Quartus II Handbook, Volumes 1-4”, San Jose CA, December 2004. U.S. Department of Defense. U.S. Marine Corps. TM 5820-45&P/1-1 Volume I, U.S. Marine Corps Technical Man-ual, Intermediate and Depot Maintenance, Single Channel Ground and Airborne Radio System (SINCGARS), Washington D.C.: GPO, 1997. Sklar, Bernard. Digital Communications: Fundamentals and Applications 2d ed., Prentice Hall, New Jersey, 2001.

28. Final Design

29. MODELING, SIMULATION AND IMPLEMENTATION OF A NON-COHERENT BINARY FREQUENCY SHIFT KEYING (BFSK) RECEIVER-TRANSMITTER INTO A FIELD PROGRAMMABLE GATE ARRAY (FPGA) Thank your for your time Juan P Svenningsen Capt USMC Advisor: H.H. Loomis Co-Advisor: F.E. Kragh Sponsored by MCTSSA