This document describes the design of a low power 16x16 SRAM array using adiabatic logic on a 180nm CMOS technology. It begins with an introduction to SRAM and discusses how large SRAM arrays are widely used in applications like cache memory and consume a significant chip area. It then provides background on adiabatic logic and its advantages for low power design. The document outlines the architecture of the designed 16x16 SRAM array, including the key components like the SRAM cell, sense amplifier, and row/column decoders. It presents the schematics of these components and discusses their implementation. Simulation results showing the successful read and write operations are provided. The designed SRAM array achieves low power
The document provides an overview of the dairy industry in India. It discusses how the dairy sector has developed significantly since independence through cooperative models. The National Dairy Development Board was created to promote farmer cooperatives following the successful Anand model. Several state cooperative unions have been established across India that are owned and controlled by rural producers. These cooperatives have helped strengthen the dairy industry and support rural development.
The document discusses identifying, criticizing, and praising qualities in people. It describes physical attributes like hair color, eye shape, nose type, and skin color. A mind map is presented to categorize descriptions of a person's face, hair, eyes, nose, lips, skin, body, age, and other qualities to provide a complete picture.
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
This document summarizes an improved SRAM design implemented using Cadence. The focus was on developing a simplified design by reducing transistor count and replacing some conventional circuit designs. Key aspects of the SRAM design discussed include the 6T SRAM cell, transistor sizing considerations, precharge circuits, sense amplifiers, write amplifiers, decoders, control circuits including flip-flops and write select generators, and specifying input stimuli using digital vector files. The design aims to increase speed and reduce layout area of the SRAM.
This document describes an improved design implementation of SRAM using Cadence. It discusses key aspects of SRAM design including the 6T SRAM cell, transistor sizing considerations, and the main components of an SRAM array. The focus is on developing a simplified design that reduces transistor count and replaces some conventional circuit designs to increase speed and reduce layout area. It provides details on the I/O section comprising the pre-charge circuit, sense amplifier, and write amplifier. It also describes the decoder section that decodes the input address to access a particular memory row.
SRAM BASED IN-MEMORY MATRIX VECTOR MULTIPLIERIRJET Journal
This document describes an SRAM-based in-memory matrix vector multiplier. It discusses using SRAM cells to perform matrix vector multiplication operations directly in memory. The weights stored in the SRAM cells are converted to analog voltages using a DAC. A switched capacitor circuit then multiplies the analog voltages by a digital input vector. Finally, charge sharing is used to sum the output voltages along each column. The circuit size, power consumption, and calculation time scale linearly with the architecture. Analytical formulas are provided for energy usage. The impact of manufacturing variations on precision is also examined.
A Comparitive Analysis of Improved 6t Sram Cell With Different Sram CellIJERA Editor
High speed and low power consumption have been the primary issue to design Static Random Access Memory (SRAM), but we are facing new challenges with the scaling of technology. The stability and speed of SRAM are important issues to improve efficiency and performance of the system. Stability of the SRAM depends on the static noise margin (SNM) so the noise margin is also important parameter for the design of memory because the higher noise margin confirms the high speed of the SRAM cell. In this paper, the improved 6T SRAM cell shows maximum reduction in power consumption of 88%, maximum reduction in delay of 64% and maximum SNM of 17% increases compared with 7T SRAM cell.
The document provides an overview of the dairy industry in India. It discusses how the dairy sector has developed significantly since independence through cooperative models. The National Dairy Development Board was created to promote farmer cooperatives following the successful Anand model. Several state cooperative unions have been established across India that are owned and controlled by rural producers. These cooperatives have helped strengthen the dairy industry and support rural development.
The document discusses identifying, criticizing, and praising qualities in people. It describes physical attributes like hair color, eye shape, nose type, and skin color. A mind map is presented to categorize descriptions of a person's face, hair, eyes, nose, lips, skin, body, age, and other qualities to provide a complete picture.
Design and Simulation Low power SRAM Circuitsijsrd.com
SRAMs), focusing on optimizing delay and power. As the scaling trends in the speed and power of SRAMs with size and technology and find that the SRAM delay scales as the logarithm of its size as long as the interconnect delay is negligible. Non-scaling of threshold mismatches with process scaling, causes the signal swings in the bitlines and data lines also not to scale, leading to an increase in the relative delay of an SRAM, across technology generations. Appropriate methods for reduction of power consumption were studied such as capacitance reduction, very low operating voltages, DC and AC current reduction and suppression of leakage currents to name a few.. Many of reviewed techniques are applicable to other applications such as ASICs, DSPs, etc. Battery and solar-cell operation requires an operating voltage environment in low voltage area. These conditions demand new design approaches and more sophisticated concepts to retain high device reliability. The proposed techniques (USRS and LPRS) are topology based and hence easier to implement.
This document summarizes an improved SRAM design implemented using Cadence. The focus was on developing a simplified design by reducing transistor count and replacing some conventional circuit designs. Key aspects of the SRAM design discussed include the 6T SRAM cell, transistor sizing considerations, precharge circuits, sense amplifiers, write amplifiers, decoders, control circuits including flip-flops and write select generators, and specifying input stimuli using digital vector files. The design aims to increase speed and reduce layout area of the SRAM.
This document describes an improved design implementation of SRAM using Cadence. It discusses key aspects of SRAM design including the 6T SRAM cell, transistor sizing considerations, and the main components of an SRAM array. The focus is on developing a simplified design that reduces transistor count and replaces some conventional circuit designs to increase speed and reduce layout area. It provides details on the I/O section comprising the pre-charge circuit, sense amplifier, and write amplifier. It also describes the decoder section that decodes the input address to access a particular memory row.
SRAM BASED IN-MEMORY MATRIX VECTOR MULTIPLIERIRJET Journal
This document describes an SRAM-based in-memory matrix vector multiplier. It discusses using SRAM cells to perform matrix vector multiplication operations directly in memory. The weights stored in the SRAM cells are converted to analog voltages using a DAC. A switched capacitor circuit then multiplies the analog voltages by a digital input vector. Finally, charge sharing is used to sum the output voltages along each column. The circuit size, power consumption, and calculation time scale linearly with the architecture. Analytical formulas are provided for energy usage. The impact of manufacturing variations on precision is also examined.
A Comparitive Analysis of Improved 6t Sram Cell With Different Sram CellIJERA Editor
High speed and low power consumption have been the primary issue to design Static Random Access Memory (SRAM), but we are facing new challenges with the scaling of technology. The stability and speed of SRAM are important issues to improve efficiency and performance of the system. Stability of the SRAM depends on the static noise margin (SNM) so the noise margin is also important parameter for the design of memory because the higher noise margin confirms the high speed of the SRAM cell. In this paper, the improved 6T SRAM cell shows maximum reduction in power consumption of 88%, maximum reduction in delay of 64% and maximum SNM of 17% increases compared with 7T SRAM cell.
This document describes the design and analysis of a 10T CMOS SRAM cell using 0.6 μm technology to reduce power consumption during write operations. It first discusses 6T SRAM cells and issues with scaling. It then presents the design of a conventional 6T SRAM cell in Microwind 2 using 0.6 μm technology files and describes its read/write operations. Next, it proposes a 10T SRAM cell with two tail transistors added to the pull down network and bit lines cross-coupled to these transistors. This is claimed to help control leakage current and efficiently charge/discharge bit lines during writes. Simulation results then show the proposed 10T cell reduces average write power consumption by 38.6% compared
The document discusses the advantages of a 5T SRAM compared to a conventional 6T SRAM. It summarizes the design and layout of a 64-bit 5T SRAM using a 90nm technology. Simulation results show that the 5T SRAM reduces power dissipation by 36.2-37.2% and leakage current by 35-36.6% compared to a 64-bit 6T SRAM, while also reducing the area by 30.2%. The document concludes that the 5T SRAM design provides improvements in power, leakage current and area over a conventional 6T SRAM.
This document discusses the advantages of a 5T SRAM cell compared to a traditional 6T SRAM cell. It summarizes the design and operation of a 5T SRAM cell, which removes one transistor compared to a 6T cell. This reduces power consumption by eliminating the need to charge and discharge one of the bit lines during read and write operations. The document then describes the layout design of a 64-bit 5T SRAM using a 90nm technology node. It compares the performance of this 64-bit 5T SRAM to a 64-bit 6T SRAM in terms of power consumption, layout area, number of transistors, and leakage current.
Design and Performance Evaluation of a 64-bit SRAM Memory Array Utilizing Mod...IRJET Journal
This document summarizes a research paper that designed and evaluated the performance of a 64-bit SRAM memory array using modern deep submicron technology. The key points are:
1) A 64-bit SRAM memory array was designed using a 1-bit 7T SRAM cell and implemented in a 8x8 bit configuration using CMOS technology and a 0.7 volt supply.
2) The 7T SRAM cell design aimed to reduce leakage power during read/write operations and improve noise immunity at low voltages.
3) Simulation results showed the 64-bit SRAM array had lower read and write power consumption compared to 8T and 7T SRAM designs.
The document describes the design and simulation of a 16-bit 4x4 SRAM memory using a 6T SRAM cell. It analyzes the SRAM cell and array architecture, including precharging, addressing, and data retention voltage. Simulation results show the read and write operations and compare the static power of a traditional 4x4 SRAM array (730.8uW) to a multi-divided wordline array (155.8uW), demonstrating power reduction using the divided wordline technique.
250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
The document summarizes research on reducing power consumption in 4T SRAM cells through a stacking technique. It describes the conventional 4T SRAM cell and its operations. A proposed design is presented using a stacking transistor controlled by a signal to reduce leakage current. Simulations using Tanner EDA show the proposed cell has lower maximum, minimum, and average power compared to the conventional cell during write operations. The stacking technique is effective for lowering power consumption in SRAM cells.
IRJET- Modified Low Power Single Bit-Line Static Random-Access Memory Cell Ar...IRJET Journal
The document discusses a modified low power single bit-line static random access memory (SRAM) cell architecture. It begins by introducing the issues of power consumption in memory systems and discusses existing techniques to reduce power, including adiabatic logic. It then presents a previously proposed single bit-line SRAM cell with an adiabatically operated word line. The document goes on to propose a modification to this cell that eliminates one transistor, reducing power consumption from 0.498mW to 0.350mW without impacting stability or performance. Simulation results demonstrating the power reduction are shown and conclusions are drawn about the benefits of the modified low power cell.
Design of Low Power High Density SRAM Bit CellIRJET Journal
The document describes the design of a low power, high density 4T SRAM bit cell. It begins by introducing the motivation to minimize power and area in memory designs for portable devices. It then describes the conventional 6T SRAM cell and compares it to the proposed 4T cell. Simulation results show the 4T cell reduces power consumption by approximately 40% and area by 35% compared to the 6T cell. In conclusion, the 4T cell is shown to achieve both reduced power and area making it suitable for high density, low power memory applications.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed...VLSICS Design
This document summarizes the design and analysis of SRAM and DRAM cells for low power consumption. It describes a 12-transistor SRAM cell built from a static latch and tri-state inverter that provides high speed. A conventional 6T SRAM cell is also discussed. DRAM cells provide higher density than SRAM but require periodic refresh to prevent data loss from capacitor leakage. Simulation results show the 12T SRAM cell and a 32x32 SRAM array function correctly in 130nm, 90nm, and 65nm technologies with good noise margins and stable output. The design flow uses Cadence tools with a 45nm process to achieve very low power consumption.
Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Spee...VLSICS Design
This paper deals with the design and analysis of high speed Static Random Access Memory (SRAM) cell and Dynamic Random Access Memory (DRAM) cell to develop low power consumption. SRAM and DRAM cells have been the predominant technologies used to implement memory cells in computer systems, each one having its advantages and shortcomings. SRAM cells are faster and require no refresh since reads are not destructive. In contrast, DRAM cells provide higher density and minimal leakage energy. Here we use 12-transistor SRAM cell built from a simple static latch and tri state inverter. The reading action itself refreshes the content of memory. The SRAM access path is split into two portions: from address input to word line rise (the row decoder) and from word line rise to data output (the read data path). The decoder which constitutes the path from address input to the word line rise is implemented as a binary structure by implementing a multi-stage path. The key to low power operation in the SRAM data path is to reduce the signal swings on the high capacitance nodes like the bit lines and the data lines.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET- Comparative Analysis of High Speed SRAM Cell for 90nm CMOS TechnologyIRJET Journal
This document presents a comparative analysis of 6T and 8T SRAM cells for 90nm CMOS technology. It begins with an abstract discussing the simulation of low power SRAM cells at different frequencies. The main body then provides background on SRAM cells, discusses related work analyzing 6T and 8T SRAM cell designs. It presents the architecture and operating principles of an 8T SRAM cell, including write and read modes. Simulation results show the 8T SRAM cell has lower dynamic power consumption than a 6T cell, with readings of 82 micro Watts for read and 120 micro Watts for write. Logic validation testing confirms the 8T cell correctly writes and reads input bit values.
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
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This document discusses the advantages of a 5T SRAM cell compared to a traditional 6T SRAM cell. It summarizes the design and operation of a 5T SRAM cell, which removes one transistor compared to a 6T cell. This reduces power consumption by eliminating the need to charge and discharge one of the bit lines during read and write operations. The document then describes the layout design of a 64-bit 5T SRAM using a 90nm technology node. It compares the performance of this 64-bit 5T SRAM to a 64-bit 6T SRAM in terms of power consumption, layout area, number of transistors, and leakage current.
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This document summarizes a research paper that designed and evaluated the performance of a 64-bit SRAM memory array using modern deep submicron technology. The key points are:
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2) The 7T SRAM cell design aimed to reduce leakage power during read/write operations and improve noise immunity at low voltages.
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250nm Technology Based Low Power SRAM Memoryiosrjce
High integration density, low power and fastperformance are all critical parameters in designing of
memory blocks. Static Random Access Memories (SRAMs)’s focusing on optimizing dynamic power concept of
virtual source transistors is used for removing direct connection between VDD and GND.
Also stacking effect can be reduced by switching off the stacktransistors when the memory is ideal and the
leakage current using SVL techniques This paper discusses the evolution of 9t SRAM circuits in terms of low
power consumption, The whole circuit verification is done on the Tanner tool, Schematic of the
SRAM cell is designed on the S-Edit and net list simulation done by using T-spice and waveforms are analyzed
through the W-edit
Power analysis of 4 t sram by stacking technique using tanner tooleSAT Publishing House
The document summarizes research on reducing power consumption in 4T SRAM cells through a stacking technique. It describes the conventional 4T SRAM cell and its operations. A proposed design is presented using a stacking transistor controlled by a signal to reduce leakage current. Simulations using Tanner EDA show the proposed cell has lower maximum, minimum, and average power compared to the conventional cell during write operations. The stacking technique is effective for lowering power consumption in SRAM cells.
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Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
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IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Design & Implementation of Subthreshold Memory Cell design based on the prima...IOSRJVSP
As there is a demand for portable electronic systems or devices, there is an incremental growth in the technology in the past few decades and also technology is cumulative at a random rate, devices are consuming large amount of power due to this the life of the battery is draining fast. so there must be a alternative devices or circuits which can reduce the power by efficiently maintaining the area and performance, therefore life of battery can be increased. As SRAM is the heart of block in all the electronic design, where the power consumption is maximum there by analyzing, estimating & modifying or changing the logic, will be able to reduce the power and performance can be greatly achieved. This proposal describes under the principle of ultra-low power logic approach which operates under subthreshold voltage operating which leads to lower power and also efficient in functionality along with secondary constraints.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
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3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
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This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
The document discusses optimizing business management processes through automation using Microsoft Power Automate and artificial intelligence. It provides an overview of Power Automate's key components and features for automating workflows across various apps and services. The document then presents several scenarios applying automation solutions to common business processes like data entry, monitoring, HR, finance, customer support, and more. It estimates the potential time and cost savings from implementing automation for each scenario. Finally, the conclusion emphasizes the transformative impact of AI and automation tools on business processes and the need for ongoing optimization.
Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
The document describes the seismic design of a G+5 steel building frame located in Roorkee, India according to Indian codes IS 1893-2002 and IS 800. The frame was analyzed using the equivalent static load method and response spectrum method, and its response in terms of displacements and shear forces were compared. Based on the analysis, the frame was designed as a seismic-resistant steel structure according to IS 800:2007. The software STAAD Pro was used for the analysis and design.
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
Software Engineering and Project Management - Introduction, Modeling Concepts...Prakhyath Rai
Introduction, Modeling Concepts and Class Modeling: What is Object orientation? What is OO development? OO Themes; Evidence for usefulness of OO development; OO modeling history. Modeling
as Design technique: Modeling, abstraction, The Three models. Class Modeling: Object and Class Concept, Link and associations concepts, Generalization and Inheritance, A sample class model, Navigation of class models, and UML diagrams
Building the Analysis Models: Requirement Analysis, Analysis Model Approaches, Data modeling Concepts, Object Oriented Analysis, Scenario-Based Modeling, Flow-Oriented Modeling, class Based Modeling, Creating a Behavioral Model.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
Discover the latest insights on Data Driven Maintenance with our comprehensive webinar presentation. Learn about traditional maintenance challenges, the right approach to utilizing data, and the benefits of adopting a Data Driven Maintenance strategy. Explore real-world examples, industry best practices, and innovative solutions like FMECA and the D3M model. This presentation, led by expert Jules Oudmans, is essential for asset owners looking to optimize their maintenance processes and leverage digital technologies for improved efficiency and performance. Download now to stay ahead in the evolving maintenance landscape.