This paper proposes a novel graph-based method to automatically generate optimized transistor networks from a sum-of-products expression to improve speed, power, and area of VLSI circuits. The method identifies efficient sub-networks ("kernels") from the graph representation and combines them, with transistor sharing, into a single minimized network. Experimental results show transistor count reduction compared to other approaches, leading to gains in gate performance, power, and area. The method was implemented in software simulation tools and on Spartan FPGA hardware.