This document summarizes a study that used TCAD (Technology Computer-Aided Design) simulation to evaluate the characteristics of an optically illuminated MOSFET. The study modeled an LDD N-channel MOSFET using process and device simulators. It analyzed the MOSFET's DC and AC characteristics under dark and illuminated conditions. The results indicate that optical illumination modifies the depletion region widths and enhances conductivity, showing potential for optoelectronic applications using a MOSFET as an optically sensitive structure.
Optimization of Empirical Modelling of Advanced Highly Strained In 0.7 Ga 0.3...IJECEIAES
An optimized empirical modelling for a 0.25µm gate length of highly strained channel of an InP-based pseudomorphic high electron mobility transistor (pHEMT) using InGaAs–InAlAs material systems is presented. An accurate procedure for extraction is described and tested using the pHEMT measured dataset of I-V characteristics and related multi-bias s-parameters over 20GHz frequency range. The extraction of linear and nonlinear parameters from the small signal and large signal pHEMT equivalent model are performed in ADS. The optimized DC and S-parameter model for the pHEMT device provides a basis for active device selection in the MMIC low noise amplifier circuit designs.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET IJECEIAES
This article presents extraction of small signal model parameters and TCAD simulation of novel asymmetric field plated dual material gate AlGaN/GaN HFET first time. Small signal model is essential for design of LNA and microwave electronic circuit by using the proposed superior performance HFET structure. Superior performances of device are due to its dual material gate structure and field plate that can provide better electric field uniformity, suppression of short channel effects and improvement in carrier transport efficiency. In this article we used direct parameter extraction methodology in which S-parameters of device were measured using pinchoff cold FET biasing. The measured S-parameters are then transformed into Y-parameters to extract capacitive elements and then in to Z-parameters to extract series parasitic elements. Intrinsic parameters are extracted from Y-parameters after de-embedding all parasitic elements of devce. Microwave figure of merits and dc performance are also studied for proposed HFET. The important figure of merits of device reported in the paper include transconductance, drain conductance, current gain, transducer power gain, available power gain, maximum stable gain, maximum frequency of oscillation, cut-off frequency, stability factor and time delay. Reported results are valdated with experimental and simulation results for consistency accuracy.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
THE EFFECT OF INTERFACE MODIFICATION BY PEDOT: PSS ON THE HOLE MOBILITY OF TH...ijoejournal
The purpose of the work is to understand how to effect the interface PEDOT: PSS on the hole mobility of
the LEC device by Space Charge Limited Current (SCLC) approaches technique. PEDOT: PSS plays a
significant role in organic electronics device as interface modification, particularly on Light-emitting
electrochemical cells (LEC) due to fundamental structure of hole only device. This study analyses the hole
mobility of the device based on current-voltage characteristic approach at room temperature. It has been
observed that the PEDOT: PSS interface increases the hole mobility of the LEC device by a factor of 108
.
Optimization of Empirical Modelling of Advanced Highly Strained In 0.7 Ga 0.3...IJECEIAES
An optimized empirical modelling for a 0.25µm gate length of highly strained channel of an InP-based pseudomorphic high electron mobility transistor (pHEMT) using InGaAs–InAlAs material systems is presented. An accurate procedure for extraction is described and tested using the pHEMT measured dataset of I-V characteristics and related multi-bias s-parameters over 20GHz frequency range. The extraction of linear and nonlinear parameters from the small signal and large signal pHEMT equivalent model are performed in ADS. The optimized DC and S-parameter model for the pHEMT device provides a basis for active device selection in the MMIC low noise amplifier circuit designs.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design High Performance Combinational Circuits Using Output Prediction Logic-...IOSRJECE
With the continuously increasing demand for low power & high speed VLSI circuits the brain storming among the scientists, inventors & researchers to find the techniques required to design such high performance circuits is also increasing day by day. In the answer to this search several design techniques have been found. Output prediction logic-OPL technique is one of such newly introduced techniques. OPL is a technique that can be applied to conventional CMOS logic families in order to obtain considerable speedups. Speedups of two to three times over static CMOS logic are demonstrated for a variety of combinational circuits. When applied to static CMOS the OPL retains the restoring nature of underlying logic family. In case of OPL applied to the pseudo NMOS & domino logic, the problem of excessive power dissipation is solved & speedups more than static CMOS logic is obtained
TCAD Simulations and Small Signal Modeling of DMG AlGaN/GaN HFET IJECEIAES
This article presents extraction of small signal model parameters and TCAD simulation of novel asymmetric field plated dual material gate AlGaN/GaN HFET first time. Small signal model is essential for design of LNA and microwave electronic circuit by using the proposed superior performance HFET structure. Superior performances of device are due to its dual material gate structure and field plate that can provide better electric field uniformity, suppression of short channel effects and improvement in carrier transport efficiency. In this article we used direct parameter extraction methodology in which S-parameters of device were measured using pinchoff cold FET biasing. The measured S-parameters are then transformed into Y-parameters to extract capacitive elements and then in to Z-parameters to extract series parasitic elements. Intrinsic parameters are extracted from Y-parameters after de-embedding all parasitic elements of devce. Microwave figure of merits and dc performance are also studied for proposed HFET. The important figure of merits of device reported in the paper include transconductance, drain conductance, current gain, transducer power gain, available power gain, maximum stable gain, maximum frequency of oscillation, cut-off frequency, stability factor and time delay. Reported results are valdated with experimental and simulation results for consistency accuracy.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
THE EFFECT OF INTERFACE MODIFICATION BY PEDOT: PSS ON THE HOLE MOBILITY OF TH...ijoejournal
The purpose of the work is to understand how to effect the interface PEDOT: PSS on the hole mobility of
the LEC device by Space Charge Limited Current (SCLC) approaches technique. PEDOT: PSS plays a
significant role in organic electronics device as interface modification, particularly on Light-emitting
electrochemical cells (LEC) due to fundamental structure of hole only device. This study analyses the hole
mobility of the device based on current-voltage characteristic approach at room temperature. It has been
observed that the PEDOT: PSS interface increases the hole mobility of the LEC device by a factor of 108
.
Performance Evaluation of two Port and four Port Measurement for Twisted Pair...IJECEIAES
A balance-unbalance (balun) transformer is commonly used to connect the balance 100 Ohm twisted pair cable to the unbalance 50 Ohm network analyzer ports, but due to the limitations of the core (i.e. ferrite) inside the balun, the balun can only effectively operates at a certain band of frequencies. This limitation can be eliminated by using a 4-port vector network analyzer (VNA) which is done by connecting the VNA’s ports to each conductor end. The extracted S-parameters will then be transformed to a 2-port S-parameters in differential mode at both ports. To validate the measurement technique, S-parameter measurement by using the 4-Port Network Analyzer without any balun will be compared to the measurement which used the 2-Port Network Analyzer with the balun transformers. Two twisted pair cable distances are selected as reference which are 500, and 1000 meters with nominal copper diameter of 0.5mm. Based on the measurement results, the 4-ports measurement shows good correlation with the 2-ports measurement especially at 500m distance. This shows that the 4-ports measurement setup is suitable to be used to measure twisted pair copper cable and possible to measure at a higher frequency band such as up to 500 MHz but at a shorter twisted pair cable distance.
Geometric and process design of ultra-thin junctionless double gate vertical ...IJECEIAES
The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...IJECEIAES
In this paper, we present an extensive analysis of the performance degradation in MOS- FET based circuits. The physical effects that we consider are the random dopant fluctuation (RDF), the oxide thickness fluctuation (OTF) and the Hot-carrier-Instability (HCI). The work that we propose is based on two main key points: First, the performance degradation is studied considering BULK, Silicon-On-Insulator (SOI) and Double Gate (DG) MOSFET technologies. The analysis considers technology nodes from 45nm to 11nm. For the HCI effect we consider also the time-dependent evolution of the parameters of the circuit. Second, the analysis is performed from transistor level to gate level. Models are used to evaluate the variation of transistors key parameters, and how these variation affects performance at gate level as well.The work here presented was obtained using TAMTAMS Web, an open and publicly available framework for analysis of circuits based on transistors. The use of TAMTAMS Web greatly increases the value of this work, given that the analysis can be easily extended and improved in both complexity and depth.
Performance analysis of ultrathin junctionless double gate vertical MOSFETsjournalBEEI
The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.
EFFECTIVE PEEC MODELING OF TRANSMISSION LINES STRUCTURES USING A SELECTIVE ME...EEIJ journal
The transmission lines structures are quite common in the system of electromagnetic compatibility (EMC)
analysis. The increasing complexities of physical structures make electromagnetic modeling an
increasingly tough task, and computational efficiency is desirable. In this paper, a novel selective mesh
approach is presented for partial element equivalent circuit (PEEC) modeling where intense coupling parts
are meshed while the remaining parts are eliminated. With the proposed approach, the meshed ground
plane is dependent on the length and height of the above transmission lines. Relevant compact formulae for
determining mesh boundaries are deduced, and a procedure of general mesh generation is also given. A
numerical example is presented, and a validation check is accomplished, showing that the approach leads
to a significant reduction in unknowns and thus computation time and consumed memories, while
preserving the sufficient precision. This approach is especially useful for modeling the electromagnetic
coupling of transmission lines and reference ground, and it may also be beneficial for other equivalent
circuit modeling techniques.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
1x2 Digital Optoelectronic Switch using MZI structure and studying the Effect...ijsrd.com
The electro optic switch has wide application in optical network due to capability of route the light path from one port to the desired port. In this paper, we propose a 1x2 digital optoelectronics switch based on mach-zehnder interferometer structure on a single titanium diffuse lithium niobate substrate. The design is simulate on BPM-cad simulator for switch analysis and study the effect of bipolar voltage 0v to ± 5.75v applied at 1st and center electrode region for switching. A short study of wavelength dependent switch for first optical window 8.5 µm and third optical window 1.55 µm has been simulated without use of voltage with changing titanium stripe thickness to 0.07µm.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Modelling of next zen memory cell using low power consuming high speed nano d...eSAT Journals
Abstract Hybrid SET-CMOS circuits which syndicate the assets of both the SET [Single Electron Transistor] and CMOS depicts highest possibilities to be incorporated in practical implementation for future low power VLSI/ULSI configurations. The proposed work is an attempt based on SET-CMOS hybrid circuit to realize the next gen simple Memory Cell. The authors adhered to MIB model for SET and BSIM4 model for CMOS in realizing the complex cell. The maneuver of the proposed circuit is verified subsequently in standard environment. The outcomes are in good trade off with the conventional statistics of existing memory cell. Keywords: SET, SED, Hybrid CMOS-SET, MIB and Memory Cell
Comparative Performance Analysis of RPL for Low Power and Lossy Networks base...Kashif Mehmood
The Internet of Things (IoT) is an extensive
network between people-people, people-things and things-things.
With the overgrown opportunities, then it also comes with a lot of
challenges proportional to the number of connected things to the
network. The IPv6 allows us to connect a huge number of things.
For resource-constrained IoT devices, the routing issues are very
thought-provoking and for this purpose an IPv6 Routing
Protocol for Low-Power and Lossy Networks (RPL) is proposed.
There are multi-HOP paths connecting nodes to the root node.
Destination Oriented Directed Acyclic Graph (DODAG) is
created taking into account different parameters such as link
costs, nodes attribute and objective functions. RPL is flexible
and it can be tuned as per application demands, therefore, the
network can be optimized by using different objective functions.
This paper presents a novel energy efficient analysis of RPL by
performing a set of simulations in COOJA simulator. The
performance evaluation of RPL is compared by introducing
different Objective functions (OF) with multiple metrics for the
network.
Comparative analysis of technology advancement from single gate to multi gate...eSAT Journals
Abstract
Among the entire contender in modern microelectronics,DG-MOSFET is a front line runner in planar technology. Itsunique
structure allows scaling the device at sub-nanometer region and mimicking the electrical characteristics of a MOSFET.Here
simulation of NMOS, SOI-NMOS, and DG-NMOS is presentedand relative comparison among short channel characteristics
ispresented.It has been seen that among all the above stated device, DG-MOSFET possess better immune to leakage current with
betterDIBL, whereas SOI MOSFET have better driving capacity.
KeyWords:SOI-MOSFET, DG-MOSFET, UTB, DIBL,SCEs
The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.
Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip IJECEIAES
Multiprocessor system-on-chip (MPSoC) has become an attractive solution for improving the performance of single chip in objective to satisfy the performance growing exponentially of the computer applications as multimedia applications. However, the communication between the different processors’ cores presents the first challenge front the high performance of MPSoC. Besides, Network on Chip (NoC) is among the most prominent solution for handling the on-chip communication. Besides, NoC potential limited by physical limitation, power consumption, latency and bandwidth in the both case: increasing data exchange or scalability of Multicores. Optical communication offers a wider bandwidth and lower power consumption, based on, a new technology named Optical Network-on-Chip (ONoC) has been introduced in MPSoC. However, ONoC components induce the crosstalk noise in the network on both forms intra/inter crosstalk. This serious problem deteriorates the quality of signals and degrades network performance. As a result, detection and monitoring the impairments becoming a challenge to keep the performance in the ONoC. In this article, we propose a new system to detect and monitor the crosstalk noise in ONoC. Particularly, we present an analytic model of intra/inter crosstalk at the optical devices. Then, we evaluate these impairments in objective to present the motivation to detect and monitor crosstalk in ONoC, in which our system has the capability to detect, to localize, and to monitor the crosstalk noise in the whole network. This system offers high reliability, scalability and efficiency with time running time less than 20 ms.
Operational transconductance amplifier-based comparator for high frequency a...IJECEIAES
Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.
Performance Evaluation of two Port and four Port Measurement for Twisted Pair...IJECEIAES
A balance-unbalance (balun) transformer is commonly used to connect the balance 100 Ohm twisted pair cable to the unbalance 50 Ohm network analyzer ports, but due to the limitations of the core (i.e. ferrite) inside the balun, the balun can only effectively operates at a certain band of frequencies. This limitation can be eliminated by using a 4-port vector network analyzer (VNA) which is done by connecting the VNA’s ports to each conductor end. The extracted S-parameters will then be transformed to a 2-port S-parameters in differential mode at both ports. To validate the measurement technique, S-parameter measurement by using the 4-Port Network Analyzer without any balun will be compared to the measurement which used the 2-Port Network Analyzer with the balun transformers. Two twisted pair cable distances are selected as reference which are 500, and 1000 meters with nominal copper diameter of 0.5mm. Based on the measurement results, the 4-ports measurement shows good correlation with the 2-ports measurement especially at 500m distance. This shows that the 4-ports measurement setup is suitable to be used to measure twisted pair copper cable and possible to measure at a higher frequency band such as up to 500 MHz but at a shorter twisted pair cable distance.
Geometric and process design of ultra-thin junctionless double gate vertical ...IJECEIAES
The junctionless MOSFET architectures appear to be attractive in realizing the Moore’s law prediction. In this paper, a comprehensive 2-D simulation on junctionless vertical double-gate MOSFET (JLDGVM) under geometric and process consideration was introduced in order to obtain excellent electrical characteristics. Geometrical designs such as channel length (Lch) and pillar thickness (Tp) were considered and the impact on the electrical performance was analyzed. The influence of doping concentration and metal gate work function (WF) were further investigated for achieving better performance. The results show that the shorter Lch can boost the drain current (ID) of n-JLDGVM and p-JLDGVM by approximately 68% and 70% respectively. The ID of the n-JLVDGM and p-JLVDGM could possibly boost up to 42% and 78% respectively as the Tp is scaled down from 11nm to 8nm. The channel doping (Nch) is also a critical parameter, affecting the electrical performance of both n-JLDGVM and p-JLDGVM in which 15% and 39% improvements are observed in their respective ID as the concentration level is increased from 1E18 to 9E18 atom/cm3. In addition, the adjustment of threshold voltage can be realized by varying the metal WF.
A Unified Approach for Performance Degradation Analysis from Transistor to Gat...IJECEIAES
In this paper, we present an extensive analysis of the performance degradation in MOS- FET based circuits. The physical effects that we consider are the random dopant fluctuation (RDF), the oxide thickness fluctuation (OTF) and the Hot-carrier-Instability (HCI). The work that we propose is based on two main key points: First, the performance degradation is studied considering BULK, Silicon-On-Insulator (SOI) and Double Gate (DG) MOSFET technologies. The analysis considers technology nodes from 45nm to 11nm. For the HCI effect we consider also the time-dependent evolution of the parameters of the circuit. Second, the analysis is performed from transistor level to gate level. Models are used to evaluate the variation of transistors key parameters, and how these variation affects performance at gate level as well.The work here presented was obtained using TAMTAMS Web, an open and publicly available framework for analysis of circuits based on transistors. The use of TAMTAMS Web greatly increases the value of this work, given that the analysis can be easily extended and improved in both complexity and depth.
Performance analysis of ultrathin junctionless double gate vertical MOSFETsjournalBEEI
The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.
EFFECTIVE PEEC MODELING OF TRANSMISSION LINES STRUCTURES USING A SELECTIVE ME...EEIJ journal
The transmission lines structures are quite common in the system of electromagnetic compatibility (EMC)
analysis. The increasing complexities of physical structures make electromagnetic modeling an
increasingly tough task, and computational efficiency is desirable. In this paper, a novel selective mesh
approach is presented for partial element equivalent circuit (PEEC) modeling where intense coupling parts
are meshed while the remaining parts are eliminated. With the proposed approach, the meshed ground
plane is dependent on the length and height of the above transmission lines. Relevant compact formulae for
determining mesh boundaries are deduced, and a procedure of general mesh generation is also given. A
numerical example is presented, and a validation check is accomplished, showing that the approach leads
to a significant reduction in unknowns and thus computation time and consumed memories, while
preserving the sufficient precision. This approach is especially useful for modeling the electromagnetic
coupling of transmission lines and reference ground, and it may also be beneficial for other equivalent
circuit modeling techniques.
Quantum-dot Cellular Automata (QCA) is an alternative innovation to the
Complementary Metal Oxide Semiconductor (CMOS) because CMOS has scaling
limitations that lead to high leakage power. QCA is structured on quantum cells, whose
sizes are on the nanoscale. This component causes faults in QCA circuits. Converting
a code into another that is programmed in logic arrays becomes important in the
physical realization of the circuits. There are many methods to resolve this problem in
circuits. A code converter is a solution to convert one code into another. In this paper,
QCA-based “4-bit binary-to-gray” and “4-bit gray-to-binary code converters” are
suggested. The offered layout prospects to a decrease in energy expenditure and can
be utilized in many fields for shielding data from outsiders and increasing information
flexibility. We executed a relative analysis of the suggested design with present earlier
designs and turned out that the suggested layout is productive on condition that
complexity, cell count, area intake, and clocking. This paper offers a streamlined design
and layout concerning code converters depending on QCA. These structures are
designed with the QCADesigner, simulator and the simulation results are examined.
1x2 Digital Optoelectronic Switch using MZI structure and studying the Effect...ijsrd.com
The electro optic switch has wide application in optical network due to capability of route the light path from one port to the desired port. In this paper, we propose a 1x2 digital optoelectronics switch based on mach-zehnder interferometer structure on a single titanium diffuse lithium niobate substrate. The design is simulate on BPM-cad simulator for switch analysis and study the effect of bipolar voltage 0v to ± 5.75v applied at 1st and center electrode region for switching. A short study of wavelength dependent switch for first optical window 8.5 µm and third optical window 1.55 µm has been simulated without use of voltage with changing titanium stripe thickness to 0.07µm.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Modelling of next zen memory cell using low power consuming high speed nano d...eSAT Journals
Abstract Hybrid SET-CMOS circuits which syndicate the assets of both the SET [Single Electron Transistor] and CMOS depicts highest possibilities to be incorporated in practical implementation for future low power VLSI/ULSI configurations. The proposed work is an attempt based on SET-CMOS hybrid circuit to realize the next gen simple Memory Cell. The authors adhered to MIB model for SET and BSIM4 model for CMOS in realizing the complex cell. The maneuver of the proposed circuit is verified subsequently in standard environment. The outcomes are in good trade off with the conventional statistics of existing memory cell. Keywords: SET, SED, Hybrid CMOS-SET, MIB and Memory Cell
Comparative Performance Analysis of RPL for Low Power and Lossy Networks base...Kashif Mehmood
The Internet of Things (IoT) is an extensive
network between people-people, people-things and things-things.
With the overgrown opportunities, then it also comes with a lot of
challenges proportional to the number of connected things to the
network. The IPv6 allows us to connect a huge number of things.
For resource-constrained IoT devices, the routing issues are very
thought-provoking and for this purpose an IPv6 Routing
Protocol for Low-Power and Lossy Networks (RPL) is proposed.
There are multi-HOP paths connecting nodes to the root node.
Destination Oriented Directed Acyclic Graph (DODAG) is
created taking into account different parameters such as link
costs, nodes attribute and objective functions. RPL is flexible
and it can be tuned as per application demands, therefore, the
network can be optimized by using different objective functions.
This paper presents a novel energy efficient analysis of RPL by
performing a set of simulations in COOJA simulator. The
performance evaluation of RPL is compared by introducing
different Objective functions (OF) with multiple metrics for the
network.
Comparative analysis of technology advancement from single gate to multi gate...eSAT Journals
Abstract
Among the entire contender in modern microelectronics,DG-MOSFET is a front line runner in planar technology. Itsunique
structure allows scaling the device at sub-nanometer region and mimicking the electrical characteristics of a MOSFET.Here
simulation of NMOS, SOI-NMOS, and DG-NMOS is presentedand relative comparison among short channel characteristics
ispresented.It has been seen that among all the above stated device, DG-MOSFET possess better immune to leakage current with
betterDIBL, whereas SOI MOSFET have better driving capacity.
KeyWords:SOI-MOSFET, DG-MOSFET, UTB, DIBL,SCEs
The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.
Detection and Monitoring Intra/Inter Crosstalk in Optical Network on Chip IJECEIAES
Multiprocessor system-on-chip (MPSoC) has become an attractive solution for improving the performance of single chip in objective to satisfy the performance growing exponentially of the computer applications as multimedia applications. However, the communication between the different processors’ cores presents the first challenge front the high performance of MPSoC. Besides, Network on Chip (NoC) is among the most prominent solution for handling the on-chip communication. Besides, NoC potential limited by physical limitation, power consumption, latency and bandwidth in the both case: increasing data exchange or scalability of Multicores. Optical communication offers a wider bandwidth and lower power consumption, based on, a new technology named Optical Network-on-Chip (ONoC) has been introduced in MPSoC. However, ONoC components induce the crosstalk noise in the network on both forms intra/inter crosstalk. This serious problem deteriorates the quality of signals and degrades network performance. As a result, detection and monitoring the impairments becoming a challenge to keep the performance in the ONoC. In this article, we propose a new system to detect and monitor the crosstalk noise in ONoC. Particularly, we present an analytic model of intra/inter crosstalk at the optical devices. Then, we evaluate these impairments in objective to present the motivation to detect and monitor crosstalk in ONoC, in which our system has the capability to detect, to localize, and to monitor the crosstalk noise in the whole network. This system offers high reliability, scalability and efficiency with time running time less than 20 ms.
Operational transconductance amplifier-based comparator for high frequency a...IJECEIAES
Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.
IMPACT OF DEVICE PARAMETERS OF TRIPLE GATE SOI-FINFET ON THE PERFORMANCE OF C...VLSICS Design
A simulation based design evaluation is reported for SOI FinFETs at 22nm gate length. The impact of device parameters on the static power dissipation and delay of a CMOS inverter is presented. Fin dimensions such as Fin width and height are varied. For a given gate oxide thickness increasing the fin height and fin width degrades the SCEs, while improves the performance. It was found that reducing the fin thickness was beneficial in reducing the off state leakage current (IOFF), while reducing the fin height was beneficial in reducing the gate leakage current (IGATE). It was found that Static power dissipation of the inverter increases with fin height due to the increase in leakage current, whereas delay decreased with increase fin width due to higher on current. The performance of the inverter decreased with the downscaling of the gate oxide thickness due to higher gate leakage current and gate capacitance.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Six-port Interferometer for W-band Transceivers: Design and CharacterizationIJECEIAES
The study has presented an extensive analysis of an integrated millimeter wave six-port interferometer, operating over a 10 GHz band, from 80 to 90 GHz. It has covered both semi-unlicensed point-to-point links (81-86 GHz), and imaging sensor system frequencies (above 85 GHz). An in-house process is used to fabricate miniaturized hybrid millimeter wave integrated circuits on a very thin ceramic substrate. Two-port S-parameter measurements are performed on a minimum number of circuits integrated on the same die, exploiting the circuit’s physical symmetry and chosen to collect enough data for full-port characterization. Based on these measurements on an integrated prototype, a six-port circuit computer model implemented and advanced system simulations performed for circuit analysis. Interferometer performances evaluated using several methods: analysis of harmonic balance, qi points’, homodyne quadrature demodulation, and error vector modulation (EVM). The analysis showed that this circuit can directly perform, without any calibration, the demodulation of various PSK and QAM signals over the 10 GHz band, with very good results.
We present this work by two steps. In the first one, the new structure proposed of the FP-HEMTs device (Field plate High Electron Mobility Transistor) with a T-gate on an 4H-SIC substrate to optimize these electrical performances, multiple field-plates were used with aluminum oxide to split the single electric field peak into several smaller peaks, and as passivation works to reduce scaling leakage current. In the next, we include a modeling of a simulation in the Tcad-Silvaco Software for realizing the study of the influence of negative voltage applied to gate T-shaped in OFF state time and high power with ambient temperature, the performance differences between the 3FP and the SFP devices are discussed in detail.
Optimization of 14 nm double gate Bi-GFET for lower leakage currentTELKOMNIKA JOURNAL
In recent years, breakthroughs in electronics technology have resulted in upgrades in the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy contenders due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene FET with a high-k/metal gate is proposed, which is composed of hafnium dioxide (HfO2) and tungsten silicide (WSix) respectively. It is simulated and modelled using silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools, as well as the Taguchi L9 orthogonal array (OA). The threshold voltage (VTH) adjustment implant dose, VTH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters. While the VTH adjustment tilt angle and the S/D implant tilt angle have both been investigated as noise factors. When compared to the initial findings before optimization, the IOFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an IOFF of 28.564 nA/µm, which is closer to the international technology roadmap semiconductor (ITRS) 2013 target than before
Miniature design of T-Shaped frequency Reconfigurable antenna for S-Band Appl...IJECEIAES
The article presents a miniature antenna with a simple geometry and a simple approach for reconfiguration. In order to make the T-shaped antenna frequency reconfigurable, we integrated Switches in specific positions. The location of the switches is determined following a study of the distribution of the surface currents of the suggested antenna. Indeed, we found that the insertion of switches in places where the concentrations of surface currents are high is irrelevant. In fact, to redirect current flow, the PIN diodes or RF Switch must be placed in positions where the distribution of the surface currents is of low concentration. These locations facilitate the establishment of new trajectories of the flux of current. As a result, a miniature tunable antenna dimension 20mm*20mm*1.6mm printed on FR4 substrate with 4.4 permittivity and with 0.04 loss tangent, the antenna can be adopted in many communication devices in view of its small size, its low manufacturing cost and performance on frequency sweep, the antenna operates in S-Band with an acceptable band and gain. The antenna is simulated and optimized using CST Microwave Studio.
Simulation and Modeling of Silicon Based Single Electron TransistorIJECEIAES
In this work, we simulated and modeled silicon quantum dot based single electron transistor (SET). We simulated the device using non-equilibrium Green’s function (NEGF) formalism in transport direction coupled with Schrodinger equation in transverse directions. The characteristics of SET such as Coulomb blockade and Coulomb diamonds were observed. We also present a new efficient model to calculate the current voltage (IV) characteristics of the SET. The IV characteristic achieved from the model are very similar to those from simulations both in shape and magnitude. The proposed model is capable of reproducing the Coulomb diamond diagram in good agreement with the simulations. The model, which is based on transmission spectrum, is simple, efficient and provides insights on the physics of the device. The transmission spectrum at equilibrium is achieved from simulations and given as input to the model. The model then calculates the evolved transmission spectra at non-equilibrium conditions and evaluates the current using Landauers formula.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog ApplicationVLSICS Design
The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnect layers, the density of the digital as well as analog circuit will increase while intrinsic gate switching delay is reduced . We have simulated conventional and DMG MOSFET at 30nm scale using Silvaco TAD tool and obtained result. A two dimensional device simulation was carried out and observed that DMG MOSFET has a low leakage current as compared to conventional MOSFET and find suitable application in analog circuits.
Frequency Dependent Characteristics of OGMOSFETidescitation
Miniaturization in length, lowering of power,
increase in package density and sensitivity to light of
MOSFET leads it as the potential candidate for RF application.
As device is expected to operate at RF, it is essential to observe
its frequency dependent characteristics at RF. In this paper
frequency dependent electro optical characteristics of
Optically Gated Metal Oxide Semiconductor Field Effect
Transistor (OGMOSFET) are investigated numerically.
Variation of drain current-voltage characteristics, gate
capacitance and transconductance of OGMOSFET, with
varying frequency, is reported. MOSFET having length of
0.35μm is selected for investigation, which is optically gated
with incident radiations of optical power of 0.25mW and
wavelength of 800nm. MATLAB is used as computational
platform to test and tune the results. Results show that
increase in modulating frequency of OGMOSFET decreases
drain current, gate capacitance, transconductance and output
conductance. This is due to decrease in life time of inversion
charges at very high frequencies. Operating bandwidth of the
device is up to 4GHz.
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
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An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wi...IJECEIAES
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About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
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Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
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accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATION
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
DOI : 10.5121/vlsic.2013.4202 11
EVALUATION OF OPTICALLY ILLUMINATED MOSFET
CHARACTERISTICS BY TCAD SIMULATION
Prerana Jain1
and Mishra B.K2
1
SKVM’s NMIMS,Vile Parle(W),Mumbai,India
jainpnj@gmail.com
2
Principal, Thakur College of Engg and Technology, Mumbai
drbk.mishra@thakureducation.org
ABSTRACT
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
KEYWORDS
AC, DC, MOSFET, Optical Illumination, RF, Simulation.
1. INTRODUCTION
Silicon CMOS technology has matured into the nanometre regime. The feasibility of RF CMOS
circuit integration has clearly been demonstrated due to reduction in gate length [1]. This
continued transistor miniaturization is the key for sustained performance improvement. But this
aggressive scaling is also associated number of higher order effects which significantly affect the
device operations. The design of RF CMOS circuits in practical systems is a real challenge due to
the strong constraints on power consumption and noise. This leaves very little margin for
design[2]. This necessitates advances in materials, device structures and other alternatives to gain
better control over the device characteristics. In spite of superior performance of compound
semiconductors, the cost issue in silicon and conventional CMOS technology devices dominates
the market place[3][4]. One of the alternatives is use of optical port to enhance the device
characteristic. Optoelectronic and CMOS integration offers all the advantages like immunity to
electromagnetic interference, better reliability etc [5]. Properties of Silicon offer possibility of
integration on the same chip. Electronic circuits, photonic circuits and micromechanical structures
can be fabricated at low cost and high reproducibility using Silicon technologies[6][7]. Silicon
detectors are also appropriate for the visible and near infrared spectral range[8]. Several
photodetector structures like photoconductors, PIN diodes and avalanche photo diodes(APD) are
available. Photoconductors and PIN diodes have no internal gain and require high are power. The
APD’s offer high gain but suffer from high amplification noise problem. Transistor photo-
detectors offer advantage of gain in comparison with diode detector structures and hence a
MOSFET under illuminated condition is considered for analysis [9].
In a device, the I-V characteristics are important at DC while Scattering (S) parameters and
admittance (Y) parameters are important at high frequency. Y and S parameters are small signal
parameters by definition and high frequency behaviour of the device is determined around a bias
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
12
point over its operational bandwidth[10]. The S parameters are also important as they are used to
determine signal power gain and various figures of merit[11] .
Technology computer-aided design (TCAD) software is powerful tool and is widely used to
study, optimize and predict the behaviour of devices. Characterization of devices under effects of
various electrical, thermal and optical conditions is also possible [12].This paper presents analysis
of MOSFET for DC and AC under small signal condition for frequency range of 1 GHz to 10
GHz. The gain and feedback considerations are of prime importance while dealing with active
devices and hence power gain issues and their graphical displays are the starting point of analysis
and design of high frequency amplifiers. To meet this requirement the transducer gain, available
power gain, operating power gain, unilateral power gain and maximum stable power gain are
evaluated for dark and under optical radiation. Current gain analysis of the device is also
presented. Simulations are done for MOSFET under dark and optically illuminated condition. All
the calculations presented in this work have been obtained using ATLAS from SILVACO®
international unless stated otherwise. The results indicate the prospective of the device as
promising candidate for optoelectronic applications at low as well at RF frequency.
The paper is structured as follows. Section –II presents MOSFET formation in TCAD, the device
parameters, models and the methodology used for simulation under dark condition. Section III
considers MOSFET under illuminated conditions. Section IV is devoted for results and discussion
arising out of simulations.
2. THEORY
The schematic of the structure under consideration is a lightly doped drain (LDD) N channel–
MOSFET as shown in figure-1.
Figure 1. Schematic of LDD MOSFET
The conventional structure of MOSFET needs to be modified at RF to achieve the requirement of
figures of merit like low noise figure, transit frequency fT and maximum frequency of oscillation
fmax. Several modifications in the typical bulk structure have been proposed for MOSFET at RF
[4]. One of the structure is a multifinger MOSFET, which is modelled and analysed by Jain et
al.[13][14][15]. Another proposed device structures considered for present analysis is standard
LDD MOSFET.
This structure is fabricated using ATHENA which provides capability of numerical, physically-
based, two-dimensional simulation of semiconductor processing. The fabrication process in
ATHENA started with selection of wafer and completed with metallization for electrodes for a
standard LDD MOS process [16].The parameters for the device were estimated by use of
EXTRACT command. The outcome of the fabrication process simulation is the device structure
as indicated in Figure 2 and Figure 3. Figure 2 is a NMOSFET structure with materials and
junctions simulated in ATHENA. Figure 3 is the structure with net doping profile of the
NMOSFET.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
13
Figure 2. MOSFET structure with materials and junctions in TCAD
Figure 3.MOSFET structure with net doping profile.
The NMOSFET simulated uses a p type substrate of concentration of 1 x 1017
atoms/cm3
with an
ion implanted profile. The surface concentration under the channel is 3.74188 x 1016
atoms/cm3
.
The gate oxide is 10nm thick deposited by dry oxidation process. The fabricated junction depth
achieved is about 0.17µm. The source and drain structures have been processed to achieve LDD
structure. The drain and source regions have peak concentration of 5.36 x 1020
atoms/cm3
and the
lightly doped region has concentration of 2 x 1017
atoms /cm3
. The gate is made of n doped
polysilicon while the source and drain electrodes are of Aluminium. The gate length of the device
is 0.36µm. The long channel threshold voltage of the fabricated structure extracted is 0.6V. The
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
14
device fabrication is done using two dimensional simulator, and hence the device width is 1µm
unless specified.
Atlas is two and three dimensional physically based device simulator. Simulation in ATLAS
requires appropriate mesh definition. It has been demonstrated that inappropriate mesh spacing
often affects accuracy of simulation. The mesh structure of MOSFET is presented in figure 3.
Lateral spacing in the channel under the gate and source drain region is small. Similarly very
small vertical mesh spacing is selected in the channel under the gate for optimized simulation
considering speed and accuracy of simulation.
Figure 4. Mesh structure of MOSFET
The numerical simulation of MOSFET is carried out using MOS models in the ATLAS. MOS
parameter enables Shockley-Read-Hall (SRH), Fermi Statistics (FERMI), and the Lombardi
Mobility model (CVT) for transverse field dependence. The CVT model sets a general purpose
mobility model to include concentration, temperature, parallel field and transverse field effects.
The SRH model accounts for recombination effects, and uses fixed minority carrier lifetimes.
The contact statement is used to define gate electrode which is n doped poly silicon for which the
simulator assumes work function of 4.7 eV.For accurate simulation of MOS devices the interface
charge at the oxide, must be considered. This is done by setting the QF parameters for the
INTERFACE statement to a value of 3x1010
/cm2
[17]
Several numerical methods are available and can be used for calculating the solutions to
semiconductor device[18]. In the ATLAS tool a method or combination of methods is selected
depending on the equations to be solved. For the MOS structure the trend is to simulate only
majority carriers to improve speed of simulation. But this is not advised when the simulation
involves small signal ac analysis or when recombination effects are to be considered. To calculate
electrical parameters, the simulator makes use drift diffusion formulation discretized over a multi-
dimensional numerical mesh[19]. The isothermal drift diffusion model requires the solution of
three decoupled equations for potential, electron concentration, and hole concentration.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
15
This solution was achieved by use of Gummel Newton iteration scheme. This method initially
performs a GUMMEL iteration to obtain an improved initial guess for the NEWTON solution
scheme. This is slow but reliable way of obtaining solutions for any device[20]. For device
analysis under any applied bias, first initial solution must be performed with zero bias for initial
guess to determine potential and carrier concentrations from the doping profile. The simulator
solves the three basic equations using drift diffusion model evaluating for potential, electron
concentration and hole concentration with appropriate assumptions and calculates the drain
current[21].
The drain current under dark condition was evaluated by ramping the bias in small initial steps.
The ATLAS tool calculates the drain current under varying gate bias and drain bias, but the
transconductances cannot be obtained directly. TONYPLOT™ is used which is a graphical post
processing tool for use with all SILVACO simulators. The transconductances are obtained
graphically using TONYPLOT functions from the plot of drain current with respect to gate and
drain voltages by taking derivatives as per (1). The gate transconductance gm and the drain
conductance gds are given by
(1A)
(1B)
The ac analysis is performed to determine small signal characteristics of the device. Instead of
extracting a small-signal model from measurements, the complete small-signal model of the
intrinsic device is derived from physically-based simulations. Several advantages can be achieved
by use of this methodology. Errors resulting from measurements and extraction of extrinsic
component are decoupled; Non Quasi Static (NQS) effects are included by default resulting in a
good description of the electrical performance, even at frequencies beyond transition frequency
fT. Parameter extraction between any two ports of the device is easily feasible which is difficult
otherwise [22].
The ATLAS tool supports calculation of various AC parameters like Hybrid (H), Admittance(Y),
Impedance (Z), Scattering(S) etc. The gain analysis can also be done as a part of small signal
analysis. AC sinusoidal small-signal analysis should be performed after solving for a DC
condition. The full Newton method must be used for this analysis. Frequency range of interest,
device width and the method for ac analysis has to be selected. A direct parameter is included
which is robust for all range of frequencies. The gate terminal is selected as input port where ac
bias will be applied, while drain terminal is selected as output port indicating that device works in
common source configuration.
Design of high frequency circuits is often done with help of Y parameters. The device simulator
does not make a distinction between the intrinsic and parasitic parts of the device. The Y
parameters are simulated using the (2) for each DC bias condition as in[11].
jkjkjk cjgy ω+=− (2)
The yjk parameters are obtained by applying a small-signal voltage at the kth
terminal and detecting
current at the jth
terminal while all other terminals are AC grounded with following relationship
constVV
V
I
gg DS
GB
DS
mmg =
∂
∂
== ,
constVV
V
I
gg DG
DB
DS
dsmd =
∂
∂
== ,
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
16
k
j
jk
v
i
y = (3)
Admittance or impedance parameters require short circuit or open circuit condition for
measurement, which is difficult to achieve at high frequency where lead inductance and parasitic
capacitances dominate the measurement. [13].Scattering or S parameters are alternative to
admittance or impedance parameters for characterization at high frequency. S parameters are
relatively simple to measure, conceptually simple, analytically convenient and capable of
providing a great insight into measurement or design problem. The S parameters can be obtained
from Y parameters using Y to S conversion for the desired characteristics impedance as in[23,24].
The expressions for gain and unilateral figure of merit are obtained from S parameters and
reflection coefficients. The source(ГS), load(ГL), input(Гin) and output(Гout) reflection coefficients
have same definitions as in [23].
The transducer power gain GT, quantifies the gain of the amplifier placed between source and
load.
(4A)
An often employed approximation for the transducer power gain is the so-called unilateral power
gain, GTU, which neglects the feedback effect of the amplifier (S12 = 0). It is often used as a basis
to develop approximate designs for an amplifier and its input and output matching networks.
(4B)
The available power gain GA for load side matching (TL, = Tout) is defined as
(4C)
The operating power gain is the ratio of the power delivered to the load to the power supplied to
the amplifier.
(4E)
The current gain h21 of a small-signal common-source amplifier stage is defined as
11
21
2
1
1
21
Y
Y
0
I
I
=== Vh
(4F)
The calculation of current gain h21 is important as it can be used to evaluate frequency ft .
Transition frequency ft also known as unity gain frequency and is one of the figure of merit for
RF operation and indicates the frequency at which current gain h21 equals one.
3. MOSFET UNDER ILLUMINATION
When light falls on the surface of a semiconductor material, photons whose energy is in greater
than that of the band-gap energy of the semiconductor material, are absorbed. This absorption
excites an electron to jump into the conduction band and as a result a hole is left in the valence
band. These promoted electrons and valence band holes behave as free particles and travel under
intrinsic or externally-applied electric field. This continuous separation of electron-hole pairs due
2
12212211
22
21
2
)1)(1(
)1()1(
SLLS
SL
T
SSSS
S
G
ΓΓ−Γ−Γ−
Γ−Γ−
=
2
11
2
22
22
21
2
11
)1()1(
SL
SL
TU
SS
S
G
Γ−Γ−
Γ−Γ−
=
2
11
2
22
21
11(
)1(
Sout
S
A
S
S
G
Γ−Γ−
Γ−
=
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
17
to the absorption of photons enhances the conductivity. This photocurrent is directly proportional
to the intensity of the incident light.
The schematic of MOSFET under illumination is as shown in figure 5. The Aluminium electrodes
block the incident light, but the light can be absorbed at the edge of the gate electrodes. This
modifies the depletion region width of the drain(YdD) and source(YdS) region and hence the
depletion region width at gate(YdG). Silicon is sensitive to UV, visible and near-infrared regions
i.e. from around 200 nm to 1100 nm of wavelength. The peak response can be modified to suit
specific applications using special antireflection coatings and filters [9]In the present work no
such modification has been done.
Figure 5. Schematic of MOSFET under illumination.
The ATLAS framework includes LUMINOUS which is optoelectronic simulator. LUMINOUS is
a general purpose ray trace and light absorption program which calculates optical intensity
profiles within the semiconductor device, and converts these profiles into photo generation rates.
This unique coupling of tools allows simulation of electronic responses to optical signals for a
broad range of optical detectors. For the simulation purpose an optical source originates 0.5um
above the device, perpendicular to the front surface of the device is considered. The wavelength
of the source is 830nm with intensity of 0.25 mW/cm2
assumed to be incident over the MOSFET.
Presently, it has been found extensively that lot of systems for home–networking and chip–to–
chip interconnect make use of wavelength less than 850nm and hence is chosen for
simulation.[8]
The SRH, CONMOB, AUGER and FLDMOB models activated for simulation. The effect of the
transmission coefficients, reflection coefficients, along with the integrated loss due to absorption
over the ray path is considered for each ray. This computation due to the cumulative effect is
saved for each ray. The generation associated with each grid point can be calculated by
integration of the generation rate formula as in equation (5). The calculation for the generation
rate is then performed over the area of intersection between the ray and the polygon associated
with the grid point.
y
e
hc
P
G α
α
λ
η −
=
*
0 (5)
Where
P* contains the combined effects of loss due to absorption, reflections and transmissions.
ηo represents number of carrier pairs generated per photon and is measure of internal quantum
efficiency
y is a relative distance for the ray.
h is Planck’s constant
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
18
λ is the wavelength.
c is the speed of light.
α is the absorption coefficient.
The simulator calculates source photo current IS and available photocurrent IA. The source photo
current can be considered as a measure of the rate of photons incident on the device expressed as
a current density and is given by(6).
t
n
s W
hc
B
qI
λ
= (6)
The available photocurrent can be thought of as a measure of the rate of photo absorption in the
device expressed as a current density. This is less than the source photocurrent. The losses are due
to reflection and transmission of light out of the device structure.
∑ ∫=
−
=
R
i
iN
i
y
x
iiR
n
A dyePW
hc
B
qI
1 01
α
α
λ
(7)
Where
Bn is the intensity in beam number n,
λ is the source wavelength,
h is Planck's constant,
c is the speed of light,
Wt is the width of the beam including the effects of clipping,
NR is the sum is taken over the number of rays traced,
WR is the width associated with the ray,
Yi, is the integral is taken over the length, associated with the ray,
Pi accounts for the attenuation
αi is the absorption coefficient in the material that the ray is traversing,
To account for the diffraction or coherent effects beam propagation method is used.The total
current under illumination is the addition of dark current and the current due the carriers
generated due to photons.
4. RESULTS AND DISCUSSION
The device under consideration is a Silicon N-MOSFET with a LDD structure. The gate length is
0.36 µm and the width is 1µm for DC analysis. The drain current is calculated by varying gate
and drain voltage in small steps, one at a time, since the equations are solved by numerical
methods. The simulation has been performed for the device in dark condition and also under
optical illumination for incident wavelength of 830nm and beam intensity of 0.25 mW/cm2.
Figure 6A indicates plot of drain current with respect to gate voltage VG = 1 V, 2 V and 3 V in
dark condition and VD varying from 0 V to 3 V. Figure 6B is plot for similar bias conditions of
gate and drain voltage, under optical illumination. Figur e 7A and 7B are comparative plots of
drain current with respect to gate voltage VG= 1V and VG=2V in dark and illuminated condition.
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
19
Figure 6 Figure 6.2
Figure 6A:Drain current Vs Drain voltage for VG=1V, 2V and 3V in dark condition
Figure 6B: Drain current Vs Drain voltage for VG=1V, 2V and 3V under optical illumination.
Figure 7(A) Figure 7(B)
Figure 7A: Drain current Vs Drain voltage for VG= 1V in dark & under optical illumination.
Figure 7B: Drain current Vs Drain voltage for VG= 2V in dark & under optical illumination.
It can be seen that there is appreciable increase in drain current under optical illumination for
varying gate voltage VG as compared to dark condition. This is because incident radiation results
in excess electron hole pair generation in the depletion region. Because of this, photo
voltage(VOP) is developed modifying the effective gate bias to VG+VOP. This higher effective
gate bias enhances the device conductivity and hence the drain current increases.
Figure 8A and Figure 8B are plots of drain current with respect to varying gate voltage VG from 0
V to 3 V with VD=0.1 V and 1 V in dark and under optical radiation. Again here similar effect is
observed that drain current increases under light. Conventionally drain current-gate voltage
characteristics are used to evaluate threshold voltage. It can be seen that the effective threshold
voltage reduces under influence of optical radiation confirming that photovoltage develops across
the gate. The effect of optical radiation is more pronounced with increasing drain bias from 0.1 V
to 1 V for constant gate voltage because the depletion width of the MOSFET is affected by drain
bias.
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
20
Figure 8(A) Figure 8(B)
Figure 8A: Drain current Vs Gate voltage for VD= 0.1 V in dark & under optical illumination.
Figure 8B: Drain current Vs Gate voltage for VD= 1 V in dark & under optical illumination
Figure 9(A) Figure 9(B)
Figure 9A. Drain Conductance Vs Drain voltage for VG=1V in dark & under illumination.
Figure 9B. Drain Conductance Vs Drain voltage for VG= 2V in dark & under illumination.
Figure 9A and Figure 9B are plots of drain conductance under varying voltage with VG of 1 V
and 2 V.The graphs signify that drain conductance is almost constant with increasing drain
voltage. The output conductance is proportional to the drain current, and since drain current is
almost constant in saturation region of MOSFET at higher drain voltage, output conductance also
becomes independent with increasing drain bias. It can be seen that drain conductance remains
constant in dark as well as with photon flux radiation. Thus this verifies that optical flux modifies
the effective gate bias than drain bias.
Figure 10A and Figure 10B are plots of gate transconductances at fixed drain voltage of 0.1 V
and 1 V with varying gate voltage. The drain current is very small till the device enters inversion
as indicated in Figure 8 Due to this the change in device gate transconductances is seen at higher
gate voltage as seen in Figure 10. The transconductances curve reaches a peak and then remains
almost constant. This is due to influence of VGS on effective mobility. The nature of plots of
transconductance are not similar for VD= 0.1V and 1V. This is because the device is in linear
region for VD=0.1V and is in saturation for VD=1V. The transconductance is one of the very
important factors considered in circuit design as it decides transit frequency. Thus the optically
modulated device can be used to as an additional control for the device operation.
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
21
Figure 10(A) Figure 10(B)
Figure 10A: Transconductance Vs Gate voltage for VD=0.1V in dark & under illumination.
Figure 10B: Transconductance Vs Gate voltage for VD= 1V in dark & under illumination.
Figure 11. Y parameters for VG =1 V and VD =1V in dark and under optical illumination.
Figure 11 and Figure 12 are plots of Y and S parameters for the quiescent condition of VG=1 V
and VD=1 V. The width of the device is necessary parameter for ac analysis. The width of the
device under consideration for simulation is 50 µm. The frequency range for the analysis varies
from 1 GHz to 10 GHz in steps of 1 GHz. The characteristic impedance, load impedance and
source impedance for analysis are assumed to be 50 ohm for S parameter and gain calculations.
Figure 11 is a plot of parameter Y11, Y12, Y21 and Y22 under dark and illuminated situation.
Parameter Y11 and Y22 signify input and output admittance. It is seen that Y11 and Y22 are affected
by optical radiation. For the circuit operating at RF, the input and output admittances are often
12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
22
terminated at characteristics admittance by use of matching network, hence the effect on
impedance can be treated as insignificant. The parameter Y21 signifies device forward gain or
transconductance which is one of the most important parameter. The comparative plot of
parameter Y21 in dark and illuminated condition signifies that illumination enhances the
transconductance of the device, making it more suitable for RF operation. On other hand the plot
for parameter Y12 indicates that reverse gain decreases.
Figure 12: S parameters for VG and VD of 1V in dark and under optical illumination
Figure 12 is a plot of parameter S11, S12, S21 and S22 under dark and illuminated situation. S and Y
parameters for the device are inter-convertible and hence similar effect is observed for S
parameters. The S11 and S22 are related with input and output impedances and reflect similar effect
as that of Y11 and Y22. Parameter S21 which is associated with forward gain of the device increases
with light impeachment. It can be seen that device transconductance in DC or AC always
improves with optical radiation and this is reflected in parameter S21.
Figure 13 are plots of available power gain, maximum stable power gain, maximum transducer
power gain and unilateral power gain for frequency of 1 GHz to 10 GHz in dark and under optical
illumination. The plots show that there is increase in gain under optical illumination for the
frequency range under consideration. The rise of gain is consistent even with rise in frequency.
The rise in gain is seen as the forward gain S21 of the device increases, while reverse gain is
almost unaffected by optical illumination, contributing to enhancement of power gain for the
device under illuminated condition.
13. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
23
Figure 13: Power gain for VG and VD of 1V in dark and under optical illumination
Figure 14A Figure 14B
Figure 14A and 14B: Current gain for VG and VD of 1V in dark and under illumination
Figure 14A is plot of current gain for frequency of 1 GHz to 10 GHz in dark and under optical
illumination. The optically illuminated MOSFET shows advancement in the current gain of the
device, thus indicating improvement in the transition frequency of the device. Figure 14B is the
plot of current gain for frequency of 1 GHz to 40 GHz in dark and under optical illumination, to
locate transition frequency ft. The transition frequency is the frequency at which current gain is
equal to one in magnitude or 0 dB. Using interpolation technique and extract command, the
transition frequency in dark condition is found to be 13.65GHz and under optical radiation is
36.480 GHz. The substantial rise in transition frequency can be contributed to increase in drain
current and hence improvement in transconductance. Thus significant improvement seen in
14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.2, April 2013
24
transition frequency proves that optical radiation of the NMOSFET aids in rise of figure of merit
at RF.
5. CONCLUSIONS
The optical response of lightly doped drain N-channel Silicon MOSFET has been studied using
SILVACO TCAD software. The simulation been carried out using appropriate models and
suitable numerical methods for dark condition and under optical radiation. The effect of optical
illumination has been studied for dc and ac characteristics. The increase of drain current,
conductances and transconductances of the optically illuminated device is contributed to
modulation of channel conductivity due to incident photon flux.
RF performance of the device for frequency range of 1 GHz to 10 GHz is also investigated. The
variations of admittance and scattering parameters indicate that the device capacitances are
sensitive to light. This can property can be used to design optical mixers and oscillators. The
improvement in transconductance and the forward current gain signify that device can be used as
an optically controlled amplifier with low noise at RF. The effect on power gain and the transit
frequency of the device has also been studied. The simulation results indicate prominent
improvement in transit frequency and the boost in power gain of the device.
The increase in drain current, enhancement of ac and dc transconductances and the boost of
power gain at RF suggest that the device is a promising candidate for optoelectronic applications
at DC and RF. The present device structure is suitable for wavelength upto 1100 nm.
Modification of device structure is likely to extend the range of incident wavelength to 1500 nm
making it suitable for long haul communication.
ACKNOWLEDGEMENTS
The authors would like to thank Department of Electronics, North Maharashtra University,
Jalgaon, for providing usage of TCAD software by SILVACO international.
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[10] Jaejune Janguse, "Small Signal Modelling of RF CMOS," Stanford University, PhD Thesis 2004.
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[17] "ATLAS User Manual," 2010.
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Authors
Dr.B.K.Mishra was born in 5th
June 1966,in Bihar He completed his B.E. in Electronics
Engg in 1988 and M.E. in Electronics and Communication Engg in 1992. He was
awarded PhD degree from Birla Institute of Technology in 1998. He has 23years of
teaching experience. His present research interest focuses on device and structures
working at microwave frequencies and optical sensors. He is presently working as
Principal at Thakur College of Engineering and Technology, Kandiwali, Mumbai..
Prerana Jain born on 30th
Nov 1969, completed her graduation in Electronics and
Telecommunication in 1991 from Pune University. She completed her Mtech in VLSI
Technology from North Maharashtra University in 2007 and has work experience of 20
years in industry and teaching. Presently she is pursuing PhD under guidance of
Dr.B.K.Mishra. Her research area is semiconductor device modelliing for optoelectronic
applications. She is presently working as Asst Prof in North Maharashtra university,
Jalgaon.