I am Currently a Post Graduate student pursuing MTECH-VLSI degree from VIT University, Vellore.

1. RESUME
Sriram Madala
Email:ramusprofile@gmail.com
Contact No: +91-9655915754
Objectives:
Seeking a position with an organization where I can contribute my skills for organization’s success
and in the process build a career which is intellectually challenging and personally rewarding.
ACADEMIC PROFILE:
 Master of Technology (VLSI Design) – VIT University,Vellore (2014-2016)(6.3 CGPA till date) 
  Bachelor of Technology (ECE) – Prakasam Engineering College-2010-2014(69.2%) 
  Intermediate (MPC) – Board of Intermediate,A.P. (2008 - 2010) (84.1%) 
 SSC – Board of Secondary Education,A.P (2008) (76.6%) 
Strengths & Skills:
 EDA Tools : Altera Quartus –II, Modelsim, Cadence Virtuoso, Cadence ncverilog, Cadence RTL
 compiler,Cadence Encounter 
  Hardware Description Languages : Verilog 
  Software skills : C 
 Scripting Languages : Perl,TCL 
  Mathematical Tools : MATLAB,Atlanta 
 Operating system :Xilinx, Windows 8/7 
PROJECTS
B.TECH PROJECT:
Title: Traffic Signal Control using wireless Technology using Ambulance Unit
Description: Implemented a traffic controller using the pic micro controller. Two sensors are placed
on both sides of the road and it is interfaced to PIC controller. An efficient algorithm has been
implemented in PCI controller to control the traffic lights based on the availability of the traffic on
the road.
Team size: 4
M.TECH PROJECTs:
Project 1:
Title: High Speed Low Power Viterbi Decoderusing ASIC Implementation
Description:Implemented a high speed low power design using Viterbi Decoder.The Simulation is
done for the RTL Verilog code and testbench.And Implemented physical design using SoC Encounter
and showed it aspower efficient and reduced area.
Tools: Cadence ncverilog,RTL Compiler and Encounter
Team size:3

2. Project 2:
Title: 3D-IC’s withSelfHealingCapabilityforThermal Effect’s inRF Circuits usingFINfet.
Description: Implemented a design to reduce the thermal effects in 3d IC’s using FINfet.In this
we Implemented a circuit using cadence Virtuoso which is placed on a Integrated chip will start
cooling the IC When it exceedsthe given threshold voltagelevel.
Tools: Cadence Virtuoso, gpdk90nmtechnology.
Team size: 3
Project 3:
Title: Sine and Cosine Generator UsingCORDIC ALGORITHM in AsicImplementation
Description: Implemented a design to generate the sine and cosine function using Cordic Algorithm.
The Simulation is done for the RTL Verilog code and testbench.And Implemented physical design
using SoC Encounter and generated waveforms using Modelsim.
Tools: Cadence ncverilog,RTL Compiler and Encounter,Modelsim.
Team size:3
MASTER THESIS :
Title: IMPLEMENTATION OF REAL TIME MOTION PICTURE EXTRACTION USING SOBEL EDGE DETECTOR
Description:Implemented a design to detect an edge detection of an image using sobel edge
detection.this is done using matlab and synthesized by using fpga.the area efficient algorithm is
implemented.
Tools:Matlab,Quartus II.
Team size: 1
Professional Experience:
 Participated in Thrusang 12 National Technical fest organized by electronics and
 communication engineering department,and secured 2 nd prize, K L university ,Vijayawada. 
 Participated in SPORTS QUIZ Competion in VIGNAN UNIVERSITY, Guntur. 
Personal Details:
Father’s Name : M.Govardhan Rao
Date Of Birth : 10-03-1992
Mother Tongue : Telugu
Languages Known : Telugu, English, Hindi
Marital Status : Single
Permanent Address : 17-1-110.kandukur, prakasam(dist), Andhra Pradesh.
Declaration
 I hereby declare thatthe above particularsthat have beenfurnishedbyme are true to the best of my
knowledge.Iassure yougivenachance;I will execute my work to the satisfaction of my superiors. 
Place: Vellore
Date: (M.SRIRAM)