![Linear Testbench Example
//DUT (Design Under Test)
module adder(a,b,c);
//code start
input [15:0] a;
input [15:0] b;
output [16:0] c;
assign c = a + b;
endmodule
// Testbench Code
module top();
reg [15:0] a;
reg [15:0] b;
wire [16:0] c;
adder DUT(a,b,c); //DUT Instantiation
initial
begin
a = 16'h45; //apply the stimulus
b = 16'h12;
#10
$display("a=%0d,b=%0d,c=%0d",a,b,c);
end
endmodule
16](https://image.slidesharecdn.com/functionalverificationtechniquesew16session-160905204446/75/Functional-verification-techniques-EW16-session-16-2048.jpg)
Uploaded bySameh El-Ashry
Functional verification techniques EW16 session
The document discusses functional verification techniques in digital design, emphasizing the importance of detecting and correcting bugs before product delivery. It covers topics such as verification methodologies, testbench structures, and the evolution of verification roles in the industry. Additionally, it explores the career pathways for verification engineers, highlighting the increasing demand and complexity of verification processes.
More Related Content
Similar to Functional verification techniques EW16 session
Functional verification techniques EW16 session
- 1. Functional Verification Techniques SamehEl-Ashry Digital Verification Engineer ©2016 1
- 2. Agenda • Companies. • DigitalDesign Flow. • Functional Verification. • Simulation and Emulation. • Design for Test (DFT). • Power Aware Simulation. • Verification as a Career and Interesting Questions. 2
- 3. VLSI Companies inEgypt 3
- 4. Semiconductors Global Network SYSTEMCOMPANIES MEMORY IDM LOGIC IDM FOUNDRIES FABLITE FABLESS EQUIPMENT SUPPLIERS MATERIAL SUPPLIERS SOFTWARE SUPPLIERS OSAT 4
- 5. Fablite & Fabless& OSATLogic & Memory IDM & Foundries LamRESEARCH INDUSTRY ECO SYSTEM 5
- 6. Where can Ifind Digital Design 6
- 7.
- 8. Chip Design Flow 9/5/2016Verification with System 8 Design Specifications Floor Planning Technology Library SDF & Parasitics Design Entry (Schematic/HDL) Functional Verification & Power Analysis Logic & Test Synthesis Layout Design Placement & Routing Static Timing Analysis Gate Level Simulation Formal Verification Power Estimation Physical Verification Tapeout Front End Back End Verification Signoff Floor Planning & CTS 8
- 9.
- 10.
- 11. Design and SynthesisProcess Translation Mapping Verilog Code Netlist By A software tool 11
- 12. What is thedifference between verification and testing? 12
- 13. Why we needfunctional verification? ▪ To build confidence and stay in business. ▪ A primary purpose for functional verification is to detect failures so that bugs can be identified and corrected before it gets shipped to costumer. ▪ A single mistake (bug) may lead to a chip failure. ▪ Not all bugs are caused by coding errors.There are possibilities that error may in the specification itself. ▪ Sometimes miscommunications between teams may lead to wrong design. 13
- 14. History of thetestbench 14
- 15. Traditional Testbench Structure(Directed) Testbench and DUT are completely separate ( DUT is often treated as a black box). Interaction only through one (potentially large) interface. (Simple Design ok) Stimulus is applied and results are measured from external pins only For complex designs: It is virtually impossible to predict all potential input sequences How do you know when you are done? Highly non-reusable 15
- 16. Linear Testbench Example //DUT(Design Under Test) module adder(a,b,c); //code start input [15:0] a; input [15:0] b; output [16:0] c; assign c = a + b; endmodule // Testbench Code module top(); reg [15:0] a; reg [15:0] b; wire [16:0] c; adder DUT(a,b,c); //DUT Instantiation initial begin a = 16'h45; //apply the stimulus b = 16'h12; #10 $display("a=%0d,b=%0d,c=%0d",a,b,c); end endmodule 16
- 17. Advanced Testbench Structure( AVM ) • AVM combines many techniques/ideas to form a reusable verification environment. 17
- 18.
- 19. Verification is nolonger just running tests • Advanced test benches need architecture and design. • Always more to be verified in a lesser time (need innovation). • Multiple aspects of verification (Functional, Formal, Power, performance, emulation) • VIP (Verification IP) based approach. • Debug challenges. 19
- 20. OVM/ UVM VerificationMethodology 20 • Reduce testbench development and testing as it supports all the building blocks required to build a test environment. • High-level verification languages and environments such as SystemVerilog.
- 21.
- 22. Tracking the SimulationProcess 22
- 23. Hardware-Accelerated Simulation • Simulationperformance is improved by moving the time-consuming part of the design to hardware. 23
- 24. Hardware-Accelerated Simulation • Challenges –Improves speed but degrades on HW-SW communication – Abstracting HW-SW communication at transaction level rather than cycle level desired for better speeds • HW Emulation – Full mapping of HW into an emulator (array of FPGAs) – More like a real target system. Speed up possible up to 1000X simulation – Debug is a challenge with limited visibility – Usually used for HW+SW co-verification 24
- 25.
- 26. Platform definition Ansi-C DSP model SystemSW Algorithms Platform HW IP library ARM, AMBA, peripherals … IP ADRES, DFE … RTL model platform TLM model platform chip Functional MATLAB Optimized & quantized MATLAB MATLAB-over-the-air validation = functional simulation = simulation HW/SW = Real time HW demonstration = Emulation (FPGA-based) RTL refinement RTL2GDSII mapped on & simulated with platform mapped on & emulated with platform mapped on chip runs real-time ConvergensC MATLAB® to C Synthesis Digital WL Design Flow 26
- 27.
- 28.
- 29. Design For Test(DFT) Physical faults Examples 29
- 30. Power Aware Simulationand Verification 30 • As important as functionality verification – A design consuming 2x power than the budget is dead and has no workarounds. • Several low power techniques used in current SOC designs – Clock gating , power gating. • Power Analysis – Estimating a Power at RTL and Gate level simulations. – Define stimulus for peak and average power. • Power Aware Simulations – Functional correctness with power domain ON/OFF. – UPF – IEEE 1801 Standard.
- 31.
- 32. Digital and AnalogCo –Simulation 32
- 33. Verification Engineer Skills •Demanding both hardware and software skills. • Digital logic , Analog, Computer Architecture and memories. • HDLs like SystemVerilog. • Software Programming concepts such as OOP to use it in UVM. • Scripting languages for automation and regression. 33
- 34. Verification Career -Confusions 34 • Is there any career path for verification engineers ? • Can I move from Verification to Design in my career ? • Can I move from verification to Software Engineer ? • Is it possible to move from frontend to backend in my career ? • Can I become a good verification engineer if I don’t like programming ?
- 35. Verification Career -Facts 35 • Verification Engineer has a solid career path • Two decades back- Design engineer tested their designs. • Today – Verification of a design needs dedicated skills. • Verification is increasingly complex and critical. • Verification consumes majority of the project time (Avg – 70 %). • Increasing demand for verification engineers (12% compound annual growth rate as per industry survey). • Verification engineers are involved in project from early stage of the design.
- 36. References 36 • ASIC DigitalDesign Flow from concept to IC , Amr lofty, Intel. • Electronic Systems Design from Specifications to production, Khaled Salah, Mentor-graphics. • Verification Engineer - Opportunities and Career Path, Ramdas M, AppliedMicro.
- 37. Presented by SamehEl-Ashry samehelashry@ieee.org https://eg.linkedin.com/pub/sameh-el-ashry/3b/560/22b 37