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Problem :
For multi-clock synchronous circuit,
model-checking verification needs to specify the
relations between clocks.
ex. at least 2 edges of clock B occur in a period of clock A.
Because the state space explodes without the
relations.
Aim :
Formal verification without the relations between clocks.
We adopt theorem-proving method.
Theorem-proving Verification of Multi-clock
Synchronous Circuits on Multimodal Logic
Shunji Nishimura
Method :
2
comb.
circuit
0
⓪ st0 = f0 (in, st0, st1)
① st1 = f1 (in, st0, st1)
○ st = f (in, st)
in temporal logic
in
1
in multimodal logic
this study …previous …
st0
single clock multi-clock
st1
comb.
circuit
in
st
NEXT
operator
Theorem-proving Verification of Multi-clock
Synchronous Circuits on Multimodal Logic
Theorem-proving Verification of Multi-clock
Synchronous Circuits on Multimodal Logic
3
clk0
clk1
sel1
en0
en1
out
derives □(sel1 = 0) ⇒ ◇□(out = clk0).
This means ”when sel1 is always 0, clk0 will come
out eventually.”
Verification ex. : clock selector
□ : GLOBALLY
◇ : FUTURE

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Theorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic

  • 1. 1 Problem : For multi-clock synchronous circuit, model-checking verification needs to specify the relations between clocks. ex. at least 2 edges of clock B occur in a period of clock A. Because the state space explodes without the relations. Aim : Formal verification without the relations between clocks. We adopt theorem-proving method. Theorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic Shunji Nishimura
  • 2. Method : 2 comb. circuit 0 ⓪ st0 = f0 (in, st0, st1) ① st1 = f1 (in, st0, st1) ○ st = f (in, st) in temporal logic in 1 in multimodal logic this study …previous … st0 single clock multi-clock st1 comb. circuit in st NEXT operator Theorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic
  • 3. Theorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic 3 clk0 clk1 sel1 en0 en1 out derives □(sel1 = 0) ⇒ ◇□(out = clk0). This means ”when sel1 is always 0, clk0 will come out eventually.” Verification ex. : clock selector □ : GLOBALLY ◇ : FUTURE

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