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The document outlines the syllabus for the COMSM0115 Design Verification course which aims to familiarize students with routine design verification tasks and techniques, covering topics like verification planning, coverage metrics, constrained random stimulus generation, assertion-based verification, and formal verification methods. It also describes opportunities for undergraduate and graduate student projects as well as PhD research collaborating with local industry on topics like coverage-directed test generation, formal specification, and verification methodology development.
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The document discusses methodologies for improving verification efficiency at Cisco. It advocates separating testbench creation into three stages: component design, testbench integration, and testcase creation. It also recommends using standardized methodologies like testflow to synchronize component behavior, reusing unit-level component models and checkers, linking transactions between checkers, and generating common testbench infrastructure from templates to reduce duplication of effort. The key is pushing reusable behavior into components and standardizing common elements to maximize efficiency.
Stinson post si and verification
This document discusses the importance of pre-silicon verification for post-silicon validation. It notes that post-silicon validation schedules are growing due to increasing design complexity, while pre-silicon verification investment and methodologies have not kept pace. The document highlights mixed-signal verification, power-on/reset verification, and design-for-testability verification as key focus areas needed to improve pre-silicon verification and enable faster post-silicon validation. It provides examples of mixed-signal and power-on bugs that were found post-silicon due to insufficient pre-silicon verification of these areas. The document argues that pre-silicon verification must move beyond just functional verification and own mixed-signal effects
Shultz dallas q108
This document discusses challenges in low-power design and verification. It addresses why low-power is now a priority given trends in mobile applications. Key challenges include increased leakage due to process scaling, accounting for active leakage, and handling process variations. The document also discusses low-power design methodologies, including multiple power domains, voltage scaling, and clock gating. Verification challenges are presented, such as needing good test patterns and coordination across design domains. Overall power analysis is more complex than timing analysis due to its pattern dependence and need to optimize for performance per watt.
Shreeve dv club_ams
Verilog-AMS allows for mixed-signal modeling and simulation in a single language. It provides benefits like simplified mixed-signal modeling, decreased simulation time, and improved mixed-signal verification. Previous solutions involved using two simulators or approximating analog circuits, which caused issues like slow simulation and lack of analog results. Verilog-AMS uses constructs from Verilog and Verilog-A to model both analog and digital content together. This avoids issues with interface elements between domains.
Sharam salamian
This document discusses the verification of Intel's Atom processor. It describes the key verification challenges, methodology used, and results. The main challenges were verifying a new microarchitecture with aggressive schedules and limited resources. The methodology involved cluster-level validation, functional coverage, architectural validation, and formal verification. Metrics like coverage, bug rates, and a "health of model" indicator were used. The results showed a successful pre-silicon verification with few escapes and debug/survivability features working as intended. Key learnings included the importance of keeping the full-chip design healthy early and putting equal focus on testability features.
Schulz sv q2_2009
The document discusses verification strategies based on Sun Tzu's classic book "The Art of War". Some key points:
1. Sun Tzu emphasized understanding the objective conditions and subjective opinions of competitors to determine strategic positioning. This relates to verification where it is important to understand the design and "Murphy the Designer".
2. Sun Tzu's 13 chapters provide guidance on tactics like laying plans, attacking weaknesses, maneuvering, and using intelligence sources. These lessons can help verification engineers successfully navigate different stages of a competitive campaign against bugs and errors.
3. Effective verification requires knowing the design, understanding one's own verification process, preparing appropriate tools, and using feedback to improve. Coverage metrics alone do
Schulz dallas q1_2008
Here are the key challenges faced in low power design without a common power format:
1. Domain definitions, level shifters, isolation cells, and other low power techniques are specified differently in each tool using tool-specific commands files and languages. This makes cross-tool consistency and validation difficult.
2. Power functionality cannot be easily verified at the RTL level without changing the RTL code, since power domains and low power techniques are not represented. This limits verification coverage.
3. Iteration between design creation and verification is difficult, since changes to the low power implementation require updates to multiple tool-specific specification files rather than a single cross-tool definition. This impacts design schedule and risks inconsistencies.
4.
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Kersten eder q4_2008_bristol
- 1. Design Verification Research and Teaching Kerstin Eder Design Automation and Verification Department of COMPUTER SCIENCE
- 2. COMSM0115: Design Verification Aim: “To familiarize students with the routine tasks and the latest techniques in design verification, and to give them the theoretical background plus some of the practical skills expected from a professional design verification engineer.”
- 3. Syllabus Introduction to HW Design Flow and Functional Verification Verification Flow and Tools Traditional simulation-based Verification: basic testbench architecture, directed testing, driving & checking tutorial Verification Planning Process Coverage: metrics: structural, functional, analysis, need to combine metrics Automation for Verification: constrained pseudo-random stimulus generation self-checking testbenches Coverage Driven Verification Assertion Based Verification Functional Formal Verification
- 4. Design Verification Research Exploiting state-of-the-art techniques from other areas of CS to advance Design Verification Formal specification, refinement, derivation and verification by mathematical proof Reassessing processor design decisions – impact on verification Coverage Directed Test Generation: Formal approaches Feedback-based approaches – machine learning Methodology development for coverage balancing Industrial Collaboration with: IBM Research Labs in Haifa (Israel) Local semiconductor industry: STM, Infineon, Clearspeed, Xmos, BRCM, Icera etc EDA: Cadence and Mentor Graphics
- 5. Opportunities to get involved Undergraduate student projects – Final year project BSc: 400h (40 CP), part-time, October to May – Final year project MEng: 400h (40 CP), full-time, February to May MSc student projects – 200h (20 CP), part-time, February to May – 600h (60 CP), full-time, June to September PhD – 3 years 6 months full-time research EngD – 4 years full-time research and professional training – 75% of time spent in industry – Portfolio-based Get involved: Contact Kerstin.Eder@bristol.ac.uk to explore collaboration opportunities
- 6. Ramaram Naresh (MSc AMSE student at University of Bristol) Email ID : nr8627@bristol.ac.uk Experience : Worked as Member Technical staff in GD Micro Systems Pvt Ltd for THREE plus years. Interested in : SOC Verification, Analog & Mixed signal design. Domain Expertise : SOC Verification, Reference Verification Methodology & AMBA AHB/APB bus systems. Projects Done : Dual core 2 million gate count System-on-chip using 90nm technology, AHB Verification IP using VERA. Role : Verification of chip at block, system and production level. Languages : C, C++, Verilog, Unix, Perl.