This document describes an FPGA UART transmitter project that requires a baud rate generator to set the communication rate between the FPGA and Spartan 3E boards, a finite state machine to control the program flow by loading and transmitting data, and a data path to perform operations like loading and transmitting data under the control of the finite state machine.

1. FPGA PROJECT
FPGA BASED UART TRANSMITTER

2. DESIGN NEEDS
• BAUD RATE GENERATOR
• FSM (CONTROLS THE PROGRAM FLOW)
• DATA PATH (PERFORMS DIFFERENT OPERATIONS UNDER CONTROL OF FSM)

3. BAUD RATE GENERATOR
• AS FPGA KIT HAS CLOCK OF 50 MHZ SO FOR COMMUNICATION BETWEEN FPGA AND
SPARTAN 3E WE HAVE TO SET FIRST THE BAUD RATE FOR COMMUNICATION.
ACCORDING TO THE FORMULA
BAUD RATE COUNTER=CLOCK FREQUENCY OF FPGA/DESIRED BAUD RATE
BAUD RATE COUNTER=50MHZ/115200=434

4. FSM
S2
LOAD=0
LOADDATA=0
S0
LOAD=1
LOADDATA=0
S1
LOAD=0
LOADDATA=1
Start=0
Bit_counter=4’d10

5. DATA PATH

6. SIMULATION RESULT IN MODEL SIM