In this project, students learn how to design the LMS algorithm using VHDL. The adaptive noise cancellation problem is used as a test application. Hardware drivers for the SSM2603 codec are provided, along with Matlab codes used to emulate the acoustic environment and generate audio files.

1. University of Quebec–Trois-Rivières
Department of Electrical and Computer Engineering
Course GEI-1064: VLSI Design
FPGA implementation of an LMS-based adaptive noise
canceller (ANC)
Prepared by: Hocine MERABTI, F. NOUGAROU and D. MASSICOTTE
Fall 2016 1

2. Skills learned in the course
 Introduction to the least mean squares (LMS) algorithm
 Hardware modeling of the LMS using VHDL
 Design verification using behavioral simulation
 Synthesis, place & route and resource utilization report generation
 Design verification using post-route simulation
 Bitstream generation and FPGA implementation of an adaptive noise canceller
(ANC)
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3. Introduction to the adaptive noise cancellation problem
(Helicopter Cockpit)
3Figure 1: ANC application example (images from Google Images)
Main acoustic noise sources
• Blades noise
• Engine noise

4. Mathematical modeling of the ANC problem
4Figure 2: ANC system

Adaptive
Filter (FIR-LMS)
+
-
ANC Block
ˆ( ) ( ) ( )y n h n n 
Filter output
( )y n
Primary input
( ) ( ) ( )s n h n n 
Reference input
( )n
Error ( )e n
System output
( )e nPilot
Speech s(n)
Blades noise
η (n)
ˆ( ) ( ) ( ) ( ) ( ) ( )
ˆIf ( ) ( ), we get:
( ) ( )
e n s n h n n h n n
h n h n
e n s n
     


 2
LMS: min ( )E e n
ˆ( )h n
Acoustic path
Matlab FPGA

5. Introduction to the Zybo Zync-7000
Figure 3: Zybo Zync-7000 [1]
5

6. Introduction to the Zybo Zync-7000
Audio codec features (SSM2603)
Table 2: SSM2603-Zync interface [1]
Parameter Value
Protocols I2C,I2S
Headphone out Stereo
Line out Stereo
Line in Stereo
Mic in Mono
Sampling frequency 48 Khz
Word-length 16- 32bits
Table 1: Analog Devices SSM2603 features [2]
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7. SSM2603 configuration sequence (I2C)
7
Start
Power management
<0x0C,0x72>
Left-chan. ADC volume
<0x00,0x17>
Right-chan. ADC volume
<0x01,0x17>
Analog audio path
<0x08,0x10>
Digital audio path
<0x0A,0x00>
Digital audio I/F
<0x0E,0x42>
Sampling rate
<0x10,0x00>
Active
<0x12,0x01>
Power management
<0x0C,0x60>
End

8. Architecture of the LMS based ANC
Figure 4: Architecture of the ANC system
8
3-Taps
FIR-LMS
Hardware
driver
(I2C, I2S)
SSM2603
Headphone
Line in
LMS_clk (1)CLK (1)
LMS_reset (1)RST (1)
L_bus (18)
R_bus (18)
Error (16)
ANC On/Off
FPGA
LMS_pure_noise (16)Yb (16)
LMS_corrupted_speech (16)Ybin (16)

9. Filtering system architecture
Filter integration in the project (Main.vhd)
 Add the source files of your 3-taps FIR-LMS to project « ANC-LMS » (after performing
ModelSim-Matlab design verification)
 Declare the FIR-LMS component in the source file « Main.vhd »
 Perform instantiation of the FIR-LMS component using the following mapping:
(make sure the Reset signal of your components is active high)
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10. Filtering system architecture
FPGA pins assignment
The assignment of the FPGA pins to the
design elements is defined in the user
constraints file (.xdc). The placement
constraints « set_property » and
« get_ports » are used for this purpose
(figure 5).
The electrical interface of the FPGA’s I/O
with the board peripherals can be found in
the manufacturer data sheet (atlys_sch.pdf). Figure 5: Pins assignment in the constraints file
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11. FPGA design implementation
 Run « Synthesize ». Make sure that all the design signals are interconnected correctly by
visualising the RTL schematic
 Run « Implement Design » and « Generate Programming File »
 Power-up and connect the Zybo board to your PC (using USB PROG interface)
 Run the Harware Manager tool
1) Open target
2) Program device
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12. FPGA design implementation
 Disable ANC (audio loopback) using « SW1 » (LED1 "off")
 Play soundtrack « Audio_combined.wav » (Generated with Matlab. Right
channel: noisy speech, Left channel: pure noise)
 Enable ANC (audio goes through FIR-LMS bloc) using « SW1 » (LED1 "on")
 Play the soundtrack again« Audio_combined.wav »
 Enjoy!
Design validation (figure 6)
12

13. FPGA design implementation
Figure 6: Test and validation
Line in
Headphone
Power
Switch
USB PROG
SW7
13

14. References
[1] https://reference.digilentinc.com/_media/zybo:zybo_rm.pdf
[2] http://www.analog.com/media/en/technical-documentation/data-
sheets/SSM2603.pdf
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