This document summarizes research on automated synthesis and modeling of analog and mixed-signal systems. It discusses using heuristic optimization algorithms, integer programming, and synthesis from VHDL-AMS specifications to synthesize analog and mixed-signal circuits. It also covers automated modeling techniques for circuits including modeling process variations, symbolic methods, statistical modeling, compiled code simulation, and neural networks. Specific applications discussed include delta-sigma modulator topologies, reconfigurable delta-sigma modulators, and algorithms for analog filter synthesis.

1. Automated Synthesis and Modeling of
Analog and Mixed-Signal Systems
Alex Doboli, PhD
Associate Professor
Department of Electrical and Computer Engineering
State University of New York, Stony Brook, NY 11794
Email: adoboli@ece.sunysb.edu

2. • Analog and mixed-signal synthesis:
– Heuristic optimization algorithms (many kinds)
– Integer linear and nonlinear programming
– Synthesis from VHDL-AMS
• Automated modeling for design:
– Automated modeling of analog circuits and systems
– Modeling of process parameter variations
– Linear and nonlinear symbolic methods
– Statistical modeling
– Compiled code simulation
– Neural networks and PWL modeling
Mixed-Domain Embedded Systems Laboratory
(http://www.ece.sunysb.edu/~vsdlab)

3. • Synthesis of analog and mixed-signal circuits with
high degree of innovation:
– Understand the difference between human designed circuits
and automatically synthesized circuits
– Understand the level of innovation of new design solutions
– Representation of design knowledge for innovation:
• Classification scheme to show commonalities and
differences
• Management and reuse of existing IP
– Synthesis method using the representation:
• Process more similar to human design process (i.e.
combination of existing design features)
Mixed-Domain Embedded Systems Laboratory
(http://www.ece.sunysb.edu/~vsdlab)

4. VHDL-AMS
specifications:
entity aaa is
…
end entity;
Topology generation and
system architecture selection:
integ
DAC
integ
m
m
m
Constraint transformation,
floorplanning and global routing
Obtained
performance
Circuit and
interconnect
models
Performance
evaluation
(simulation)
Performance
evaluation
Automated synthesis of analog and mixed-
signal systems

5. Application-specific DS modulator topologies
H. Tang, A. Doboli, "High-Level Synthesis of Delta-Sigma
Modulators Optimized for Complexity, Sensitivity and Power
Consumption", IEEE Transactions on CAD of Integrated
Circuits and Systems, Vol. 25, No. 3, pp. 597-607, 2006.
• Automatically synthesize DS modulator topologies optimized for a
given application (specification)
• Novelty:
• Synthesis methods for topology (no general method available)
• New theoretical formulation
• Advantages:
• Global optimal solution is guaranteed (new topologies
invented)
• The methodology is scalable
• The methodology could be fully automated

6. Generic topology for 3rd order modulator
Chain of Integrators with
Feedforward Summation
Chain of Integrators with Distributed
Feedback, Distributed Feedforward
and Local Feedback
Chain of Integrators
with Distributed Feedback
Generic topology

7. Optimal topology
Minimum signal path (topology not unique)
9 signal paths 9 signal paths

8. Optimal topology
Minimum sensitivity
Sensitivity cost function values are 1.723 and 2.250
respectively, with all (good case)
L. Huelsman, “Active and Passive Analog Filter Design”, McGraw Hill, 1993
0
.
1
, 
j
i
j
i
q
x
P
x S
S

9. Topology from Toolbox
R. Schreier, “The Delta-Sigma Toolbox 6.0”,
www.mathworks.com/matlabcentral/fileexchange, Nov 2003.
0
.
1
, 3
34
3
3

q
t
q
a S
S
Sensitivity cost function values is 4.454, with some
terms larger than 1.0, e.g.

10. Synthesis of Reconfigurable DS Modulators
Y. Wei, H. Tang, A. Doboli, "Systematic Methodology for
Designing Reconfigurable Delta Sigma Modulator Topologies for
Multimode Communication Systems", invited paper, IEEE
Transactions on CADICS, Vol. 26, No. 3, March 2007.
Mode DR (bits/dB) Bandwidth
UMTS 11.5/70 1.92MHz
CDMA2000 13/80 615kHz
GSM 15/90 190kHz
EDGE 14.5/87 270kHz
• Design
Specifications
A cell phone chip
works for CDMA,
GSM, UMTS … …

11. Reconfigurable DS modulator topologies
Topology opt1

12. Experiments
• Compare the triple-mode modulator with three single-
mode modulators obtained with DS toolbox
– Design effort can be less than 1/3
– Complexity can be as less as 40%
– Power saving can be as large as 24.2%
– More robust to circuit nonidealities

13. SNR degradation due to circuit noise
Improvement as compared to the state-of-art design:
3dB for the case of -60dB noise level
5dB for the case of -50dB noise level

14. Experiments

15. Algorithms for Analog Synthesis
3rd order elliptic
lowpass filter
Synthesis problem:
– Find circuit constraints and system
parameters so that functionality is
achieved, and multiple performance
attributes are optimized
H. Tang, H. Zhang, A. Doboli, "Refinement based Synthesis
of Continuous-Time Analog Filters Through Successive Domain
Pruning, Plateau Search and Adaptive Sampling",
IEEE Transactions on CAD of Integrated Circuits and Systems,
Vol. 25, No. 8, pp. 1421-1440, 2006.

16. Slow convergence
• Plot 1: smaller variable ranges is good
• Plot 2: different types of regions: convex
regions mixed with plateaus
• Plot 3: adaptive sampling for buried optima
oscillation
Cost=3000
Small sampling steps
(5,000,6hours)
Plot 3
Plot 1
Large sampling steps
(20,20 sec)
Plot 2
Cost=6
plateau
Convex region

17. Experiments
NeoCircuit Circuit Explorer Plateau search
Small
ranges
Large
ranges Time
(hrs)
Small
ranges
Large
ranges Time
(hrs)
Large
ranges Time
(hrs)
Total # Separ. Total #Separ. Total # Separ. Total# Separ. Total # Separ.
3rd
(12M) 23 3 13 3 1.6 49 5 28 1 6.3 40 11 6.3
3rd
(100M) 17 3 7 1 1.6 16 2 0 0 6.3 11 5 6.3
4th
38 7 18 3 6.0 22 3 12 3 15 27 11 15
5th
80 3 0 0 18 47 1 2 1 19 20 2 19

18. Experiments (DS ADC)
Very
good
good fair Time
(hrs)
Very
good
good fair Time
(hrs)
3rd
order
SD
0 1 2 51 1 3 7 87
4th
order
SD
0 1 3 53 2 5 11 98
SA Plateau search

19. Automated Macromodeling
• Produced macromodels:
– Structural
– No feedback dependencies (decoupled)
– Symbolically characterized nonlinear current sources
– Extensible, accuracy is controllable
– Insight into circuit
– Reusable
Y. Wei, A. Doboli, "Structural Macromodeling of Analog
Circuits through Model Decoupling and Transformation",
IEEE Transactions on CADICS, Vol. 27, No. 4, April 2008.

20. f(vin)
vin vout
Black-box macromodel
Circuit netlist Structural nonlinear macromodel
(R2,C2)
Automated Macromodeling

21. Circuit netlist
Automated Macromodeling

22. Comparison of HD2, HD3
Automated Macromodeling

23. Automated Macromodeling

24. Automated Macromodeling

25. Automated Macromodeling

26. Automated Macromodeling

27. Process Variation Modeling
H. Zhang, A. Doboli, "A Scalable Sigma-Space Based
Methodology for Modeling Process Parameter Variations in
Analog Circuits", Microelectronics Journal, Elsevier,
February 2009.

28. Index
SA ALAMO
Iref Iout DI Iref Iout DI
1 0.0156 0.0398 0.0366 0.0270 0.0357 0.0362
2 0.0159 0.0391 0.0358 0.0273 0.0351 0.0363
3 0.0160 0.0393 0.0362 0.0273 0.0353 0.0365
4 0.0277 0.0208 0.0364 0.0276 0.0346 0.0361
5 0.0273 0.0208 0.0356 0.0272 0.0353 0.0363
6 0.0274 0.0211 0.0360 0.0274 0.0353 0.0365
The limitation of the SA Method
“Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits”,
Christopher Michael and Mohammed Ismail, Kluwer Academic Publishers, 1993
   number
normal
unit
:
,
T
2
1
2
1 n
N
Ni
i
i
i R
R
R
R
a
a
a
P 



29. Process Variation Modeling Method

30. Experimental Results

31. Experimental Results

32. Modeling and Fast Simulation of Nonlinear Systems
• At the system-level, the method uses symbolic descriptions of ADCs
• Building blocks are macromodels, which include circuit non-idealities and
nonlinear behavior.
• Non-linear parameters are expressed using PWL models, which are
created automatically through model extraction from trained neural
networks (NN) .
• Method is more accurate than simulation of behavioral models
• Method is significantly faster than numerical simulation (two orders of
magnitude)
• Accuracy is not traded-off for speed
• Simulator code can be optimized to avoid convergence problems
H. Zhang, S. Doboli, H. Tang, A. Doboli, "Compiled Code
Simulation of Analog and Mixed-Signal Systems Using Piecewise
Linear Modeling of Nonlinear Parameters", Integration the VLSI
Journal, Elsevier, Vol. 40, No. 3, pp. 193-209, 2007.

33. Simulation Methodology - overview
Topology
Compiled-code simulator
GIT
library
Lazy generation of
symbolic expression
Model abstraction
Level selection
Connection pattern
recognition
Modified nodal
analysis
PWL MM
library
DDDs APTs
PWL segment control
flow generation
Code generation
Code optimization
Terminal block analysis Middle block analysis
Code generation and optimization

34. Structure of 3rd-order Single-loop S-D Modulator

35. Simulation Results
SD ADC
order
Spectre +
VerilogXL(s)
Symbolic (s) Speed-up
1 507.1 3.5 144.88
2 533.9 5.88 90.79
3 852.3 8.24 103.43
4 1284.9 10.69 120.19
5 1752.0 12.91 135.70
Comment: Because of the extreme values of some parameters, we had
severe convergence problems in Cadence Mixed-Signal Simulation
Environment (Spectre + Verilog A).

36. • Automated synthesis of analog and mixed-signal synthesis:
– Heuristic optimization algorithms (all kinds)
– Integer linear and nonlinear programming
– Stochastic methods (Markov chains, dynamic programming)
• Automated modeling for design:
– Automated modeling of analog circuits and systems
– Modeling of process parameter variations
– Linear and nonlinear symbolic methods
– Statistical modeling
– Compiled code simulation
– Neural networks and PWL modeling
Conclusions

37. Towards Creative Analog Synthesis:
A Symbolic Representation for Exploring
Circuit Operation Principles
Cristian Ferent and Alex Doboli
cferent@ece.sunysb.edu

38. Motivation, Goals, and Contributions
 Systematically characterize a collection of designs:
 Implement performance specific circuit models
 Highlight common & different features between circuits
 Identify advantages & limitations of a circuit compared to others
 Derive conditions under which design alternatives exhibit
similar performance

39. Motivation, Goals, and Contributions (II)
 Model to characterize transconductor linearity
 Illustrate mechanisms which can enhance circuit performance:
extended operating range and/or device non-linearity compensation

40. Motivation, Goals, and Contributions (III)
 Automatically produce circuit classification schemes:
 Build a model to express main similarities & differences between a set
of circuits implementing the same functionality
 Based on topological structures of features that influence the
performance of a design
 Produce compact classification – minimum of separation criteria

41. Problem Description: concept representation
Coupling
between nodes
Distinguishing
criteria curves
Circuit node
Classification
along curve D1
Features
related to
performance
Similar node
features
C. Ferent, A. Doboli, "A Symbolic Technique for Automated
Characterization of the Uniqueness and Similarity of Analog
Circuit Design Features", DATE 2011

42. Proposed Method: automated generation of
classification schemes
 Produce the separation criteria for a given performance
 Determine best separation criteria
 Construct hierarchical classification scheme

43. Algorithm Details
1) Build performance-based circuit models
2) Group nodes with similar behavior:
 Minimize total number of matched groups (N )
 Minimize matching error within groups of nodes
 Identify constraints under which matching is valid

44. Algorithm Details (II)
3) Sort matched groups:
 Signal path tracing and model decoupling algorithms
4) Use entropy to rank similarities and differences between
circuits:
 N – number of circuits represented in cluster Ck
 pi – probability a circuit from cluster Ck is associated with
matched group Gj
5) Produce hierarchy with maximum matching at higher levels

45. AC Domain Model Matching:
amplifier circuits hierarchical classification
Increasing
entropy
value
Similar
behavior
Different
behavior
Common
structures
Different
structures

46. Classification correlation with performance
Also identify number of terms that differ between node structures
Indication of topology’s flexibility to satisfy performance
(e.g. setting pole and zero positions)

47. Transconductor Linearity Models
Extend range
Correct linearity

48. Linearity Model Matching:
transconductors hierarchical classification
Common
structures
Different
structures
Identical
Processing
Path
Additional
Processing

49. Linearity Model Matching: (II)
transconductors hierarchical classification
Identical
Control
Path
Additional
Control
Voltages
Additional
Control

50. Current Developments
 Apply the proposed
methodology for a set of 10
state-of-the-art amplifier designs
 Derive topological and
performance classification
schemes

51. Conclusions
 Develop new symbolic technique for automated generation
of circuit classification schemes
 Produce the set of separation criteria
 Based on performance specific circuit models
 Sort separation criteria based on their capability to
distinguish between different structures
 Proposed metric based on entropy
 Build hierarchical classification
 Highlight similarities and differences with impact on performance
 Offer insight through symbolic expressions
 Identify common & dissimilar circuit node structures
 Relate symbolic differences and similarities to performance
attributes
 Suggest design’s flexibility for achieving certain performance