IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
Abstract The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2 in 0.13μm CMOS ,which gives the best figure of merit and performance. Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
A Novel Architecture for Different DSP Applications Using Field Programmable ...journal ijme
This paper presents a reconfigurable processor for different digital signal processing applications. The performance of the proposed architecture has been evaluated by taking different dsp applications like Low pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for dsp applications. This paper investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for different dsp applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.
A Simulation of Wideband CDMA System on Digital Up/Down ConvertersEditor IJMTER
In this paper, I present FPGA implementation of a digital down converter (DDC) and
digital up converter (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in
nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx
System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the
circuits are verified on the Spartan - 3 FPGA
Connecting electrical appliances to a Home Network using low-cost Power-Line ...Valerio Aisa
This paper discusses a novel “proxy” approach, aimed at connecting digital appliances to a home network and based on ultra low cost, narrow band power-line transmission (ULP). Bidirectional point-to-point communication is carried out on power-supply wire between the appliance itself and the outlet.
Here a dedicated device embeds both network management functions and ULP communication, acting as a proxy between the appliance and the home network. Through this approach, white goods and any other electrical household appliance can be connected to the home network at extremely low communication cost and without issues related to standard protocol selection. In this summary, after a brief introduction, the network structure is presented. Next, physical layer of ULP protocol is discussed and a prototypal HW implementation is presented. Finally, experimental ULP performances are discussed and conclusions are drawn. (Presented at ISPLC 2005)
Compact Power Divider Integrated with Coupler and Microstrip Cavity Filter fo...TELKOMNIKA JOURNAL
This paper present the compact power divider integrated with coupler and microstrip cavity filter
for x-band surveillance radar system. These modules consist of several devices (splitter, filter and coupler)
it is integrated in a single module aims to reduce the loss in the joint connectors. The bandpass filter is use
microstrip cavity filter for operating on X-Band Frequency and deployed on RT/duroid 5880. The power
divider and coupler is designed using quarter wavelength transformer. A theoretical analytical circuit model
will be presented, from the theoretical model; a compact integrated module will be designed and simulated.
The proposed compact integrated module is small in dimension and performs a compact size. The
compact integrated devices design on X-Band frequency is simulated and the result is presented.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
Abstract The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2 in 0.13μm CMOS ,which gives the best figure of merit and performance. Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
A Novel Architecture for Different DSP Applications Using Field Programmable ...journal ijme
This paper presents a reconfigurable processor for different digital signal processing applications. The performance of the proposed architecture has been evaluated by taking different dsp applications like Low pass filter, high pass filter, finite impulse response (FIR) filter and FFT module. We designed the architecture of the processor and realizing the architecture using adder, multiplier, delay unit and validate it in the FPGA, which show that the hardware scheme is feasible for practical application. The experimental results clearly reveal the novelty of the architecture for dsp applications. This paper investigates the potential use of FPGAs for implementing efficient “Reconfigurable Processor” for different dsp applications. The proposed processor is based on parallel re-configurable which is implemented on FPGA. FPGAs have become an important component for implementing these functions with respect to cost, performance and flexibility. The general purpose SPARTAN 3AN FPGA kit has been employed for developing reconfigurable processor, with all the coding done using the hardware description language VERILOG.
A Simulation of Wideband CDMA System on Digital Up/Down ConvertersEditor IJMTER
In this paper, I present FPGA implementation of a digital down converter (DDC) and
digital up converter (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in
nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx
System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the
circuits are verified on the Spartan - 3 FPGA
Connecting electrical appliances to a Home Network using low-cost Power-Line ...Valerio Aisa
This paper discusses a novel “proxy” approach, aimed at connecting digital appliances to a home network and based on ultra low cost, narrow band power-line transmission (ULP). Bidirectional point-to-point communication is carried out on power-supply wire between the appliance itself and the outlet.
Here a dedicated device embeds both network management functions and ULP communication, acting as a proxy between the appliance and the home network. Through this approach, white goods and any other electrical household appliance can be connected to the home network at extremely low communication cost and without issues related to standard protocol selection. In this summary, after a brief introduction, the network structure is presented. Next, physical layer of ULP protocol is discussed and a prototypal HW implementation is presented. Finally, experimental ULP performances are discussed and conclusions are drawn. (Presented at ISPLC 2005)
Compact Power Divider Integrated with Coupler and Microstrip Cavity Filter fo...TELKOMNIKA JOURNAL
This paper present the compact power divider integrated with coupler and microstrip cavity filter
for x-band surveillance radar system. These modules consist of several devices (splitter, filter and coupler)
it is integrated in a single module aims to reduce the loss in the joint connectors. The bandpass filter is use
microstrip cavity filter for operating on X-Band Frequency and deployed on RT/duroid 5880. The power
divider and coupler is designed using quarter wavelength transformer. A theoretical analytical circuit model
will be presented, from the theoretical model; a compact integrated module will be designed and simulated.
The proposed compact integrated module is small in dimension and performs a compact size. The
compact integrated devices design on X-Band frequency is simulated and the result is presented.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Implementation Cost Analysis of the Interpolator for the Wimax Technologyiosrjce
The design of the multirate filter (programmable) has been proposed which can be used in digital
transceivers that meets 802.16d/e (wimax) standard in the wireless communication system. Wimax is a
technology emerging in the wireless communication system in order to increase the broadband wireless internet
access. As there is wide spread need of the digital representation of the signal for the transmission and storage
which create the challenges in DSP [1]. In this paper, analysis of the implementation cost of interpolator for the
wimax technology, and cost of interpolator is analyzed on the basis of number of adders and multiplier. The
Filters are designed using the FDA (filters design and analysis) tool in MATLAB.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Sentence level sentiment polarity calculation for customer reviews by conside...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Transfer of ut information from fpga through ethernet interfaceeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Structural evaluation of low volume road pavements using pavement dynamic con...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
A case study on energy savings in air conditioning system by heat recovery us...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An experimental study of square footing resting on geo grid reinforced sandeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Testing the flexural fatigue behavior of e glass epoxy laminateseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a
total power 1.96mW.
Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wirele...IJERA Editor
This paper presents the design of CT ΣΔ modulator which can provide high DR and SNR over a 20 MHz signal bandwidth. So far all the CT SDM uses either feedback or feedforward loop filter architecture. The proposed topology is a 3rd order low-pass sigma-delta modulator, which employs a combination of feedforward and feedback schemes. Loop filter is designed as RC integrators due to its high linearity and easy interface. The design starts from system level using Matlab/Simulink. Then, the first integrator in the loop, which is the most critical block in the modulator, is implemented at transistor level using Cadence Virtuoso 180 nm CMOS technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
Digital Implementation of Costas Loop with Carrier RecoveryIJERD Editor
Demodulator circuit is a basic building block of wireless communication. Digital implementation of
demodulator is attracting more attention for the significant advantages of digital systems than analog systems.
The carrier signal extraction is the main problem in synchronous demodulation in design of demodulator based
on Software Defined Radio. When transmitter or receiver in motion, it is difficult for demodulator to generate
carrier signal same in frequency and phase as transmitter carrier signal due to Doppler shift and Doppler rate.
Here the digital implementation of Costas loop for QPSK demodulation in continuous mode is discussed with
carrier recovery using phase locked loop.
Effects of filtering on ber performance of an ofdm systemeSAT Journals
Abstract In upcoming generations, wireless communication system requires a higher standard in order to provide high quality of services to customers. Orthogonal Frequency Division Multiplexing (OFDM) is an efficient modulation technique of forthcoming wireless systems which can be implemented easily. In this paper, an effort has been made to analyze how well an OFDM system can perform when a signal is transmitted over an Additive White Gaussian Noise (AWGN) channel using 16 QAM modulation techniques. The performance of OFDM system with pulse shaping filters are also evaluated and results reveal that the pulse shaped OFDM improve the overall performance of the system in terms of BER. We use Different pulse shaping filters such asRaised cosine, FIR Nyquist and SQRT Raised Cosine for analyzingthe Bit Error Rate (BER) performance. Index Terms: AWGN, ICI, OFDM, Bit Error Rate.
This paper presents a novel approach for completely test enable feature and low-voltage delta– sigma analog-to-digital (A/D) converters for cutting edge wireless applications. Oversampling feature of ADCs and DACs is enough to meet the requirement related to in-band and adjacent channel leakage ratio (ACLR) execution of 3G/4G portable radio. The quantization noise which is not filtered in ADC is addressed. We have achieved work power-optimization and test enable feature of oversampling ADC is uses in design and simulation so that the problem of quantization error in continues time sigma delta ADC is solved. This paper suggests support to designer for selecting appropriate topologies with various channel arrangements, number of bits and oversampling issues. A test enable feature of CT A/D is presented introducing the test signal generation (TSG) and the COrdinate Rotation Digital Computer (CORDIC) for evaluating the performance of ADC. This helps in addressing the challenge of 4G and upcoming 5G wireless radio. System level plan of a delta–sigma modulator ADC for 4G radios is studied.
Performance Analysis and Simulation of Decimator for Multirate ApplicationsIJEEE
In this paper, a decimator design has been presented for multirate digital signal processing. The decimator design has been analysed and simulated for performance comparison in terms of filter order and ripple factor. Direct form-I with decimation factor 2 have been used for performance and ripple analysis. The decimators have been designed & simulated using MATLAB. It can be observed from the simulated results that as we increase the filter order, ripple factor decreases, for the same filter structure. On the other hand, increasing filter order will increase its area and implementation cost.
A power efficient delta-sigma ADC with series-bilinear switch capacitor volta...TELKOMNIKA JOURNAL
In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
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Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
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Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
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First order sigma delta modulator with low-power
1. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
__________________________________________________________________________________________
Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org 700
FIRST ORDER SIGMA-DELTA MODULATOR WITH LOW-POWER
CONSUMPTION IMPLEMENTED IN AMS 0.35 µM CMOS
TECHNOLOGY
RADWENE LAAJIMI
NIZAR KHITOUNI, University of Sfax, Department of Electrical Engineering Electronics,
Micro-technology and Communication (EMC) research group Sfax (ENIS), BP W, 3038 Sfax, Tunisia
radwene_fac@yahoo.fr
Abstract
This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits
Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is
necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS
technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and
the power consumption was 5.5 mW under ±1.5V supply voltage .
Index terms: Analog-to-Digital conversion, Delta-Sigma modulation, CMOS technology, Transconductance operational
amplifier.
--------------------------------------------------------------------***--------------------------------------------------------------------------
1. INTRODUCTION
Sigma-Delta (ΣΔ) Analog to Digital Converters (ADC) [1] has
been successful in realizing high resolution consumer audio
products, such as MP3 players and cellular phones for some
time now. DS converters are well suited for low bandwidth,
high-resolution acquisition, and low cost, making them a good
ADC [2] choice for many applications. ΣΔ [3] converters
combine an analog ΣΔ modulator with a more complex digital
filter.
Delta
Sigma
Modulator
Digital
LowPass
Filter
Analog
Signal
in
Digital
Signal
out
Figure 1: Block diagram of the ΣΔ analog to digital converter
Accuracy depends on the noise and linearity performance of
the modulator, which uses high performance amplifiers. ΣΔ
modulators trade resolution in time for resolution in amplitude
such that the use of imprecise analog circuits can be tolerated.
The narrow bandwidths in digital audio applications have
made oversampled converters particularly appealing.
A block diagram of an analog to digital converter using ΣΔ
modulator is shown in Figure 1. ΣΔ converters come into the
category of oversampled converters. Oversampling is simply
the act of sampling the input signal at a frequency much
greater than the Nyquist frequency. One significant advantage
of the method is that analog signals are converted using only a
1-bit ADC and analog signal processing circuits having a
precision that is usually much less than the resolution of the
overall converter. The penalty paid for the high resolution
achievable with ΣΔ is that the hardware has to operate at the
oversampled rate, much larger than the maximum signal
bandwidth, thus demanding great complexity of the digital
circuitry. First-order ΣΔ modulator has the advantages of
being simple, robust and stable. This modulator is shown in
Figure 2.
H(z)
DAC
YX
Qin
E
Σ Σ
Figure 2: Linear model of first order ΣΔ Modulator
The modulator can be considered as a two-input, one-output
linear system. The signal transfer function, STF(z) of this
system is:
2. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
__________________________________________________________________________________________
Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org 701
)(1
)(
)(
)(
)(
zH
zH
zX
zY
zSTF
(1)
And the noise transfer function, NTF(z) is:
)(1
1
)(
)(
)(
zHzE
zY
zNTF
(2)
By using superposition principle, the output signal is obtained
as the combination of the input signal and the noise signal,
with each being filtered by the corresponding transfer
function:
)().()().()( zEzNTFzXzSTFzY (3)
By properly selecting the loop filter, the signal transfer
function and the noise transfer function of a theoretical 1st
order ΣΔ modulator yield in the z-domain:
1
)(
zzSTF (4)
)1()( 1
zzNTF (5)
Solving (1) and (4) gives:
1
1
1
)(
z
z
zH
(6)
Note that loop-filter is simply an integrator which can be
easily implemented with switched-capacitor techniques. For a
generalized Lth order ΣΔ modulator, the transfer functions
become:
L
zzSTF
)( (7)
L
zzNTF )1()( 1
(8)
To achieve a transfer function of Lth order, L basic building
blocks i-e L integrators are required. When the modulator
order is higher than one, the frequency response of NTF
presents the characteristic of high-pass filters. The higher the
order L is, the more quantization error energy is suppressed at
low frequencies.
In this way, the output signal for the ideal linear model can be
written as:
LL
zzEzzXzY )1).(().()( 1
(9)
Analog to Digital Converters (ADC) as the interface of analog
circuit and digital circuit connection, which is widely used in
various systems and is a very important module. But the DS
uses rate to substitute accuracy and reduce the performance
requirement of the circuit, which is an effectively way to
achieve high-precision ADC [4]. Discrete time ΣΔ modulator
[5][6] significantly reduces the requirements of the operational
amplifier gain and noise by using well capacitive matching
characteristics, oversampling and noise shaping technology, so
it is very suitable for the application of low voltage.
The main objective of a receiver for wireless communication
applications is to recover the base band signals that are
modulated on a carrier wave at radio frequencies. The design
of a high performance, low power integrated radio frequency
receiver in mainstream silicon technologies CMOS is a very
challenging task involving numerous tradeoffs during the
design process, especially between noise, linearity and power
consumption.
To achieve the objective cited above, all aspects of the
receiver [7] and radio system need to be addressed as shown in
table 1. (Base band, Modulation scheme, hopping bandwidth,
data rate)
Table 1: Sensor receiver specifications
Direct conversion receiver
Base band frequency
( fb )
80 Khz
Modulation scheme BFSK
Hopping bandwidth 7 MHz (863-870)
MHz
Data rate (D) 20 Kbps
The paper is organized as follows. Section II presents the
proposed structure of the ΣΔ modulator with simulations
results. In section III, all main parameters of the described
modulator are indicated with a full comparison of the most
popular designs in which the performance of each modulator
is cited in table 4. Conclusion is drawn in Section IV.
2. PROPOSED STRUCTURE OF THE DELTA-
SIGMA MODULATOR
First order ΣΔ modulators are probably the most common
category of the device which has more stability than second
order and third order circuit. At the core of any ΣΔ modulator
lie integrators; they are usually implemented in CMOS
technology. First-order ΣΔ modulator has the advantages of
being simple, robust and stable. If we compare first order ΣΔ
modulator with the other types in terms of power consumption
and size they consumed low power.
The effective number of bits of ΣΔ (Neff) converter is given
by [8]:
3. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
__________________________________________________________________________________________
Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org 702
LL
eff OSRLNN 2122
2 )/()12()12(log
2
1
(10)
Where N represents number of bits of the quantization
circuitry (N = 1), L represents order of modulator (L = 1) and
OSR means Over Sampling Ratio which is based on the
following formula:
b
s
f
F
OSR
2 (11)
If we choose an OSR equal to 64, Fs is the sampling frequency
which is calculated to 10.240MHz, and fb means base band
frequency (80 KHz). The number 8.14 bits is the theoretical
number because errors in the structure of parasites modulator
reduce the SNR and therefore the number of bits, and to
ensure low power and minimum consumption the number of
bits is chosen as 8 bits.
The functional diagram of the first order modulator simulated
using Simulink in MATLAB is shown in Figure 3. The single
bit DAC is replaced by a simple wire. The input is a sinusoidal
signal with 0.4 V amplitude and frequency 20 kHz. This signal
is fed through only one integrator and is connected to the
comparator at the output.
Analog
Signal
input
Digital
Signal
output
Integrator DAC
Figure 3: Block diagram of First Order ΣΔ Modulator
The modulated output as seen through the scope is shown in
Figure 4 with the input signal overlaid on it.
Figure 4: Block diagram of First Order ΣΔ Modulator
A discrete Fourier Transform (DFT) of the sampled output
signal is performed to calculate the SNR of the system. The
logarithm of the amplitude of the signal is plotted versus the
signal frequency and the SNR is found to be close to 49.25 dB
as shown in Figure 5.
Figure 5: Frequency spectrum zoom of the modulated signal
It can be seen that second order noise shaping is taking place
wherein most of the noise is pushed to the higher frequency
bands as shown in figure 6. The original signal can be
retrieved using a digital low pass filter.
Figure 6: Frequency spectrum of the modulated signal
4. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
__________________________________________________________________________________________
Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org 703
Figure 7 shows a block diagram of a complete first-order ΣΔ
modulator. It is made up of only one integrator, a comparator,
and digital to analog converter (DAC). These include switches
Q and Q’ for applying one of two reference node voltages,
+Vref and -Vref, depending on comparator output polarity.
The integrator is based on amplifier, and use two phase, with
the respective phases denoted by Ф1 and Ф2.
Figure 7: A complete first-order ΣΔ modulator
It is important that an Operational Transconductance
Amplifier (OTA) intended for insertion into a ΣΔ modulator
have an adequate bandwidth and a sufficiently high voltage
gain at the lower frequencies, because the former property
determines the modulator bandwidth, and the latter makes for
lower quantization noise.
The circuit diagram of OTA [9] with modified current source
shown in figure 8, contains two input transistors formed by P-
channel MOSFETs M1 and M2. Either N-channel MOSFET
(NMOS) or P-channel (PMOS) input devices can be used.
However, PMOS input devices are used more often thanks to
improved slew rate and reduced 1/f noise [10]. The use of
PMOS input devices also provides reduced power supply
rejection thanks to the current mirrors, and low sensitivity to
change in power supply voltage. This first stage of op-amp
also had the current mirror circuit formed by an N-channel
MOSFETs, M3 and M4. The transistor M7 serves as an P-
channel common source amplifier which is the second stage of
op-amp. The architecture of modified current source is
composed of two blocks: polarisation and correction.
The polarisation block is formed of four transistors (M12,
M13, M14, M15) with variable input voltage Vin and input
resistance Rin. The correction block is composed of three
transistors (M9, M10, M11).It characterized by minimum error
of copying accuracy due to the equality of drain source voltage
between M10 and M11.This equality thanks to an amplifier
between the mirror’s input and output transistors M10 and
M11 and causes high accuracy and good linearity. High output
impedance is obtained by the output current of amplifier and
passes to the gate of transistor M9. In order to achieve high
current copy accuracy, it is necessary to use an amplifier
between the mirror’s input and output transistors.
The architecture of this amplifier architecture is created by
K.Tanno[11]. As shown in figure 9, this structure is formed by
only two NMOS transistors (MN1 and MN2) in which MN1 is
operated in the weak version region (source gate voltage of
MN1 equal to zero).This version can operate either in the
linear region or in the saturation region for achieving low
voltage and low consumption. Moreover, the conventional
amplifier which has four transistors causes the increase of the
power dissipation and the chip area. The advantages of the
scheme proposed by K.Tanno are low voltage operation, small
chip area, high output resistance and no bias current. For this
reason we use this structure in voltage to current converter.
The overall gain of the amplifier is found to be given by:
767421 //.// dsdsmdsdsmv rrgrrgA
(12)
Where gm i is the transconductance and rds i is the drain to
source resistance of i th transistors with i =1,2,4,6,7.
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1
2
3
4
5
6
7
Page: 1 of 1 Size: A No
Rev: 46 16-Jan-2012 13:11 Create
File:C:UsersradweneDesktopessai_TO
M8
M5 M6
M1
M2
M4
M7
M3
Cc
Cl
Vdd
1.5V
Vss
-1.5V
Vin
M9
M10
1
23
M11
M12
M14
M15
M13
Rin
Iin
Figure 8: Operational Transconductance Amplifier with
modified current source
2
3
1
Ibias
VDD
Ibias
M5 M6
M7
Ibias/2
1 2
3
(b)
A B C D E F G
1
2
3
4
5
6
7
Page: 1 of 1
Rev: 53 16-Jan-2
MN2
Vdd
1 2
3
MN1
Figure 9: Two-transistor amplifier structure
Using Tspice based on BSIM3V3 transistor model for the
technology 0.35µm at ±1.5V power supply voltage, the
simulated output frequency response of our OTA is shown in
5. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
__________________________________________________________________________________________
Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org 704
figure 10. The bode diagram gives an open loop gain of 60 dB
with a large GBW of 82 MHz, a 97 KHz of cut-off frequency
and a phase margin of 62°. We note that the input current
passes through M8 using for polarisation are equal to 10µA
and this corresponds to an input voltage Vin of -1V.
100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
-100
-50
0
50
Magnitude(dB),Phase(deg)
Figure 10: Frequency response of Operational
Transconductance Amplifier
3. RESULTS AND COMPARISON
The modulator is designed using a 0.35um CMOS process, the
over sampling ratio is 64 with a signal band width of about
80kHz.All main parameters of the described modulator are
summed up in Table 3.
Table 3: Designed modulator parameters
Parameters Value
Technology 0.35 µm
Order of modulator 1
Sampling Frequency (clock) 10.24 MHz
Signal Band width 80 KHz
Over sample Ratio(OSR) 64
References ±1V
Maximum Input 1 Vpp
Supply voltage ±1.5V
Resolution 8-bit
Signal to Noise Ratio (SNR) 49.25 dB
Quantizer resolution 1 bit
Power consumption 5.5 mW
Table 4: Comparison table of most popular designs with current work (*)
Resolution OSR SNR
(dB)
Speed
(MHz)
Power
(mW)
Process
(CMOS)
Signal
Band width
Order Ref.
No.
14-bit 24 85 2.2 200 0.35µm 100 KHz 6 12
11-bit 10 62.5 300 70 0.13µm 15 MHz 4 13
14-bit 96 85 53 15 0.18µm 300 KHz 2 14
16-bit 128 - 5.12 2.6 0.18µm 20 KHz 3 15
8-bit 64 49.7 1.024 6.6 0.6µm 8 KHz 1 16
8-bit * 64 49.25 10.24 5.5 0.35µm 80 KHz 1 This Work
The current state of the art in the design of ΣΔ modulator is
limited by the technology and the sampling speeds it is able to
achieve. Here is a comparison table 4 of the most popular
designs which also compares the published works with the
current work. It can be seen that the current work consumes
less power than most published work and achieves the
resolution of 8 bits using one of the technology 0.35 μm
CMOS process.
CONCLUSIONS
The low-power-consumption modulator is designed with
switched-capacitor techniques, and the resolution reaches 8
bits in 0.35 µm CMOS process. Compared to other ΣΔ
modulators, the first order single ΣΔ modulator has many
advantages on performance, stability, area and system
specification requirements, especially the power consumption.
When the power supply is ±1.5 V, the power consumption is
only 5.5 mW.
6. IJRET: International Journal of Research in Engineering and Technology ISSN: 2319-1163
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Volume: 02 Issue: 04 | Apr-2013, Available @ http://www.ijret.org 705
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