In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Improving quality of service using ofdm technique for 4 th generation networkeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
International Journal of Computational Engineering Research (IJCER) ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology
Mixed Linearity Improvement Techniques for Ultra-wideband Low Noise Amplifier IJECEIAES
We present the linearization of an ultra-wideband low noise amplifier (UWB-LNA) operating from 2GHz to 11GHz through combining two linearization methods. The used linearization techniques are the combination of post-distortion cancellation and derivative-superposition linearization methods. The linearized UWB-LNA shows an improved linearity (IIP3) of +12dBm, a minimum noise figure (NF ) of 3.6dB, input and output insertion losses (S 11 and S 22 min. ) below -9dB over the entire working bandwidth, midband gain of 6dB at 5.8GHz, and overall circuit power consumption of 24mW supplied from a 1.5V voltage source. Both UWB-LNA and linearized UWB-LNA designs are verified and simulated with ADS2016.01 software using BSIM3v3 TSMC 180nm CMOS model files. In addition, the linearized UWB-LNA performance is compared with other recent state-of-the-art LNAs.
5GHz MIMO System Power Amplifier design with Adaptive Feedforward Linearizati...Ahmed Nasser Agag
- In such transceiver system, we used power amplifier stage in transmitter section and polyphase filter (PPF) in local oscillator (LO) section
- Less linearity of power amplifier causes higher order intermodulation and consequently destroys orthogonality between subcarriers in OFDM signals.
- Phase error in quadrature LO signal causes crosstalk between I and Q signals and results unavoidable demodulation errors.
4G-Fourth Generation Mobile Communication SystemSafaet Hossain
Seminar on "4G-Fourth Generation Mobile Communication System" at UODA Auditorium, November 16,2013.
Technical Presented by: Ahmedul Quadir, Function Tester, Ericcson, Sweeden
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Effective Area and Power Reduction for Low-Voltage CMOS Image Sensor Based Ap...IJTET Journal
Abstract— This paper presents a novel CMOS image sensor (CIS) based on 45nm processing technology. It includes a single inverter time-to-threshold pulse width modulation circuitry, capable of operating under very low supply voltage. Conventional CMOS image sensors implemented using 130nm processing technology had many advantages. But in order to incorporate additional processing circuitry, the device density increases which results in degradation in the speed of operation. Scaling of physical MOS device dimensions improves both speed and density. The leakage associated with scaling could be eliminated by re-designing the circuit. As result area and power consumption could be reduced, which is demanded by portable imaging equipments.
Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wirele...IJERA Editor
This paper presents the design of CT ΣΔ modulator which can provide high DR and SNR over a 20 MHz signal bandwidth. So far all the CT SDM uses either feedback or feedforward loop filter architecture. The proposed topology is a 3rd order low-pass sigma-delta modulator, which employs a combination of feedforward and feedback schemes. Loop filter is designed as RC integrators due to its high linearity and easy interface. The design starts from system level using Matlab/Simulink. Then, the first integrator in the loop, which is the most critical block in the modulator, is implemented at transistor level using Cadence Virtuoso 180 nm CMOS technology.
Efficient reconfigurable architecture of baseband demodulator in sdreSAT Journals
Abstract This paper presents the simulation architecture and performance analysis with the use of ZCD technic. A Zero-Crossing based All-Digital Baseband Demodulation architecture is proposed in this work. This architecture supports demodulation of all modulation schemes including MSK, PSK, FSK, and QAM. The proposed structure is very low area, low power, and low latency and can operate in real-time. Moreover it can switch, in run-time, between multiple modulation schemes like GMSK (GSM), QPSK (CDMA), GFSK (Bluetooth), 8-PSK (EDGE), Offset-QPSK (W-CDMA), etc. In addition, the phase resolution of the demodulator is scalable with performance. In addition, bit-wise amplitude quantization based quad-decomposition approach is utilized to demodulate higher order M-ary QAM modulations such as 16-QAM & 64-QAM, which is also a highly scalable architecture. This structure of demodulator provides energy-efficient and resource-efficient implementation of various wireless standards in physical layer of SDR. Keywords — Physical layer, Mobile and Wireless Communication, Software Defined radio (SDR), Zero Cross Detection (ZCD), Modulation Schemes, Architecture, high level synthesis, FPGA.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Improving quality of service using ofdm technique for 4 th generation networkeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
International Journal of Computational Engineering Research (IJCER) ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology
Mixed Linearity Improvement Techniques for Ultra-wideband Low Noise Amplifier IJECEIAES
We present the linearization of an ultra-wideband low noise amplifier (UWB-LNA) operating from 2GHz to 11GHz through combining two linearization methods. The used linearization techniques are the combination of post-distortion cancellation and derivative-superposition linearization methods. The linearized UWB-LNA shows an improved linearity (IIP3) of +12dBm, a minimum noise figure (NF ) of 3.6dB, input and output insertion losses (S 11 and S 22 min. ) below -9dB over the entire working bandwidth, midband gain of 6dB at 5.8GHz, and overall circuit power consumption of 24mW supplied from a 1.5V voltage source. Both UWB-LNA and linearized UWB-LNA designs are verified and simulated with ADS2016.01 software using BSIM3v3 TSMC 180nm CMOS model files. In addition, the linearized UWB-LNA performance is compared with other recent state-of-the-art LNAs.
5GHz MIMO System Power Amplifier design with Adaptive Feedforward Linearizati...Ahmed Nasser Agag
- In such transceiver system, we used power amplifier stage in transmitter section and polyphase filter (PPF) in local oscillator (LO) section
- Less linearity of power amplifier causes higher order intermodulation and consequently destroys orthogonality between subcarriers in OFDM signals.
- Phase error in quadrature LO signal causes crosstalk between I and Q signals and results unavoidable demodulation errors.
4G-Fourth Generation Mobile Communication SystemSafaet Hossain
Seminar on "4G-Fourth Generation Mobile Communication System" at UODA Auditorium, November 16,2013.
Technical Presented by: Ahmedul Quadir, Function Tester, Ericcson, Sweeden
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Effective Area and Power Reduction for Low-Voltage CMOS Image Sensor Based Ap...IJTET Journal
Abstract— This paper presents a novel CMOS image sensor (CIS) based on 45nm processing technology. It includes a single inverter time-to-threshold pulse width modulation circuitry, capable of operating under very low supply voltage. Conventional CMOS image sensors implemented using 130nm processing technology had many advantages. But in order to incorporate additional processing circuitry, the device density increases which results in degradation in the speed of operation. Scaling of physical MOS device dimensions improves both speed and density. The leakage associated with scaling could be eliminated by re-designing the circuit. As result area and power consumption could be reduced, which is demanded by portable imaging equipments.
Design of Continuous Time Multibit Sigma Delta ADC for Next Generation Wirele...IJERA Editor
This paper presents the design of CT ΣΔ modulator which can provide high DR and SNR over a 20 MHz signal bandwidth. So far all the CT SDM uses either feedback or feedforward loop filter architecture. The proposed topology is a 3rd order low-pass sigma-delta modulator, which employs a combination of feedforward and feedback schemes. Loop filter is designed as RC integrators due to its high linearity and easy interface. The design starts from system level using Matlab/Simulink. Then, the first integrator in the loop, which is the most critical block in the modulator, is implemented at transistor level using Cadence Virtuoso 180 nm CMOS technology.
Efficient reconfigurable architecture of baseband demodulator in sdreSAT Journals
Abstract This paper presents the simulation architecture and performance analysis with the use of ZCD technic. A Zero-Crossing based All-Digital Baseband Demodulation architecture is proposed in this work. This architecture supports demodulation of all modulation schemes including MSK, PSK, FSK, and QAM. The proposed structure is very low area, low power, and low latency and can operate in real-time. Moreover it can switch, in run-time, between multiple modulation schemes like GMSK (GSM), QPSK (CDMA), GFSK (Bluetooth), 8-PSK (EDGE), Offset-QPSK (W-CDMA), etc. In addition, the phase resolution of the demodulator is scalable with performance. In addition, bit-wise amplitude quantization based quad-decomposition approach is utilized to demodulate higher order M-ary QAM modulations such as 16-QAM & 64-QAM, which is also a highly scalable architecture. This structure of demodulator provides energy-efficient and resource-efficient implementation of various wireless standards in physical layer of SDR. Keywords — Physical layer, Mobile and Wireless Communication, Software Defined radio (SDR), Zero Cross Detection (ZCD), Modulation Schemes, Architecture, high level synthesis, FPGA.
Design and performance analysis of low phase noise LC-voltage controlled osci...TELKOMNIKA JOURNAL
Voltage controlled oscillator (VCO) offers the radio frequency (RF) system designer a freedom to select the required frequency. Today’s wireless communication system imposes a very stringent requirement in terms of phase noise generated in VCO. This study presents an inductive source degeneration technique to improve the phase noise performance of the inductance-capacitance (LC)-VCO. Double cross-coupled topology has been chosen for the proposed VCO. The post layout simulations with the parasitic resistance, inductance, capacitance (RLC) extracted view is carried out with united microelectronics corporations (UMC) 0.18 µm process by spectre simulator of cadence tools. The proposed VCO provides a phase noise
of -124.3 dBc/Hz @ 1 MHz. The tuning range obtained is 19.87% with a centre frequency of 2.46 GHz which makes it suitable for industrial, scientific, and medical (ISM) band applications. It consumes a power of 2.10 mW. Also, a good figure of merit of -189 is achieved. The total layout area occupied is 477×545 µm2.
A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC ...IAEME Publication
The primary motivation of the work presented in this paper is to significantly reduce power consumption in pipe lined ADCs using Switched Capacitance based MDAC with Opamp Sharing configuration. ADC power reduction enables longer battery life in mobile applications, and lower cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the power dissipation in most high-speed analog to digital conversion applications. This work presents a 9 stage, 10-bit Pipe lined ADC with Error Correction Algorithm which achieves the dynamic power consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm CMOS. All the sub-blocks to generate top level Pipe lined ADC have been designed in Cadence environment and simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction...IJECEIAES
To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 µW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 µW while CVSL shows total power consumption of 18.94 µW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Duty Cycle Corrector Using Pulse Width ModulationVLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
International Journal of VLSI design & Communication Systems (VLSICS) VLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
DUTY CYCLE CORRECTOR USING PULSE WIDTH MODULATIONVLSICS Design
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with
respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much
necessary to see to it that the clock signals are properly received specially in receiver circuits where data
sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew,
interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that
ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed
and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency
range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power
consumption is 1.01mW.
Delta-sigma ADC modulator for multibit data converters using passive adder en...journalBEEI
This paper introduces a multi-bit data converters (MDC) modulator of the 2nd order delta-sigma analog-to-digital converter use the passive adder proposed. The noise shaping quantizer can provide feedback that has generated quantization noise and perform additional shaping noise first-order by coupling noise method.Thus, two Integrator's with ring amplifier and the MDC is shaped by noise coupling quantizer know the 2nd-order noise coupled with somewhat of a DAC modulator. At a summing point, the inputs are summed and then filtered with a low pass filter. A cyclic second order response is generated with a data weighted averaging (DWA) technique in which the DACs ' outputs are limited to one of two states in the noise shaping responses. Mainly as a result of the harmonic distortion in circuits of amplifier. Transistor rate is equipped for the fully differential switched condenser integrator used, a comparator and DWA. The modulator with proposed DWA design, almost quarterly improved timing margin. A simulated SNDR of 92dB is obtained at 20 MHz sampling frequency; while a sinusoidal output of 4.112 dBFS is tested at 90µs besides 20 MHz as the bandwidth. The power consumption is 0.33 mW while the voltage of the supply is 1.2V.
Amazon products reviews classification based on machine learning, deep learni...TELKOMNIKA JOURNAL
In recent times, the trend of online shopping through e-commerce stores and websites has grown to a huge extent. Whenever a product is purchased on an e-commerce platform, people leave their reviews about the product. These reviews are very helpful for the store owners and the product’s manufacturers for the betterment of their work process as well as product quality. An automated system is proposed in this work that operates on two datasets D1 and D2 obtained from Amazon. After certain preprocessing steps, N-gram and word embedding-based features are extracted using term frequency-inverse document frequency (TF-IDF), bag of words (BoW) and global vectors (GloVe), and Word2vec, respectively. Four machine learning (ML) models support vector machines (SVM), logistic regression (RF), logistic regression (LR), multinomial Naïve Bayes (MNB), two deep learning (DL) models convolutional neural network (CNN), long-short term memory (LSTM), and standalone bidirectional encoder representations (BERT) are used to classify reviews as either positive or negative. The results obtained by the standard ML, DL models and BERT are evaluated using certain performance evaluation measures. BERT turns out to be the best-performing model in the case of D1 with an accuracy of 90% on features derived by word embedding models while the CNN provides the best accuracy of 97% upon word embedding features in the case of D2. The proposed model shows better overall performance on D2 as compared to D1.
Design, simulation, and analysis of microstrip patch antenna for wireless app...TELKOMNIKA JOURNAL
In this study, a microstrip patch antenna that works at 3.6 GHz was built and tested to see how well it works. In this work, Rogers RT/Duroid 5880 has been used as the substrate material, with a dielectric permittivity of 2.2 and a thickness of 0.3451 mm; it serves as the base for the examined antenna. The computer simulation technology (CST) studio suite is utilized to show the recommended antenna design. The goal of this study was to get a more extensive transmission capacity, a lower voltage standing wave ratio (VSWR), and a lower return loss, but the main goal was to get a higher gain, directivity, and efficiency. After simulation, the return loss, gain, directivity, bandwidth, and efficiency of the supplied antenna are found to be -17.626 dB, 9.671 dBi, 9.924 dBi, 0.2 GHz, and 97.45%, respectively. Besides, the recreation uncovered that the transfer speed side-lobe level at phi was much better than those of the earlier works, at -28.8 dB, respectively. Thus, it makes a solid contender for remote innovation and more robust communication.
Design and simulation an optimal enhanced PI controller for congestion avoida...TELKOMNIKA JOURNAL
In this paper, snake optimization algorithm (SOA) is used to find the optimal gains of an enhanced controller for controlling congestion problem in computer networks. M-file and Simulink platform is adopted to evaluate the response of the active queue management (AQM) system, a comparison with two classical controllers is done, all tuned gains of controllers are obtained using SOA method and the fitness function chose to monitor the system performance is the integral time absolute error (ITAE). Transient analysis and robust analysis is used to show the proposed controller performance, two robustness tests are applied to the AQM system, one is done by varying the size of queue value in different period and the other test is done by changing the number of transmission control protocol (TCP) sessions with a value of ± 20% from its original value. The simulation results reflect a stable and robust behavior and best performance is appeared clearly to achieve the desired queue size without any noise or any transmission problems.
Improving the detection of intrusion in vehicular ad-hoc networks with modifi...TELKOMNIKA JOURNAL
Vehicular ad-hoc networks (VANETs) are wireless-equipped vehicles that form networks along the road. The security of this network has been a major challenge. The identity-based cryptosystem (IBC) previously used to secure the networks suffers from membership authentication security features. This paper focuses on improving the detection of intruders in VANETs with a modified identity-based cryptosystem (MIBC). The MIBC is developed using a non-singular elliptic curve with Lagrange interpolation. The public key of vehicles and roadside units on the network are derived from number plates and location identification numbers, respectively. Pseudo-identities are used to mask the real identity of users to preserve their privacy. The membership authentication mechanism ensures that only valid and authenticated members of the network are allowed to join the network. The performance of the MIBC is evaluated using intrusion detection ratio (IDR) and computation time (CT) and then validated with the existing IBC. The result obtained shows that the MIBC recorded an IDR of 99.3% against 94.3% obtained for the existing identity-based cryptosystem (EIBC) for 140 unregistered vehicles attempting to intrude on the network. The MIBC shows lower CT values of 1.17 ms against 1.70 ms for EIBC. The MIBC can be used to improve the security of VANETs.
Conceptual model of internet banking adoption with perceived risk and trust f...TELKOMNIKA JOURNAL
Understanding the primary factors of internet banking (IB) acceptance is critical for both banks and users; nevertheless, our knowledge of the role of users’ perceived risk and trust in IB adoption is limited. As a result, we develop a conceptual model by incorporating perceived risk and trust into the technology acceptance model (TAM) theory toward the IB. The proper research emphasized that the most essential component in explaining IB adoption behavior is behavioral intention to use IB adoption. TAM is helpful for figuring out how elements that affect IB adoption are connected to one another. According to previous literature on IB and the use of such technology in Iraq, one has to choose a theoretical foundation that may justify the acceptance of IB from the customer’s perspective. The conceptual model was therefore constructed using the TAM as a foundation. Furthermore, perceived risk and trust were added to the TAM dimensions as external factors. The key objective of this work was to extend the TAM to construct a conceptual model for IB adoption and to get sufficient theoretical support from the existing literature for the essential elements and their relationships in order to unearth new insights about factors responsible for IB adoption.
Efficient combined fuzzy logic and LMS algorithm for smart antennaTELKOMNIKA JOURNAL
The smart antennas are broadly used in wireless communication. The least mean square (LMS) algorithm is a procedure that is concerned in controlling the smart antenna pattern to accommodate specified requirements such as steering the beam toward the desired signal, in addition to placing the deep nulls in the direction of unwanted signals. The conventional LMS (C-LMS) has some drawbacks like slow convergence speed besides high steady state fluctuation error. To overcome these shortcomings, the present paper adopts an adaptive fuzzy control step size least mean square (FC-LMS) algorithm to adjust its step size. Computer simulation outcomes illustrate that the given model has fast convergence rate as well as low mean square error steady state.
Design and implementation of a LoRa-based system for warning of forest fireTELKOMNIKA JOURNAL
This paper presents the design and implementation of a forest fire monitoring and warning system based on long range (LoRa) technology, a novel ultra-low power consumption and long-range wireless communication technology for remote sensing applications. The proposed system includes a wireless sensor network that records environmental parameters such as temperature, humidity, wind speed, and carbon dioxide (CO2) concentration in the air, as well as taking infrared photos.The data collected at each sensor node will be transmitted to the gateway via LoRa wireless transmission. Data will be collected, processed, and uploaded to a cloud database at the gateway. An Android smartphone application that allows anyone to easily view the recorded data has been developed. When a fire is detected, the system will sound a siren and send a warning message to the responsible personnel, instructing them to take appropriate action. Experiments in Tram Chim Park, Vietnam, have been conducted to verify and evaluate the operation of the system.
Wavelet-based sensing technique in cognitive radio networkTELKOMNIKA JOURNAL
Cognitive radio is a smart radio that can change its transmitter parameter based on interaction with the environment in which it operates. The demand for frequency spectrum is growing due to a big data issue as many Internet of Things (IoT) devices are in the network. Based on previous research, most frequency spectrum was used, but some spectrums were not used, called spectrum hole. Energy detection is one of the spectrum sensing methods that has been frequently used since it is easy to use and does not require license users to have any prior signal understanding. But this technique is incapable of detecting at low signal-to-noise ratio (SNR) levels. Therefore, the wavelet-based sensing is proposed to overcome this issue and detect spectrum holes. The main objective of this work is to evaluate the performance of wavelet-based sensing and compare it with the energy detection technique. The findings show that the percentage of detection in wavelet-based sensing is 83% higher than energy detection performance. This result indicates that the wavelet-based sensing has higher precision in detection and the interference towards primary user can be decreased.
A novel compact dual-band bandstop filter with enhanced rejection bandsTELKOMNIKA JOURNAL
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Impact of CuS counter electrode calcination temperature on quantum dot sensit...TELKOMNIKA JOURNAL
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Electroencephalography-based brain-computer interface using neural networksTELKOMNIKA JOURNAL
This study aimed to develop a brain-computer interface that can control an electric wheelchair using electroencephalography (EEG) signals. First, we used the Mind Wave Mobile 2 device to capture raw EEG signals from the surface of the scalp. The signals were transformed into the frequency domain using fast Fourier transform (FFT) and filtered to monitor changes in attention and relaxation. Next, we performed time and frequency domain analyses to identify features for five eye gestures: opened, closed, blink per second, double blink, and lookup. The base state was the opened-eyes gesture, and we compared the features of the remaining four action gestures to the base state to identify potential gestures. We then built a multilayer neural network to classify these features into five signals that control the wheelchair’s movement. Finally, we designed an experimental wheelchair system to test the effectiveness of the proposed approach. The results demonstrate that the EEG classification was highly accurate and computationally efficient. Moreover, the average performance of the brain-controlled wheelchair system was over 75% across different individuals, which suggests the feasibility of this approach.
Adaptive segmentation algorithm based on level set model in medical imagingTELKOMNIKA JOURNAL
For image segmentation, level set models are frequently employed. It offer best solution to overcome the main limitations of deformable parametric models. However, the challenge when applying those models in medical images stills deal with removing blurs in image edges which directly affects the edge indicator function, leads to not adaptively segmenting images and causes a wrong analysis of pathologies wich prevents to conclude a correct diagnosis. To overcome such issues, an effective process is suggested by simultaneously modelling and solving systems’ two-dimensional partial differential equations (PDE). The first PDE equation allows restoration using Euler’s equation similar to an anisotropic smoothing based on a regularized Perona and Malik filter that eliminates noise while preserving edge information in accordance with detected contours in the second equation that segments the image based on the first equation solutions. This approach allows developing a new algorithm which overcome the studied model drawbacks. Results of the proposed method give clear segments that can be applied to any application. Experiments on many medical images in particular blurry images with high information losses, demonstrate that the developed approach produces superior segmentation results in terms of quantity and quality compared to other models already presented in previeous works.
Automatic channel selection using shuffled frog leaping algorithm for EEG bas...TELKOMNIKA JOURNAL
Drug addiction is a complex neurobiological disorder that necessitates comprehensive treatment of both the body and mind. It is categorized as a brain disorder due to its impact on the brain. Various methods such as electroencephalography (EEG), functional magnetic resonance imaging (FMRI), and magnetoencephalography (MEG) can capture brain activities and structures. EEG signals provide valuable insights into neurological disorders, including drug addiction. Accurate classification of drug addiction from EEG signals relies on appropriate features and channel selection. Choosing the right EEG channels is essential to reduce computational costs and mitigate the risk of overfitting associated with using all available channels. To address the challenge of optimal channel selection in addiction detection from EEG signals, this work employs the shuffled frog leaping algorithm (SFLA). SFLA facilitates the selection of appropriate channels, leading to improved accuracy. Wavelet features extracted from the selected input channel signals are then analyzed using various machine learning classifiers to detect addiction. Experimental results indicate that after selecting features from the appropriate channels, classification accuracy significantly increased across all classifiers. Particularly, the multi-layer perceptron (MLP) classifier combined with SFLA demonstrated a remarkable accuracy improvement of 15.78% while reducing time complexity.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
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A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator
1. TELKOMNIKA Telecommunication, Computing, Electronics and Control
Vol. 18, No. 5, October 2020, pp. 2618~2627
ISSN: 1693-6930, accredited First Grade by Kemenristekdikti, Decree No: 21/E/KPT/2018
DOI: 10.12928/TELKOMNIKA.v18i5.14034 2618
Journal homepage: http://journal.uad.ac.id/index.php/TELKOMNIKA
A power efficient delta-sigma ADC with series-bilinear
switch capacitor voltage-controlled oscillator
D. S. Shylu1
, P. Sam Paul2
, D. Jackuline Moni3
, J. Arolin Monica Helan4
1,3
Department of Electronics and Communication Engineering, Karunya Institute of Technology and Sciences, India
2
Department of Mechanical Engineering, Karunya Institute of Technology and Sciences, India
4
Department of Electronics & Communication Engineering, Karunya Institute of Technology and Sciences, India
Article Info ABSTRACT
Article history:
Received Sep 3, 2019
Revised Mar 28, 2020
Accepted Apr 24, 2020
In low-power VLSI design applications non-linearity and harmonics are
a major dominant factor which affects the performance of the ADC. To avoid
this, the new architecture of voltage-controlled oscillator (VCO) was required
to solve the non-linearity issues and harmonic distortion. In this work,
a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC)
VCO based quantizer was designed using switched capacitor technique.
The proposed technique uses frequency to current conversion technique as
a linearization method to reduce the non-linearity issue. Simulation result
show that the proposed 12-bit delta-sigma ADC consumes the power of
2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.
Keywords:
Amplifier
Continuous-time (CT)
Delta-sigma (ΔΣ)
Loop filter
Switch capacitor circuits
Voltage-controlled oscillator
(VCO)-based ADCs
This is an open access article under the CC BY-SA license.
Corresponding Author:
D. S. Shylu,
Department of Electronics and Communication Engineering,
Karunya Institute of Technology and Sciences,
Karunya Nagar, Coimbatore-641114, Tamil Nadu, India.
Email: mail2shylu@yahoo.com
1. INTRODUCTION
The Delta-sigma (ΔΣ) ADC were widely used for signal acquisition and processing applications.
Hence such types of ADCs were used as codec and hearing aids which require large dynamic range for signal
paths [1-4]. When compared with the Nyquist rate converters, ΔΣ ADC is easier to design as they do not require
analog components with stringent parameters. Oversampling converter samples the input signal bandwidth and
the need for an anti-aliasing filter is eliminated. With medium oversampling ratio and by increased sampling
rate high-resolution ADC can be designed. This efficiently reduces the entire power consumption while
maintaining the required resolution [5]. Scaling of voltage is applicable to digital circuit design in reducing
the heat dissipation at the trade-off of speed factor.Several techniques have been reported to address
this problem such as body-driven circuits, SAR operation, sub-threshold operation [6-9] and zero crossing
circuits [10, 11] and the performance of these circuits were very less.The delta-sigma ADC is a very efficient
structure with oversampling and noise shaping properties.The process scaling factor and bandwidth has
been improved in continuous ΔΣADC. High performance analog circuits include op-amp less pipelined
ADC [12, 13], energy efficient successive approximation register (SAR) ADC [14, 15] and digital calibrated
technique [16, 17]. To process the signal in time domain voltage-controlled oscillators (VCO) play a major
role [18-24]. The VCO outputs introduce quantization error in VCO when the flip-flops are synchronized.
2. TELKOMNIKA Telecommun Comput El Control
A power efficient delta-sigma ADC with series-bilinear switch capacitor… (D. S. Shylu)
2619
Several existing techniques in ΔΣ ADC architecture reduce the power consumption at the cost of
speed [25-29]. Hence the performance of ADC can be improved by transferring the signal processing task to
digital domain and by applying proper scaling methodology. In the proposed design, series-bilinear switch
capacitor based VCO Quantizer is used to eliminate the harmonic distortion and non-linearity by frequency to
current conversion-based linearization technique. The non-linearity of the developed and accomplished VCO
based quantizers is improved by frequency to current conversion method. This paper is organized as follows.
The conventional ΔΣ ADC architecture, circuit designs with its layout are shown and explained in section 2.
Section 3 describes the proposed work of series-bilinear based VCO. Section 4 describe the 4 result and
discussion. Section 5 describes the conclusion.
2. CIRCUIT DESIGN OF CONVENTIONAL DELTA-SIGMA ADC
2.1. Two stage differential operational amplifier
Op-amp is the most important block of ADC and in CMOS technology the design of operational
amplifiers is a challenge as the transistor channel length and voltage reduces. The advantages of the two-stage
op-amp are the good gain, high output swing, low noise and good bandwidth over folded cascade op-amp [25].
The differential gain structure consists of M1, M2, M3, and M4 against the structure of the conventional
operational amplifier as in Figure 1. The input stage of the op-amp is constructed using M1 and M2 NMOS
transistors. For the active load of input differential stage, M3 and M4 transistors are used. M7 is a load and M6
is a driver for current sink load inverter. The output of the M2 transistor was boosted using current source
represented as M6 transistor [26].
The performance of two-stage CMOS op-amp is based on the width and length of the transistor. Care
must be taken to assure that the transistors are operating in the saturation region and not in the triode region.
This is because the triode region causes the transistor to behave in a non-linear fashion leading to poor transient
response as well as the reduction of the overall gain [27]. The layout of the two-stage amplifier is
shown in Figure 2. The obtained area is 75.79*65.1µm² which has a total area of about 4933.9µm². The physical
design steps including DRC check, LVS check, QRC Check and Post-layout simulation was done for
the two-stage amplifier.
2.2. Loop filter
The loop filter of ΔΣ ADC provides the noise-shaping property. It suppresses the nonlinearity present
in the VCO. To achieve a higher order noise shaping, the order of the loop filter must be increased. In this
work, RC topology is chosen for its excellent linearity. In order to suppress the distortion, a high gain loop
filter is required [28]. Figure 3 shows the first order loop filter integrator. It is used because of its linearity and
it is a fully differential circuit that converts square wave input into a triangular waveform. The input is given
to the coupling capacitor. The high value of transconductance is achieved by adjusting the W/L ratio of
the transistors. The circuit of the loop filter is shown in the Figure 3. Figure 4 shows the layout of the loop
filter. The obtained area of the loop filter integrator is 59.06*137.94µm² which has a total area of about
8111.3µm². GDS-II file is also obtained for the layout.
Figure 1. Circuit diagram of two-stage differential amplifier
3. ISSN: 1693-6930
TELKOMNIKA Telecommun Comput El Control, Vol. 18, No. 5, October 2020: 2618 - 2627
2620
Figure 2. Layout for the two-stage amplifier
Figure 3. Op-amp used in the loop filter integrator Figure 4. Layout of the loop filter
2.3. Dynamic latch comparator
In dynamic latch comparators, two cross-coupled CMOS inverters are used for regeneration as in
Figure 5. A clock is used to set the comparator in active or standby mode. The reset operation is achieved through
the shorted transistor M6 between the two cross-coupled inverters. When the enable signal goes low, the circuit enters
into the comparison phase. By adjusting the W/L ratio of the transistors, the high value of transconductance can be
achieved [29, 30]. The major drawback of the dynamic latch comparator is the offset error caused by transistor
mismatch and unbalanced charge residues [30]. Figure 6 shows the layout of the dynamic latch comparator.
The obtained area is 22.095*46.74 µm² which has a total area of about 1032.7 µm.
4. TELKOMNIKA Telecommun Comput El Control
A power efficient delta-sigma ADC with series-bilinear switch capacitor… (D. S. Shylu)
2621
Figure 5. Dynamic latch comparator Figure 6. Layout of the dynamic
latch comparator
2.4. Voltage controlled oscillator based quantizer
The most important building block of ADC is labelled as VCO based Quantizer. VCO produces
a continuous time placed signal whose frequency is precisely corresponding to the input analog signal.
The large value of transconductance is accompanied by regulating the W/L ratio of the transistors [31, 32].
It quantizes the signal on the individual stage and achieves the comparable digital output [33]. There are
mainly two types of building blocks for VCO placed ADCs named as counter based architecture and phase
detector-based architecture [34]. The VCO quantizer comprises of the multistage ring oscillator (RO), two
arrays of DFFs and an array of XOR as shown in Figure 7. The power consumption obtained for VCO quantizer
is 408.7µW. The layout of the VCO Quantizer is shown in Figure 8. The obtained area is 150.02*229.03 µm²
which has a total area of about 34359 µm².
Figure 7. VCO Quantizer based on multistage
ring oscillator
Figure 8. Layout of VCO quantizer
2.5. Digital to analog converter (DAC)
The essential operation of DAC is to cause the digital output of ADC balanced to the analog input.
Delta-sigma ADC uses multi-bit quantizer and multi-bit digital-to-analog (DAC) block to fix up the analog
signal [35, 36]. Figure 9 shows that the layout of the Digital to Analog Converter (DAC). The obtained area is
15.28*33.58 µm² of which the total area is about 513.1024 µm2
.
5. ISSN: 1693-6930
TELKOMNIKA Telecommun Comput El Control, Vol. 18, No. 5, October 2020: 2618 - 2627
2622
Figure 9. Layout of the DAC
3. PROPOSED SERIES -BILINEAR SWITCH CAPACITOR VCO BASED QUANTIZER
Switched capacitor circuits are used in the discrete signal processing applications [37]. The operation
of the switch capacitor circuit is based on the charging and discharging of charges in capacitors. The switched
capacitor emulates the resistor and classified into three types named as parallel, series, and bilinear techniques.
Switch capacitors are mainly used to minimize the chip area [38]. Figure 10 shows the series-bilinear switch
capacitor circuit. The proposed work used is the integration of a series capacitor switch and bilinear capacitor
switch to reduce the non-linearity and harmonic distortion. The significance of the switch capacitor technique
is to have a good dynamic range and accurate frequency. Accuracy is obtained from filter coefficients which
are determined by capacitance ratio. In order to reduce the non-linearity, clock phases are introduced for charge
transfer and non-overlapping clock phases. In the previously reported work, the VCO Quantizer is affected
by linearity issues and noise distortion. In order to reduce the noise distortion, series-bilinear switched capacitor
technique is proposed. The main difficulty in VCO-based Quantizer is the nonlinearity. Linearization technique
used in this proposed work is FCC technique [39] (Frequency to the current converter) in which the harmonic
distortions are reduced. The proposed VCO-based Quantizer uses two parasitic capacitances and two switches
and it is insensitive to the applied voltage and current. Switched capacitor reduces the non-linearity issues using
the linearization method. The proposed work consists of 4 switches. S1, S4 are odd Switch and S2, S3 even
switches. Figure 11 shows the proposed circuit diagram of series-bilinear switch capacitor based low
voltage integrator.
The series-bilinear transformation which is the simple continuous mapping from the S-plane to the
Z-plane by the (1).
𝑆 = 2(1 − 𝑍−1
)/𝑇(1 + 𝑍−1
) (1)
In the proposed work X2 and X3 are resistors; unswitched capacitors X5, X4, X1 perform as capacitive elements.
During Փ2, capacitors X2, X3 are discharged. During Փ1, X5, X4, X1 are charged and not losing the charge
during Փ2. The equivalent resistance of the series-bilinear switch capacitor circuit is (2).
𝑅 =
𝑇
4𝐶1+𝐶2
(2)
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Where R is the resistance and C1 and C2 is the capacitance of the Series-Bilinear switch capacitor circuit.
The flip-flops used in the VCO quantizer changes the VCO output at every clock edges. The output frequency
of the VCO is sampled and is converted to current and is compared with the input current. The converted
current is integrated to the loop filter. The layout of the 12-bit Delta-sigma ADC is shown in Figure 12.
The obtained area is 136.7*143.2µm² of which the total area is 19575µm².
Figure 10. The series-bilinear switch capacitor circuit
Figure 11. Proposed series-bilinear switch capacitor using low voltage integrator
Figure 12. Layout of the proposed 12-bit delta-sigma ADC
4. RESULT AND DISSCUSSION
A conventional delta-sigma analog to digital converter is simulated in a 90nm CMOS process using
a cadence tool. The open loop gain of the designed op-amp is 41 dB. A high-speed VCO quantizer is designed
using 5-stage Ring oscillator with arrays of DFFs and XOR. The obtained power consumption of VCO
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quantizer is 408.7 µW with a sampling frequency of 100 kHz and a Vp-p of 1.2 V. The ADC is designed in
a 90nm CMOS process and achieves 71.54 dB SFDR, 80.63 SNR, 11.56 ENOB, 2.68 mW power consumption
for a 0.6 Vp-p differential input signal from a 1.2 V supply voltage. Figure 13 shows that the various
specification parameters obtained for 12-bit Delta-sigma ADC. Table 1 shows performance comparision of
proposed delta-sigma ADC with prior works [39-44]. The power of 12-bit incremental delta-sigma ADC is
reduced up to 65% when compared with conventional ADCs [45-47].
Table 1. Performance comparision of proposed delta-sigma adc with prior works
Parameter This work [39] [40] [41] [42] [43] [44]
Process Technology(nm) 90 180 180 90 90 90 90
ENOB 11.56 11 13.7 - - - -
Input Frequency 1GHz 150 MHz 350MHz 80MHz 40-240MHz 80-
320MHz
Sampling Frequency 200 MSPS - 200 MSPS 80 80 90 33.3
Supply Voltage(V) 1.2 3.3 3.3 1 1.2 1.2 1.2
Input Voltage(p-pdiff) 0.6 V 2.5V 3V 2mV - 0.8
SFDR (dB) 71.54dB 87 82 - - 79-83
SNR (dB) 80.63dB 84 86 76 68 65.5-77 76.30
Power consumption(mW) 2.68 4.8 16 6.98 5.35 3.43-6.83 6.74
Figure 13. Various specification for 12 -bit delta-sigma ADC
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5. CONCLUSION
The proposed Delta-sigma ADC is used for high-resolution gain and stability of the quantizer.
The designed op-amp achieves the gain of 41dB and consumes the power of 51.11µW from a 1-V supply.
The ADC saves power by sharing a two-stage amplifier to perform signal summation. The loop filter produces
the integrated output, which depends on the operational amplifier. The VCO quantizer is used as comparator
circuit which quantizes the signal from the filter. The total power consumption of 12- bit ADC is 2.68mW.
Simulation result shows that the proposed work 12-bit ΔΣ ADC consumes the power of 2.68mW and the total
area occupied is 0.12mm2
. The Post Layout simulation is done for all the blocks and GDS-II file format has
been obtained for 12-bit incremental delta-sigma ADC .Based on the other reported ADCs in the literature it
is found that the designed 12-bit Delta-sigma ADC with the new proposed VCO has less power consumption
and less core area which make it suitable for various applications
ACKNOWLEDGEMENTS
We would like to give sincere thanks to the VLSI Lab of ECE Department, School of Engineering &
Technology, Karunya Institute of Technology & Sciences for providing the cadence software tool to complete
this work.
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BIOGRAPHIES OF AUTHORS
D. S. Shylu is working as an Associate Professor in ECE Department, Karunya Karunya
Institute of Technology & Sciences. She received her BE degree from M.S. University,
Tirunelveli and M. Tech in VLSI Design from SASTRA University, Thanjavore. She
obtained her Ph.D. degree in ECE Department at Karunya Deemed University. She has 16
years of teaching experience. She has published more than 50 papers in National and
International Journals and conferences. Her areas of interest are Analog VLSI Design,
Device modeling, Low Power VLSI Design.
10. TELKOMNIKA Telecommun Comput El Control
A power efficient delta-sigma ADC with series-bilinear switch capacitor… (D. S. Shylu)
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P. Sam Paul received his Bachelor degree in Mechanical Engineering in 1999 from
Manonmonium Sundaranar University and Master degree in CAD in 2001 from Madras
University, India. He obtained his Ph.D. degree in Mechanical Engineering at Karunya
Deemed University. At present he is working as a Professor in Department of Mechanical
Engineering in Karunya Deemed University. His research interests include Vibration and
Finite element analysis. He has published papers in many refereed international journals
and conferences for his highest level of achievement.
D. Jackuline Moni working as a Professor in ECE Department, Karunya University.
She did her B. Tech in Electronics Engineering at Madras Institute of Technology, Anna
University, M.E in (Applied Electronics) from Government College of Technology,
Coimbatore, and her Ph. D in (VLSI Design) from Anna University, Chennai. She has over
30 years of teaching experience. She has presented and published more than 90 papers in
National and International Journals and conferences. Her areas of interest are CAD VLSI
Design, Device modeling, Low Power VLSI Design, analog VLSI Design.
J. Arolin Monica Helan completed Bachelors in Electronics Engineering from Karpagam
Institute of Technology, Coimbatore. She completed M. Tech in VLSI Design from
Karunya Institute of Technology and Sciences. Her area of interest is CMOS VLSI Design,
Analog VLSI Design and Testing and Testability.