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Design of 60 GHz Receiver inCMOSTeam 5:Hao WangMing DingMayur Sarode
Assignment       Goals:       •   Use 57 to 64 GHz unlicensed band       •   Over 1 Gbps of bit rate at a distance of 10 m...
Evaluating the Link Budget                           Contribution    Running total  TX power                 +10dBm       ...
Bit rate calculationC     BW *log 2 (1 SNR) 14.863We use 10 Gbps    We use 16-QAM modulation, which    The required Bandwi...
System Specification                    Specifications   achieved   unit Technology         45-130           65         nm...
Choice of Architecture(1)       Goal           To design a Low noise amplifier, Mixer and the oscillator           Low IF ...
Choice of Architecture(2)       Antennas       • Omnidirectional antennas provide limited gain and bit rate       • Using ...
The CMOS technology       We choose 65 nm for our design       Trade off between design bottleneck and benefits of scaling...
System performance  Noise Figure IIP3                Gain       SNR     Power                                             ...
New System Performance   Noise               IIP3(dB)   Gain(dB)   SNR    Power   Figure(dB)                              ...
LOW NOISE AMPLIFIER                             DESIGN/ name of department                         30-5-2010   PAGE 10
Survey of LNA’sPaper                   CMOS   Supply   topology          specifications                        (nm)   (vol...
Choice of topology       • Choice between common gate,cascode and common         source   In this a assignment a combinati...
Design of the circuit                                                                           30-5-2010   PAGE 13/Courte...
Passive and active component       specifications      These formula are based on the short channel model of CMOS         ...
Design of the second Stage            •C1 is taken as a bond pad capacitance            •L1 is the bond wire used for outp...
Design of circuit (2)       • Biasing of CMOS with a current mirror (1.72mA)       • Reduces channel length modulation eff...
Components specifications        Parameter            Designed Values   Optimized Values        Width                9.954...
Performance(1)/ name of department    30-5-2010   PAGE 18
Performance(2)/ name of department    30-5-2010   PAGE 19
Performance(3)                          1dB compression                          point= -20 dBm                        K>1...
Performance/ name of department   30-5-2010   PAGE 21
/ name of department   30-5-2010   PAGE 22
Specifications  RF_power                      IP3in                IP3out_upper   IP3out_lower  -12                       ...
LNA achieved specifications                       Specifications                       S(2,1) (power again)          19.25...
Future Developments       • Replacing inductors with Microstrip transmission lines, coplanar         waveguides       • Re...
Corrections made to the LNA                       • Biasing of the output stage. The output stage was biased with a       ...
New performance(1):Noise Figure                       •Noise figure/ name of department                     30-5-2010   PA...
New performance(2): S parameters/ name of department                      30-5-2010   PAGE 28
New performance(3): 1 dB compression       point and stability/ name of department                   30-5-2010   PAGE 29
New Performance(3):Input output       matching/ name of department                     30-5-2010   PAGE 30
New performance(4):IIP3  RF_power             IP3in     IP3out_upper   IP3out_lower  -12                  -12.621   7.185 ...
New Specifications                       Specifications                       S(2,1) (power again)          16.25 dB      ...
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LnA Design_group5

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THis ppt decibes the simulation reuslts of 60 GHz LNA simulated in ADS agilent

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LnA Design_group5

  1. 1. Design of 60 GHz Receiver inCMOSTeam 5:Hao WangMing DingMayur Sarode
  2. 2. Assignment Goals: • Use 57 to 64 GHz unlicensed band • Over 1 Gbps of bit rate at a distance of 10 m • Cost <10 euros • Robust receiver Challenges: • Use latest CMOS technology (65nm - 45 nm) • Selecting channel BW, modulation • Specifications of the Digital part of the system/ name of department 30-5-2010 PAGE 1
  3. 3. Evaluating the Link Budget Contribution Running total TX power +10dBm 10dBm TX antenna gain 10dB 20dBm Path loss over 10m -68.1188dBm -48.1188dBm Rx antenna gain 10dB -38.1188dBm Background noise -174dBm/Hz -174dBm/Hz Noise BW(3Ghz) +94.7712 -79.2288dBm Noise figure of RX +10dB -69.2288dBm SNR at output -38.1188-(-69.2288)=31.11 Required SNR 10dB System margin 21dB Oxygen absorption can be omitted here Path loss more complicated/ name of department 30-5-2010 PAGE 2
  4. 4. Bit rate calculationC BW *log 2 (1 SNR) 14.863We use 10 Gbps We use 16-QAM modulation, which The required Bandwidth 12Gbps/4b=3GHz
  5. 5. System Specification Specifications achieved unit Technology 45-130 65 nm Supply Power - 1.2 V Power <1000 39.4296 mW cost <10 5.4 euro Noise Figure 10 1.93 dB RF frequency 57-64 60.91 GHz LO frequency 55-64 57.91 GHz IF frequency 3 3 GHz Bond wire:1nH/mm Bond pad~ 100 fF
  6. 6. Choice of Architecture(1) Goal To design a Low noise amplifier, Mixer and the oscillator Low IF architecture was selected. +++ Monolithic integration LNA matching LPF filter --- LO leakage IP2 Sensitive to noise Gain and phase match/ name of department 30-5-2010 PAGE 5
  7. 7. Choice of Architecture(2) Antennas • Omnidirectional antennas provide limited gain and bit rate • Using directional and array of antennas to meet the requirements • Use of phase shifters to improve SNR of a receiver • It reduces multipath propagation • Filters Low pass filter at the output mixer/ name of department 30-5-2010 PAGE 6
  8. 8. The CMOS technology We choose 65 nm for our design Trade off between design bottleneck and benefits of scaling Advantages Higher speed, higher integration Challenges • Increasing leakage • Reduction in voltage supply • Process variability • Parasitic effects and impedance matching/ name of department 30-5-2010 PAGE 7
  9. 9. System performance Noise Figure IIP3 Gain SNR Power consumed 1.425dB -24.55 dB 21.521dB ????? 39.4296mW/ name of department 30-5-2010 PAGE 8
  10. 10. New System Performance Noise IIP3(dB) Gain(dB) SNR Power Figure(dB) consumed (mW) 1.3971 -14.42 17.768 ???? 52.79/ name of department 30-5-2010 PAGE 9
  11. 11. LOW NOISE AMPLIFIER DESIGN/ name of department 30-5-2010 PAGE 10
  12. 12. Survey of LNA’sPaper CMOS Supply topology specifications (nm) (volt)60 GHz compact 65 1.2 3 stage single CenterLNA in 65 nm ended topology Frequency=57 GHz Gain=19.1 NF=5.5 dBA 60GHz Low- 90 1.2 Single stage NF=9.6,Noise High- cascode IP3=-14Linearity Receiver gain =10 dBFront-End Design 5.4mAA 60-GHz CMOS 130 1.2 Common gate Voltage gain:28 dBReceiver Front-End topology NF:12.5, Power :9mw60-GHz Receiver 65n 1.2 5 stage Cascode 20 dB gainand Transmitter topologyFront-Ends in 65- / name of department 30-5-2010 PAGE 11
  13. 13. Choice of topology • Choice between common gate,cascode and common source In this a assignment a combination of cascode and common source amplifier is used/ name of department 30-5-2010 PAGE 12
  14. 14. Design of the circuit 30-5-2010 PAGE 13/Courtesy:LNA-ESD co design for fully integrated CMOS wireless receivers
  15. 15. Passive and active component specifications These formula are based on the short channel model of CMOS Length=0.065e-6 m Ft=190MHz/ name of department 30-5-2010 PAGE 14
  16. 16. Design of the second Stage •C1 is taken as a bond pad capacitance •L1 is the bond wire used for output matching 1 w0 LC •CL is designed by •Ld and the source inductance of M1 is designed to maximize gain. •RL is designed for a quality factor of 10/ name of department 30-5-2010 PAGE 15
  17. 17. Design of circuit (2) • Biasing of CMOS with a current mirror (1.72mA) • Reduces channel length modulation effect W2 Iout L2 • Iref W1 L1 •Reduction in noise finger with number of fingers •ESD protection at the gate •Input and output bond pad capacitance •Noise in the power supply lines •Input /output matching/ name of department 30-5-2010 PAGE 16
  18. 18. Components specifications Parameter Designed Values Optimized Values Width 9.954 um 10 um Ls(for Ft=190 GHz) 4.18e-11 H 3.35e-11 H Lg 5.55e-10 H 2.75e-10 H Ld 7.063e-12 H 4e-10 H CL 8.74e-14 F 8.79e-14 F RL 303.479 ohm 303.479 ohm/ name of department 30-5-2010 PAGE 17
  19. 19. Performance(1)/ name of department 30-5-2010 PAGE 18
  20. 20. Performance(2)/ name of department 30-5-2010 PAGE 19
  21. 21. Performance(3) 1dB compression point= -20 dBm K>1 for the 60Ghz band/ name of department 30-5-2010 PAGE 20
  22. 22. Performance/ name of department 30-5-2010 PAGE 21
  23. 23. / name of department 30-5-2010 PAGE 22
  24. 24. Specifications RF_power IP3in IP3out_upper IP3out_lower -12 -12.437 7.369 7.282 1st and 3rd order spectrums/ name of department 30-5-2010 PAGE 23
  25. 25. LNA achieved specifications Specifications S(2,1) (power again) 19.25 dB Voltage gain 18.54 dB Third order intercept(IIP3) -12 dBm Noise figure 1.206 dB 1 dB compression point -20dBm Center frequency 60.91 GHz Power dissipation 31.03 mW/ name of department 30-5-2010 PAGE 24
  26. 26. Future Developments • Replacing inductors with Microstrip transmission lines, coplanar waveguides • Resistance and Inductance of interconnects • Effects of variation in temperature • Effect of the substrate/ name of department 30-5-2010 PAGE 25
  27. 27. Corrections made to the LNA • Biasing of the output stage. The output stage was biased with a resitor of 10K ohm from the drain to the source./ name of department 30-5-2010 PAGE 26
  28. 28. New performance(1):Noise Figure •Noise figure/ name of department 30-5-2010 PAGE 27
  29. 29. New performance(2): S parameters/ name of department 30-5-2010 PAGE 28
  30. 30. New performance(3): 1 dB compression point and stability/ name of department 30-5-2010 PAGE 29
  31. 31. New Performance(3):Input output matching/ name of department 30-5-2010 PAGE 30
  32. 32. New performance(4):IIP3 RF_power IP3in IP3out_upper IP3out_lower -12 -12.621 7.185 7.284/ name of department 30-5-2010 PAGE 31
  33. 33. New Specifications Specifications S(2,1) (power again) 16.25 dB Voltage gain 14.925 dB Third order intercept(IIP3) -12.621 dBm Noise figure 1.206 dB 1 dB compression point -19dBm Center frequency 60.91 GHz Power dissipation 44.4mW/ name of department 30-5-2010 PAGE 32

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