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FINFET TRANSISTORS
BY: ESMAEIL JAVADI
MASTER STUDENT OF KNTU
1
MOOR’S LAW
• 1965 – 1975 first edition Theory
• Review in 1975 until now
• 6m from 1976 to 7nm in 2019
2
HISTORY
• 20nm Feature size challenge in integration
• DIBL, Constriction Doping, Vth, Quantionic reactions, …
• FINFET Theory, Revolution in Structure of Planar Transistors
• HU & King-Liu & BOKO from Berkeley California firs theorist of FINFET 3
MOSFET SHORT CHANNEL EFFECTS
• Cg-s & Cg-d & Cg-ch
• Punch – Through & Doping
• DIBL Effect
• Surface Current Effect
4
SOI MOSFET STRUCTURE
• Using SOI Wafer
• Advantage :
• Reduce the parasitic junction
capacitance
• Lower power
• Disadvantage :
• Difficulty in manufacturing
• Self-heating problem
5
FINFET THEORY & STRUCTURE
• Offer in 1999 - 2000
• Without doping
• Improve channel control
• Decrease channel length
• Increase L/W parameter
6
CHANNEL IMPROVING
Width of Channel = 2 X Fin Height + Fin Width (Equation-4)
7
FINFET OPERATION
8
ADVANTAGE
FINFET ADVANTAGES
• Solve disadvantage parameter in MOSFETs.
• Feature sizes - Possible to lower 7nm.
• Much lower power consumption allows high integration levels. (150%)
• Operating speed - Often in excess of 30% faster.
• Static leakage current-Typically reduced by up to 90%
9
SAMSUNG FOUNDRY'S NEW TRANSISTOR
7nm Samsung Technology :
• GEAT-ALL-AROUND FET TRANSISTOR (GAAFET)
• MULTI-BRIDGE-CHANNEL FET TRANSISTOR (MBCFET)
10
THE END
11

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Finfet Transistors

  • 1. FINFET TRANSISTORS BY: ESMAEIL JAVADI MASTER STUDENT OF KNTU 1
  • 2. MOOR’S LAW • 1965 – 1975 first edition Theory • Review in 1975 until now • 6m from 1976 to 7nm in 2019 2
  • 3. HISTORY • 20nm Feature size challenge in integration • DIBL, Constriction Doping, Vth, Quantionic reactions, … • FINFET Theory, Revolution in Structure of Planar Transistors • HU & King-Liu & BOKO from Berkeley California firs theorist of FINFET 3
  • 4. MOSFET SHORT CHANNEL EFFECTS • Cg-s & Cg-d & Cg-ch • Punch – Through & Doping • DIBL Effect • Surface Current Effect 4
  • 5. SOI MOSFET STRUCTURE • Using SOI Wafer • Advantage : • Reduce the parasitic junction capacitance • Lower power • Disadvantage : • Difficulty in manufacturing • Self-heating problem 5
  • 6. FINFET THEORY & STRUCTURE • Offer in 1999 - 2000 • Without doping • Improve channel control • Decrease channel length • Increase L/W parameter 6
  • 7. CHANNEL IMPROVING Width of Channel = 2 X Fin Height + Fin Width (Equation-4) 7
  • 9. ADVANTAGE FINFET ADVANTAGES • Solve disadvantage parameter in MOSFETs. • Feature sizes - Possible to lower 7nm. • Much lower power consumption allows high integration levels. (150%) • Operating speed - Often in excess of 30% faster. • Static leakage current-Typically reduced by up to 90% 9
  • 10. SAMSUNG FOUNDRY'S NEW TRANSISTOR 7nm Samsung Technology : • GEAT-ALL-AROUND FET TRANSISTOR (GAAFET) • MULTI-BRIDGE-CHANNEL FET TRANSISTOR (MBCFET) 10