IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This presentation discusses the basics of Pass Transistor Logic, its advantages, limitation and finally implementation of Boolean functions/Combinational Logic circuits using Pass Transistor Logic.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This presentation discusses the basics of Pass Transistor Logic, its advantages, limitation and finally implementation of Boolean functions/Combinational Logic circuits using Pass Transistor Logic.
PIC A special purpose integrated circuit that function as an overall manager in an interrupt driven system.
๏It accepts request from the peripheral equipment,determines which of the incoming request is of the highest priority, ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination.
Register Organization of 8086, Architecture, Signal Description of 8086, Physical Memory
Organization, General Bus Operation, I/O Addressing Capability, Special Processor Activities,
Minimum Mode 8086 System and Timings, Maximum Mode 8086 System and Timings.
Addressing Modes of 8086.
Design of ring oscillator using controlled low voltage swing inverter khush_19
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Hello everyone. I am khushboo kumari.
I am pursuing M.tech from NIT Agartala(2017-2019). This is my 3rd semester partial project where i have successfully implemented the design of low voltage swing inverter. In the 4th semester i would be designing ring oscillator by connecting odd number of this inverter design in cascade.
I was able to complete this under the supervision of my respected guide Bidyut kumar .
Hope this presentation helps you to some extent.
Thank you.
Please do comment me if you have any doubts/ query/ or suggestions.
Threshold Voltage & Channel Length ModulationBulbul Brahma
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Design and Technology of Electronic Devices:
Review of microelectronic devices, introduction to MOS technology and related devices.
MOS transistor theory, scaling theory related to MOS circuits, short channel effect and its
consequences, narrow width effect, FN tunnelling, Double gate MOSFET, Cylindrical
MOSFET, Basic concept of CMOS circuits and logic design. Circuit characterization and
performance estimation, important issues in real devices. PE logic, Domino logic, Pseudo
N-MOS logic-dynamic CMOS and Clocking, layout design and stick diagram, CMOS
analog circuit design, CMOS design methods. Introduction to SOI, Multi layer circuit
design and 3D integration. CMOS processing technology: Crystal grown and Epitaxy, Film
formation, Lithography and Etching, Impurity doping, Integrated Devices.
This Presentation describes the ARM CORTEX M3 core processor with the details of the core peripherals. Soon a CORTEX base controller(STM32F100RBT6) ppt will be uploaded. For more information mail me at:gaurav.iitkg@gmail.com.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
This presentation has given a brief introduction and working of CMOS Logic Structures which includes MOS logic, CMOS logic, CMOS logic structure, CMOS complementary logic, pass transistor logic, bi CMOS logic, pseudo โnMOS logic, CMOS domino logic, Cascode Voltage Switch Logic(CVSL), clocked CMOS logic(cยฒmos), dynamic CMOS logic
Power Management in Embedded Systems โ Colin Walls
The importance of power management in todayโs embedded designs has been steadily growing as an increasing number of battery powered devices are developed. Often power optimizations are left to the very end of the project cycle, almost as an afterthought. In this presentation we will discuss design considerations that should be made when starting a new power sensitive embedded design, which include choosing the hardware with desired capabilities, defining a hardware architecture that will allow software to dynamically control power consumption, defining appropriate power usage profiles, making the appropriate choice of an operating system and drivers, choosing measurable power goals and providing these goals to the software development team to track throughout the development process.
Power reduction techniques are important for the modern VLSI designs. Power is the today's major concern when we come to optimal trade off between area, performance and power.
PIC A special purpose integrated circuit that function as an overall manager in an interrupt driven system.
๏It accepts request from the peripheral equipment,determines which of the incoming request is of the highest priority, ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination.
Register Organization of 8086, Architecture, Signal Description of 8086, Physical Memory
Organization, General Bus Operation, I/O Addressing Capability, Special Processor Activities,
Minimum Mode 8086 System and Timings, Maximum Mode 8086 System and Timings.
Addressing Modes of 8086.
Design of ring oscillator using controlled low voltage swing inverter khush_19
ย
Hello everyone. I am khushboo kumari.
I am pursuing M.tech from NIT Agartala(2017-2019). This is my 3rd semester partial project where i have successfully implemented the design of low voltage swing inverter. In the 4th semester i would be designing ring oscillator by connecting odd number of this inverter design in cascade.
I was able to complete this under the supervision of my respected guide Bidyut kumar .
Hope this presentation helps you to some extent.
Thank you.
Please do comment me if you have any doubts/ query/ or suggestions.
Threshold Voltage & Channel Length ModulationBulbul Brahma
ย
Design and Technology of Electronic Devices:
Review of microelectronic devices, introduction to MOS technology and related devices.
MOS transistor theory, scaling theory related to MOS circuits, short channel effect and its
consequences, narrow width effect, FN tunnelling, Double gate MOSFET, Cylindrical
MOSFET, Basic concept of CMOS circuits and logic design. Circuit characterization and
performance estimation, important issues in real devices. PE logic, Domino logic, Pseudo
N-MOS logic-dynamic CMOS and Clocking, layout design and stick diagram, CMOS
analog circuit design, CMOS design methods. Introduction to SOI, Multi layer circuit
design and 3D integration. CMOS processing technology: Crystal grown and Epitaxy, Film
formation, Lithography and Etching, Impurity doping, Integrated Devices.
This Presentation describes the ARM CORTEX M3 core processor with the details of the core peripherals. Soon a CORTEX base controller(STM32F100RBT6) ppt will be uploaded. For more information mail me at:gaurav.iitkg@gmail.com.
This presentation discusses the details of the I2C protocol and interfacing of EEPROM with 8051 based on I2C protocol. It also discusses the other applications of I2C protocol
This presentation has given a brief introduction and working of CMOS Logic Structures which includes MOS logic, CMOS logic, CMOS logic structure, CMOS complementary logic, pass transistor logic, bi CMOS logic, pseudo โnMOS logic, CMOS domino logic, Cascode Voltage Switch Logic(CVSL), clocked CMOS logic(cยฒmos), dynamic CMOS logic
Power Management in Embedded Systems โ Colin Walls
The importance of power management in todayโs embedded designs has been steadily growing as an increasing number of battery powered devices are developed. Often power optimizations are left to the very end of the project cycle, almost as an afterthought. In this presentation we will discuss design considerations that should be made when starting a new power sensitive embedded design, which include choosing the hardware with desired capabilities, defining a hardware architecture that will allow software to dynamically control power consumption, defining appropriate power usage profiles, making the appropriate choice of an operating system and drivers, choosing measurable power goals and providing these goals to the software development team to track throughout the development process.
Power reduction techniques are important for the modern VLSI designs. Power is the today's major concern when we come to optimal trade off between area, performance and power.
SOC, SOPC, MPSOC, ASIC are new VLSI approaches. Therefore power estimation and precise power calculation is vital to better understanding of Electronic world
Analysis of leakage current calculation for nanoscale MOSFET and FinFETIJTET Journal
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AbstractโThis paper presents logic level estimators of leakage current for nanoscale digital standard cell circuits. Here the proposed estimation model is based on the characterization of internal node voltages of cells and the characterization of leakage current in a single Field-Effect Transistor (FET). Finally the estimation model allowed direct implementation of supply voltage variation impact on leakage current and output voltage drop (loading effect).The technique is feasible for implementation in Hardware Description Language (HDL) and HDL cell models supporting leakage estimation at simulation time.
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Linaro Connect 2016 (BKK16) - Introduction to LISAPatrick Bellasi
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This presentation introduces the tutorial on the Linux Integrated System Analysis toolkit and provides a short description of its main modules. The tutorial is available on GitHub at this URL:
https://github.com/ARM-software/lisa/blob/master/ipynb/tutorial/00_LisaInANutshell.ipynb
The general purpose of operating systems like Linux, thanks to their predisposition to adapt easily to different application contexts, is a common choice for many new generation mobile devices. Being a key feature to improve mobility, energy efficiency has become a high priority design goal, and the implementation of the necessary mechanisms to optimize both power and performances can no longer be separated from the requirements of ease of development, portability and adaptability.
This work presents a formal model to define the problem of power vs performance control. We have proven that a distributed control is particularly suited to meet the goals of both adaptability and portability, without unduly compromising the effectiveness of control and its efficiency.
Starting from the current Linux solution we will advance the proposal for an extension that is better tailored to embedded mobile systems. The proposed solution has been implemented in a new Linux kernel framework named CPM which is competitive in adaptability and ensures better control on performances while still not affecting ease of implementation.
Cross-Layer Frameworks for Constrained Power and Resources Management of Embe...Patrick Bellasi
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Power and resource management are key goals for the success of modern battery-supplied multimedia devices. This kind of devices are usually based on SoCs with a wide range of subsystems, that compete in
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This presentation introduces Constrained Power Management (CPM), a cross-layer formal model and framework for power and resource management, targeted to MPSoC-based devices. CPM allows coordination and communication, among applications and device drivers, to reduce energy consumption without compromising QoS. A dynamic and multi-objective optimization strategy is supported, which has been designed to have a negligible overhead on the development process and at run-time.
Sources of Power Dissipation
Dynamic Power Dissipation
Static Power Dissipation
Power Reduction Techniques
Algorithmic Power Minimization
Architectural Power Minimization
Logic and Circuit Level Power Minimization
Control Logic Power Minimization
System Level Power Management.
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
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Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Analysis of Power Dissipation & Low Power VLSI Chip DesignEditor IJMTER
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Low power requirement has become a principal motto in todayโs world of electronics
industries. Power dissipation has becoming an important consideration as performance and area for
VLSI Chip design. With reducing the chip size, reduced power consumption and power management
on chip are the key challenges due to increased complexity. Low power chip requirement in the
VLSI industry is main considerable field due to the reduction of chip dimension day by day and
environmental factors. For many designs, optimization of power is important as timing due to the
need to reduce package cost and extended battery life. This paper present various techniques to
reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power
Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level
Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors,
Dynamic Threshold MOS, Short Circuit Power Suppression.
The project is designed to control the speed of a single phase induction motor in three steps by using cyclo convertor technique by thyristors. A.C. motors have the great advantages of being relatively inexpensive and very reliable.
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
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: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of โDeep submicron technologiesโ it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on โ64-bit SRAM array using leakage controlled transistor technique
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Power Gating Based Ground Bounce Noise ReductionIJERA Editor
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As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
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Back track input vector algorithm for leakage reduction in cmos vlsi digital ...VLSICS Design
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circuit has become a major constrain in a battery operated device for technology node below 90nm, as it
drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time
condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited
by stacking effect when the series transistors are maximized in OFF state condition. This method is
independent of process technology and does not require any additional power supply. This paper gives an
optimized solution of input pattern determination of some small circuit to find minimum leakage vector
considering promising and non-promising node which helps to reduce the time complexity of the algorithm.
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logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and
different logics respectively.
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We all have good and bad thoughts from time to time and situation to situation. We are bombarded daily with spiraling thoughts(both negative and positive) creating all-consuming feel , making us difficult to manage with associated suffering. Good thoughts are like our Mob Signal (Positive thought) amidst noise(negative thought) in the atmosphere. Negative thoughts like noise outweigh positive thoughts. These thoughts often create unwanted confusion, trouble, stress and frustration in our mind as well as chaos in our physical world. Negative thoughts are also known as โdistorted thinkingโ.
The Indian economy is classified into different sectors to simplify the analysis and understanding of economic activities. For Class 10, it's essential to grasp the sectors of the Indian economy, understand their characteristics, and recognize their importance. This guide will provide detailed notes on the Sectors of the Indian Economy Class 10, using specific long-tail keywords to enhance comprehension.
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1. Power Management
an embedded system perspective
Patrick Bellasi
Dipartimento di Elettronica ed Informazione
Politecnico di Milano
bellasi@elet.polimi.it
12/12/08
2. Agenda
๎ Introduction
๎ Basic Principles of Power Consumption
๎ Low Power Design
PM Techniques
Architectural Blocks for PM
2
3. Introduction
Why Low Power Design?
Why should we interest on Power Management?
It make us happy!?
The need of more and
more complex portable and
wireless applications requires
better effort on designing low
power system solutions
3
4. Introduction
Low Power Design Concerns
Cooling and
energy costs
Battery
lifetime
System
reliability
Environmental concerns
4
5. Introduction
Technology Trends
๎ Physical Gate Length decrease
new IC are manufactured using sub-micro production technology
process
=> increased sub-threshold leakage
๎ Transistors number increase
more and more transistors are integrated within single chips
=> higher power density
๎ Frequency increase
modern embedded systems could operate at hundreds MHz
๎ Performances increase
more and more complex operations delivered by single chip
๎ Battery discharge rate is super-linearly related to the
average power consumption in the VLSI circuits
excessive discharge rate and varying load conditions will have a
negative effect and shorten the battery life
5
6. Power Consumption
Leakage Components
๎ Main components I2
Gate
I1
Subthreshold Leakage I3
Gate Leakage
Junction Leakage Sourc Drain
e
๎ Other components
Gate Induced Drain Leakage
Impact Ionization current
๎ Overall and relative contribution depends on
technology node
Very Nano-scaled
Short Channel
Long Channel Short Channel L<90nm
L>180nm
L>1um L>90nm Tox<20Ao
Tox>30Ao
Tox>20Ao
Very Small Subthreshold +
Subthreshold
leakage Subthreshold + Gate + Junction
leakage
Gate leakage leakage
6
7. Power Consumption
Basic Principles
2
P = 0.5V DD f clock C L E sw ๎t sc V DD I peak f 0 ๎ 1๎V DD I l
๎ Switching (or dynamic) power
E sw represents the probability that the output
node makes a transition at each clock cycle
models the fact that, in general, switching does
not occur at the clock frequency
it is called the switching activity of the gate
๎ Short-circuit power
๎ Leakage (or stand-by) power
in older technologies (250nm and above) was marginal w.r.t.
switching power
in deep sub-micron processes becomes critical accounting for about
35-50% of power budget at 90nm
7
8. Power Consumption
Technology Scaling Effects on Power Consumption
๎ Higher device densities
smaller capacitance per gate to be charged
and discharged Increased
dynamic-power
โฆ but many more gates per chip consumptions
=> higher switched capacitance
๎ Higher clock frequencies
๎ Lower supply voltages
lower switching power, lower speed Increased
leakage-power
โฆ but lower threshold voltages consumptions
๎ Higher operating temperatures
8
10. Power Consumption
Architectural Power Reduction Approaches
2
P = 0.5V DD f clock C L E sw ๎t sc V DD I peak f 0 ๎ 1๎V DD I l
๎ Switching (or dynamic) power
reduce supply voltage
quadratic effect => higher savings
negative effect on performance
reduce clock frequency
reduce switched capacitance
reduce wasteful switching
๎ Short-circuit power
๎ Leakage (or stand-by) power
reduce supply voltage
๎ Many techniques apply at logical and physical level
10
11. Architectural Blocks for PM
Clock Domains
๎ Group of modules fed with the same gated clock
๎ Support clock gating
cut a clock to a group of inactive modules to lower their
active power consumption
two possible states: active or inactive
=> control of dynamic power consumption
11
12. Architectural Blocks for PM
Power Domains
๎ Section of the device with dedicated power rails
๎ Supplied by two voltage sources
VDD active voltage source (normal operating voltage)
VRET retention voltage source
less than active voltage => less power consumption
logic and memory are not operational, but their content or state is retained
๎ Retention state
in addition to on/off
useful for quickly switching to low-power idle mode without losing the
context and quickly switching back to active state when necessary
12
13. Architectural Blocks for PM
Voltage Domains
๎ Group of modules supplied by the same V regulator
power consumptions can be controlled by regulating
voltages independently
๎ Assign different operating V to the different modules
voltage scaling of device subsections
based on application performance requirements
๎ Lower voltage to reduce power consumption
when all modules are inactive
switch back to normal operating V
only when a wake-up event is
received
13
15. Device PM Architecture
Domains Hierarchical Architecture
๎ Scalable/switchable voltage domains
๎ Switchable power domains
๎ Switchable clock domains
subset of a power domain
15
16. Device PM Architecture
Interface and Functional Clocks
๎ Each module can have two type of clock
Interface clocks (ICLK) Functional clocks (FCLK)
ensure proper communication supply the functional part
supply the module interface and can have several or none at all
registers several modules can share the
can have several same
synchronous across the entire device
management is done at the device
level
16
17. Device PM Architecture
Auto-idle Clock Control
๎ Device can supports an auto-idle clock control scheme
for the module interface clocks (ICLK)
executes under hardware control
HW controller automatically activate/deactivate ICLK
๎ Two device module types
Initiator (e.g. uP, DMA, MMU)
can generate bus transactions (read, write, etc.)
active: when generates transactions
Target
passive module that can process bus transactions
active: when ICLK and some or all FCLK are available
๎ Idle modules can have ICLK gated
can still receive functional clocks
can generate interrupts, DMA requests, async wakeup-requests
17
18. Power Consumption
System Power Reduction Approaches
2
P = 0.5V DD f clock C L E sw ๎t sc V DD I peak f 0 ๎ 1๎V DD I l
๎ Switching (or dynamic) power
reduce supply voltage
quadratic effect => higher savings
negative effect on performance
reduce clock frequency
reduce switched capacitance
reduce wasteful switching
๎ Short-circuit power
๎ Leakage (or stand-by) power
reduce supply voltage
๎ Many techniques apply at logical and physical level
18
19. Power Management Techniques
DVFS - Dynamic Voltage and Frequency Scaling
๎ Allocate a variable amount of energy to perform a task
power consumption of a digital CMOS circuits
๎ท switching factor
C eff effectivecapacitance
P = ๎ทโ C effโ V 2โ f
V operating voltage
f operating frequency
energy required to run a task during T
E = Pโ T โV 2 ๎assuming f โV , T โ f โ1 ๎
Lowering V, while simultaneously and proportionately
cutting f, causes a quadratic reduction in E
19
20. Power Management Techniques
DVFS - Dynamic Voltage and Frequency Scaling
๎ Minimize system idle time
dynamic selection of optimal frequency and voltage
allow a task to be performed in the required amount of time
while still meeting task requirements
๎ Operating Performance Points (OPP)
a voltage (V) and frequency (F) pair
๎ The system always runs at the lowest OPP
that meets the performance requirement at
a given time
=> reduces both dynamic and leakage
power consumption
๎ We must be able to identify optimal OOP
20
21. Power Management Techniques
DPS - Dynamic Power Switching
๎ Maximize system idle time
Energy
automatic switch to a low-power mode consumed
1.3J
minimum power consumption
if wake-up latency conditions allow it
runs tasks at the highest OPP
complete tasks quickly
๎ Aimed at reducing active power
consumption Energy
consumed
reduces only leakage power consumption 1.15J
introduce transitions overhead
slight dynamic power consumption
exit-latency
๎ Must predict dynamical performance
requirement of applications
21
22. Power Management Techniques
SLM - Standby Leakage Management
๎ Trades static power consumption for wake-up latency
remains in lowest static power mode
compatible with the system response time requirement
๎ Similar to DPS
switching the system between high- and low-power modes
different operating timescales
latency allowed for mode transitions
DPS: compared to time constraints or deadlines of the application
SLM: compared to user sensitivity so that they do not degrade user experience
different context
who define the transition constraints
DPS: tasks are running and we must grant application performances
SLM: applications not running and must grant system responsiveness
different wake-up events
events used to exit the low-power mode
DPS: application-related, e.g. timer, DMA request, peripheral interrupt, ...
SLM: user-related, e.g. touch screen, key pressed, peripheral connections, ...
22
23. Power Management Techniques
AVC - Adaptive Voltage Control
๎ Provide automatic control of the operating voltage
๎ Silicon performances/power trade-off
depends on Power
consumed
technology process
operating temperature variations
๎ Power-supply voltage is adapted
to silicon performance
statically
based on performance points Operating
Voltage
dynamically variation
Performances
Point
based on the temperature-induced
real-time performance of the device
๎ Achieves optimal performance/power trade-off
for all devices and across the technology process spectrum and
temperature variations
23
24. Power Management Techniques
Combining PM Techniques
๎ PM techniques are most effective when used under
specific conditions
best active power saving is
obtained by combining them
AVC
boot-time: adapt voltage to device process
characteristics
always: compensate temperature variations
DVFS
varying application performances requirements
without DPS to scale F while keeping the V constant Operating Performances
Points
reduce peak power consumption
improve temperature dissipation and battery life
DPS
performance requirements between two OPPs or below the lowest OPP
with DVFS: always set F to max allowed at given V
SLM
no applications running and performance requirement drops to zero
24