EE270_Final_Project

EE270 Final Project P a g e | 1 Spring 2015
Eight-bit, Four-register Synchronous and Asynchronous FIFO
Jagbir Kalirai
Neha Mahajan
EE270 Final Design Project
Spring 2015
Due: May 11, 2015

Table of Contents:
Eight-bit, Four-register Synchronous and Asynchronous FIFO.....................................................................1
Table of Figures:............................................................................................................................................3
Executive Summary:......................................................................................................................................4
Roles for Each Team Member:......................................................................................................................5
How a Synchronous FIFO works:...................................................................................................................6
Netlist View of Synchronous circuit from Design Software:.................................................................7
Signals Involved:..................................................................................................................................10
How an Asynchronous FIFO works: ............................................................................................................11
General Asynchronous FIFO:...............................................................................................................11
Four Stage Asynchronous Pipelined Circuit........................................................................................13
Netlist View of Asynchronous circuit from Design Software:.............................................................17
Signals Involved:..................................................................................................................................20
Test Bench:..................................................................................................................................................21
Synthesis: ....................................................................................................................................................22
Timing, Area and Power......................................................................................................................22
Results Analysis and Simulations:...............................................................................................................24
VHDL code (with Testbench) for Synchronous FIFO:..................................................................................27
DFF: .....................................................................................................................................................27
Top Level Synchronous FIFO:..............................................................................................................28
Synchronous FIFO Test Bench.............................................................................................................29
Complete Synthesis (.srr) Report for Synchronous FIFO: ...........................................................................31
VHDL code (with Testbench) for Asynchronous FIFO:................................................................................36
Asynchronous Register: ......................................................................................................................36
Top Level Asynchronous FIFO:............................................................................................................38
Asynchronous FIFO Testbench:...........................................................................................................40
Complete Synthesis (.srr) Report for Asynchronous FIFO: .........................................................................48
SW Used:.....................................................................................................................................................53
References: .................................................................................................................................................54

Table of Figures:
Figure 1: Netlist block diagram representation of the Top level Synchronous FIFO circuit .........................7
Figure 2: Netlist of the Reg1 block within the Synchronous FIFO circuit......................................................8
Figure 3: Netlist of the Top Level Synchronous FIFO Circuit.........................................................................9
Figure 4: Shows each register block contains 8 DFF’s – one for each bit.....................................................9
Figure 5: FIFO full and empty conditions....................................................................................................12
Figure 6: Simplified micropipeline stage based no transparent latches and a two-to-four-phase interface
....................................................................................................................................................................13
Figure 7: Block diagram of Asynchronous FIFO Circuit Pipeline .................................................................14
Figure 8: Block diagram representation of a four stage Asynchronous FIFO Circuit Pipeline....................15
Figure 9: The two-phase signaling protocol................................................................................................15
Figure 10: Netlist block diagram representation of the Top level Asynchronous FIFO circuit ...................17
Figure 11: Close up view for Netlist block diagram representation of the Top level Asynchronous FIFO
circuit ..........................................................................................................................................................17
Figure 12: Netlist of the Reg1 block within the Asynchronous FIFO circuit................................................18
Figure 13: Netlist of the Top Level Asynchronous FIFO Circuit...................................................................19
Figure 14: Content of each register block within the Asynchronous Circuit ..............................................20
Figure 15: Synchronous circuit slack from synthesis report.......................................................................22
Figure 16: Synchronous Circuit Area Usage................................................................................................23
Figure 17: Asynchronous Circuit Area Usage..............................................................................................23
Figure 18: Simulation output of Synchronous ............................................................................................24
Figure 19: Data from Synchronous Circuit takes 4 clock cycles to output..................................................24
Figure 20: Output data from Asynchronous Circuit....................................................................................25
Figure 21: Zoomed view of the area circled in red of Asynchronous FIFO output waveform....................25
Figure 22: Zoomed view of the area circled in purple of Asynchronous FIFO output waveform...............26

Executive Summary:
A First In - First out (FIFO) circuit passes the first given input into the first register (in an array for four
registers), and this data appears as the first output. The process is then repeated for the next packets of
8-bit data. We used two types of circuits (Synchronous and Asynchronous) to perform the FIFO
function. A Synchronous FIFO circuit utilizes a clock to pass the data through the registers. Since the
Asynchronous FIFO circuit does not have a clock signal, we implement the Muller circuit (C-Element) to
act as the clock. The report contains the full description of how these FIFO circuits work, how they’re
made and how the FIFO’s were tested to confirm their functionality. The report also contains the
complete details for the timing, area and the power consumption of the circuits.

Roles for Each Team Member:
Overall this project was a team effort. Jag and Neha met for four consecutive weekends to research and
complete the design for this project, and to complete the report. Some tasks were divided up to make
for efficient use of time. Neha worked on coding the Synchronous FIFO while Jag worked on the coding
of the Asynchronous FIFO. The test bench for the Synchronous and Asynchronous FIFO’s were created as
a joint effort, where Jag worked on writing the test bench for the Synchronous FIFO and Neha worked
on the Asynchronous test bench enabling them to completely understand the working of the design that
the other wrote.
Since Jag works at Microsemi, using the Libero Design suite was the ideal choice for the circuit design,
and Synopsys VCS was used to obtain the timing, area, and power figures. The simulation, synthesis, and
RTL level representations were created by Jag. Neha learned how to use the tool as well, and ran
through the design process for the Synchronous and Asynchronous FIFO to confirm the results. The
logical level representation of the Asynchronous FIFO was created by Neha.
The report contents were divided up equally. Both team members were involved in the analysis, and
final review to ensure all of the presented data was accurate and the report was well laid out without
any errors.

How a Synchronous FIFO works:
The purpose of a FIFO is to pass the first given input as the first output, second input as the second
output, etc... What makes the circuit synchronous is the use of a clock (clk signal).
The Synchronous FIFO circuit that we designed contains four register blocks each of which contain eight
D-Flip Flops (DFF). A Flip Flop can store one bit of information at a time. The DFF works by passing the
same input as its output, ie: the logic within the DFF does not toggle, set, or reset the input signal.
The clk signal for our circuit has a period of 20 nano-seconds (ns), and is positive edge triggered. This
means the clock will only recognize the data during the rising edge of the clock. If the data were to
change within the 20ns period, the clk will not recognize the data until the next positive edge trigger –
this assumes the data hasn’t changed to a new value before the next positive edge of the clock.
One limitation of the Synchronous FIFO circuit is the speed at which the circuit can be operable. Let’s
assume the four ‘Reg’ blocks contain logic that takes different amount of time to process the signals
(10ns, 9ns, 15ns, and 17ns). We can see the first two registers can process the data within 10ns,
however our clk signal must be clocked at a minimum of 17ns to allow for a circuit without any timing
violations. This would ensure the data can be fully processed through each ‘Reg’ block during the same
clock period – keeping the process synchronized. A Synchronous FIFO circuit must be clocked depending
on the slowest block that processes the information.
During the positive edge of the clock, an 8-bit binary number is passed into the first Register block
(Reg1). In the next clock cycle, the data within Reg1 is transferred to Reg2, while at the same time a new
8-bit binary number is passed into Reg1. This process is repeated until the data that was first entered
into Reg1 is outputted out of Reg4. As we can see, there will be a delay from the time the data is first
inputted, to when it is first outputted. This delay can be observed in Figure 19.

Netlist View of Synchronous circuit from Design Software:
Figure 1: Netlist block diagram representation of the Top level Synchronous FIFO circuit

Figure 2: Netlist of the Reg1 block within the Synchronous FIFO circuit

Figure 3: Netlist of the Top Level Synchronous FIFO Circuit
Figure 4: Shows each register block contains 8 DFF’s – one for each bit

Signals Involved:
The Top level of the Synchronous circuit contains a few basic signals: 8-bit input, 8-bit output, and clock.
8-bit input (input):
This is the data that is inputted into the FIFO at a given rising edge of the clock. This data is in 8-bit
binary format.
8-bit output (output):
This is the data that is outputted from the last Register block. This data can be seen in Figure 19 in
hexadecimal (hex) format.
Clock (clk):
The clock for our circuit was positive edge triggered, and determines when the data can be read.

How an Asynchronous FIFO works:
General Asynchronous FIFO:
A FIFO is a digital circuit that is used for safe transmission of data, usually from one clock domain to
another asynchronous clock domain. That is, a block of data is sent to the FIFO memory from one clock
domain and that stored data is read back from the same FIFO by a different clock domain, with the two
clock domains being asynchronous with each other. This is usually achieved by placing the data block
into the FIFO memory with the help of control signals in one clock domain and control signals from the
other clock domain are used to retrieve the stored data from the FIFO memory from the output port of
the FIFO.
In order to ensure that incoming data is written to the right place in the FIFO memory and correct data
is read back from the same memory, we implement write and read pointers in the FIFO. The write
pointer points to the location in the memory for the next word to be written. Thus on a write operation
to the FIFO, data is written to the memory location that is pointed to by the write pointer and the write
pointer is incremented to point to the next memory location.
The read pointer points to the location in the memory where the current word to be read resides. At
reset, both the read and write pointers are set to zero as the FIFO is empty and thus the read pointer
refers to invalid data and the write pointer is pointing to the first memory location and also the empty
flag is asserted at this time. When the first data is written to the FIFO, the write pointer increments thus
pointing to the next location to be written, the empty flag is de-asserted and the read pointer that is
pointing to the first memory location makes the first data available to the output port of the FIFO to be
read if needed.
The FIFO is empty when both the read pointer and the write pointer address the same memory location,
like when both the pointers are initialized during reset or when the last written word is read from the
FIFO and the read pointer catches up to the write pointer. The FIFO is full, again when both the pointers
are equal, in the case where the write pointer has wrapped around and caught up with the read pointer.
This gives rise to a problem as we are unable to distinguish between the cases where the FIFO is full or
empty.
One way to overcome this ambiguity is to add an extra bit to the read and write pointers. Using this,
whenever the write pointer moves past the last FIFO address, it will toggle that extra bit and will reset
the rest of its bits back to zero. The read pointer follows the same technique. If the MSBs of the two
pointers are the same then that would mean that the pointers have wrapped the same number of times
and the FIFO is empty and if the MSBs of the two pointers are different, that means that the write
pointer has wrapped one more time than the read pointer and hence the FIFO is full.

Figure 5 shown below depicts the procedure described above:
Figure 5: FIFO full and empty conditions
1
This Design of the Asynchronous FIFO makes sure that the data transferred is correctly retrieved by the
receiver taking into consideration the fact that reads and writes are performed by two different clock
domains.
1
Cummings, Clifford E., and Sunburst Design. "Simulation and Synthesis Techniques for Asynchronous FIFO Design

Four Stage Asynchronous Pipelined Circuit
In our project, we have to design and implement an asynchronous pipeline circuit using FIFOs as storage
elements to securely transfer data from one stage to the other. The circuit has four pipelined stages and
data is sent at the input of the first stage and is retrieved from the output port of the last stage.
The pipelined circuit is asynchronous, that is, the transfer of data and control signals between individual
stages of the pipeline is not regulated with the occurrence of a single global event like a clock. Here, the
communication of data between stages is managed by the implementation of local handshaking signals
between stages. Whenever a stage needs to send data to the next stage, it initiates this process by first
sending a request signal to the next stage indicating it has data available at its output port. If the next
stage is allowed to accept this data, it does so and sends back an acknowledge signal to the stage that
initiated the data transfer.
Based on this idea, we will be developing an asynchronous pipeline circuit using standard latches with
level sensitive enables as storage elements to transfer data from one stage to the other. In order to
integrate these latches into the design efficiently, we need to build an interface around these level
sensitive latches.
Let us take a look at building one such latch-interface which will be replicated in all the four stages as
the storage element.
Figure 6: Simplified micropipeline stage based no transparent latches and a two-to-four-phase interface
2
2
Yun, Kenneth Y., Peter A. Beerel, and Julio Arceo. "High-Performance Asynchronous Pipeline Circuits."

The working of the four stage Asynchronous pipeline design will be as follows:
 At the start, all the wires except for the latch enable are low and the latch is transparent, that is,
the latch will allow its output to follow the input while it is in the active state.
 An activity is initiated when the input Rin rises and this leads to the C-element output to also
rise. This rise propagates through the XOR gate and causes En to become high and the latch is
now closed.
 Also, the toggle element senses the XOR gate transition and it changes the dot output, making
sure that it occurs only when the latches are no longer open.
 This further gives rise to the transition of Ain to high signaling to the previous stage of the
pipeline that the input data is not required at this stage and it also drives Rout to high signaling
that the output data from the current stage is ready to be processed to be sent out to the next
stage.
 After the next stage latches the data sent by this current stage, it changes Aout which is an input
to this stage and it propagates through the XOR gate and opens the latch.
 The toggle element now detects this change of event and changes the blank output which in
turn prepares the C-element for the next Rin event.
This latch-interface FIFO structure is now used at each of the four stages of the pipeline circuit as a
memory element. Let us understand the working of the pipeline circuit now.
As stated earlier, the transfer of data correctly from one stage to the other in the asynchronous pipeline
circuit is made with the help of handshaking control signals. Thus the interface between stage i and
stage i+1 encompasses a group of data that carries information and a request signal. Whenever the
request signal changes and is sensed at stage i+1, this signals the availability of new data the input of
stage i+1.
The implementation of this request – acknowledge communication can be depicted as follows:
Figure 7: Block diagram of Asynchronous FIFO Circuit Pipeline
3
3

The equivalent representation of this circuit with our latch-interface memory elements in the place of
the registers is shown in Figure 8 below:
Figure 8: Block diagram representation of a four stage Asynchronous FIFO Circuit Pipeline
In this implementation, the neighboring stages communicate with each other by two wires, one for
request and the other wire for acknowledgement. The request wire is denoted by Rout at the output of
stage i and Rin at the input of the stage i+1. In the same manner, the acknowledge wire is denoted by
Ain at the input of stage i+1 and as Aout at the output of the stage i. The handshaking protocol observed
by the circuit is two phase that is, both low to high and high to low transitions on a signal are identified
as events and mean the same.
The signaling protocol followed is depicted below in Figure 9:
Figure 9: The two-phase signaling protocol
4
4

At a single stage, the order of the events that take place is as follows. Whenever data becomes available
at the input of any stage, at the beginning of the data transfer, Rin will rise signaling the availability of
the new data. Now, if the FIFO is empty and ready to take the data, the input data will be latched. After
it stores the data, this stage will raise its Ain signaling to the previous stage that it is no longer in need of
that data. After the delay overhead involved with the XOR and toggle elements, the current stage will
raise Rout indicating the availability of new data to the subsequent stage. Again after some delay after
Rout rises, the next stage will raise its Aout signaling to this stage that it has saved the output data. At
the same time, the previous stage can now lower Rin signaling that a new data is available to be
transferred and this entire process can be repeated again. It is important to note that new input data
can begin to be transferred only it is available and the previously stored data has been successfully
transferred to its subsequent stage, thus preventing data loss. This condition is made sure to be
followed by the C-element.

Netlist View of Asynchronous circuit from Design Software:
Figure 10: Netlist block diagram representation of the Top level Asynchronous FIFO circuit
Figure 11: Close up view for Netlist block diagram representation of the Top level Asynchronous FIFO circuit

Figure 12: Netlist of the Reg1 block within the Asynchronous FIFO circuit

Figure 13: Netlist of the Top Level Asynchronous FIFO Circuit

Figure 14: Content of each register block within the Asynchronous Circuit
Signals Involved:
The Top level of the Asynchronous circuit contains a few basic signals: 8-bit data input, 8-bit data
output, Rin, Ain, Rout, and Aout.
8-bit input (Data_in_Top):
This is the data that is inputted into the FIFO at a given rising edge of the Rin signal. This data is in 8-bit
binary format.
8-bit output (Data_out_Top):
This is the data that is outputted from the last Register block. This data can be seen in Figures 21 and 22
in hexadecimal (hex) format.
Rin, Rout:
Rout is a signal which is an output from stage i of the pipeline and it acts as an indicator to the
subsequent stage that stage i has new data available for it. Rout becomes Rin as an input signal to stage
i+1, again indicating that it has new data available at the stage's input.
Ain, Aout:
Ain is the output signal from stage i+1 which becomes Aout as the input signal to stage i, and it acts as
an indication to stage i that stage i+1 has successfully latched its data and no longer needs it.

Test Bench:
A testbench allows the designer to verify the functionality of the design without actually burning it to
the hardware. When creating a design, you are only designing the sub-blocks within the Top level
module. However, at this point you will not be able to determine the behavior of the circuit. The ports of
the top level module are still unconnected and do not have signals telling the circuit what to do.
The testbench for the Synchronous and Asynchronous circuit provides modifiable signals that can be
used to test the functionality of the circuit.
When creating a testbench, the designer must map the ports from the top level design (or whichever
block he chooses to test) to the testbench ports. In the case of the Synchronous circuit (as an example),
the following highlighted top level Synchronous ports are connected to the testbench ports:
signal clk : std_logic := ‘0’;
signal input : std_logic_vector(7 downto 0) := (others => ‘0’);
signal output : std_logic_vector(7 downto 0);
From the code mentioned above, we specify the input and output ports to be 8 bits each. Below, we can
see the ‘port mapping’ – this is where we connect the clk port of the top level module to the clk port of
the test bench module. Similarly, we do this for the input and output signals.
clk => clk,
input => input,
output => output
Once we complete the port mapping, we need to set the initial states for the input signals (clk and
input). In this case we have set the initial values of the 8-bit input signals to be ‘0’. We then need to
define the clock frequency to determine how to data will be passed through the circuit. Once the clock
frequency is defined, we can choose how long the clock stays in a high or low state for.
After setting the initial states, and defining the characteristics of the clock, we are ready to input
different values for the inputs at different times. The snippet of code shown below shows how to enter
a FF value and hold that value for 200 ns.
input <= "11111111"; --FF
wait for 200 ns;
Now that the testbench is created, we can confirm the VHDL code is error free and run the simulation
on a software tool such as Synopsys VCS simulator or ModelSim. The Synopsys VCS simulator
simulations are shown in the “Results Analysis and Simulations” section of the report.

Synthesis:
When synthesizing a design there are two critical variables that the designer may choose to optimize:
Area and Timing.
Area is the amount of chip/silicon resources the design will use; this is typically measured in Look-up
Tables (LUT) or the number of Gates. The positioning of the gates can alter the power consumption as
well. Generally speaking, there is a tradeoff between area and power, the wider you spread the logic
cells, the more efficient the design will be in terms of power, but you will be using more area on the
silicon.
Timing analysis is determined by the amount of gates your design uses. Typically, the more gates you
use, the longer it will take the signal to propagate through the design. A few important factors when
discussing timing are the clock skew and slack. Clock skew is the difference between the source clock
and another area within the circuit that uses the same clock signal. As the clock signal propagates
through the circuit, it gets delayed, this causes the timing of the clock to be slightly offset – this is what
we call the clock skew. Slack is used to define timing critical paths (longest path in terms of timing) in a
design using static timing analysis. Slack can be used to optimize the timing since it tells you the path
which takes the longest to propagate; this can be translated to the fastest clock for the particular circuit.
Since there were no constraints for timing, area, or power in this project, none of these values were
optimized through the software. However, the sections below discuss the timing, area and power
qualities for the Synchronous and Asynchronous FIFO circuits.
Timing, Area and Power
For the Synchronous FIFO circuit, the clock period was set to 10 ns. From this, we deduct the setup time
and any propagation delays and our critical slack becomes 8.368 ns. This means we can clock the circuit
faster by 8.368 ns without running into any timing violations. Below is a snippet from the timing report
for the Synchronous circuit.
Figure 15: Synchronous circuit slack from synthesis report

Since the Asynchronous FIFO circuit doesn’t utilize a clock, the same information was not available
through the synthesis report. However, through the implementation of the Muller Circuit, we were able
to implement the circuit at a period of 50ns, which equivalents to 20MHz.
For the Synchronous circuit, the design used 32 core (logic) cells, and would utilize 17 I/O ports (8 for
input, 8 for output, and 1 for clock). Similarly, for the Asynchronous design it utilizes 44 core cells, and
20 I/O cells. The following two figures below show a snippet of the Synchronous and Asynchronous area
usage.
Figure 16: Synchronous Circuit Area Usage
Figure 17: Asynchronous Circuit Area Usage
As for power, the Synchronous circuit prooved to be more efficient as it used only 395 uW compared to
the 512 uW the Asynchronous Circuit used.
A complete summary of the synthesis report for the Synchronous and Asynchronous FIFO circuits is
available in their respective sections toward the end of the report.

Results Analysis and Simulations:
The results for this project are what we expected them to be. The following paragraphs along with the
simulation output waveform screen captures will be used to explain the results for the Synchronous and
Asynchronous FIFO.
For the Synchronous circuit and Asynchronous circuit data (let’s call it data_1) is passed into the first
register (Reg1) during the first clock cycle. During the next clock cycle, the data_1 goes into Reg2, and
new data (data_2) is passed into Reg1. This process is repeated until data_1 is outputted from Reg4.
Here we can see the first data that was inputted, is the first data that is outputted. Because our circuits
have four registers, it takes four clock cycles for us to see the data at the output stage.
Figure 18 below shows the waveforms for the Synchronous FIFO circuit. The first waveform in the figure
is our clock (clk), which is toggling at a period of 20ns. The next waveforms we see are the input signals,
followed by the output signals.
Figure 18: Simulation output of Synchronous
Figure 199 shows a close up view of the waveforms. FF is the first value passed into Reg1. From Figure
19, we can clearly see that it takes four clock cycles to see the value appear in the output. This is true for
the following values as well. This proves to us the Synchronous FIFO circuit is functioning properly.
Figure 19: Data from Synchronous Circuit takes 4 clock cycles to output

Figures 20 through 22 below show the waveforms of the Asynchronous FIFO circuit. Since the
Asynchronous FIFO doesn’t have a clk signal, we use R_in to act as the clock. The R_in signal is controlled
through the testbench where we are able to determine the amount of time the signal is in a high and
low state. The data gets processed when R_in is high since the R_in signal is active high.
From observing Figure 13, we can see the R_in signal was in the high and low states for the same
amount of time for the first half of the waveform (circled in red). In the second half of the waveform,
the signal is in the high and low states for different periods of time (show in purple circle). Varying the
period of the signal was done to show the data still passes through the FIFO circuit. D_in and D_out
represent the Data going into the first register block, and coming out of the last register block,
respectively.
Figure 20: Output data from Asynchronous Circuit
From Figure 21 below (the expanded view of the area circled in red from Fig. 20), we can see the R_in
signal is clocked periodically at 20ns. Each time a signal is pushed into Reg1, it takes exactly four clock
cycles for the data to be pushed to the output.
Figure 21: Zoomed view of the area circled in red of Asynchronous FIFO output waveform

Figure 22 (below) shows the expanded view of the area circled in purple from Fig. 20. The purpose of
showing this is to show the R_in signal can be high or low for different amounts of time. The FIFO circuit
still works as it should – taking four cycles for the data to show up at the output.
Figure 22: Zoomed view of the area circled in purple of Asynchronous FIFO output waveform

VHDL code (with Testbench) for Synchronous FIFO:
DFF:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Define I/O's of DFF
entity DFF is
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (7 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0));
end DFF;
--Process to set the clock characteristics.
--DFF becomes Synchronous with the introduction of a clock
architecture Behavioral of DFF is
--Defines the behavior of the DFF.
begin
process(clk)
begin
if ( rising_edge(clk) ) then
Q <= D;
end if;
end process;
end Behavioral;

Top Level Synchronous FIFO:
library IEEE;
--Creating the Top Level Architecture of one register containing 8 DFF's
--7 downto 0 represents 8 bits in each Register block
entity FIFO_4reg_8bits is
Port ( clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0));
end FIFO_4reg_8bits;
--Will use 4 registers, each contains 8 DFF's
architecture Behavioral of FIFO_4reg_8bits is
--Instanciating a DFF
component DFF
port (
D : in STD_LOGIC_VECTOR (7 downto 0);
Q : out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC );
end component;
--'Signal' represents wires interconnecting each Register block within the top level module
signal W1,W2,W3 : std_logic_vector(7 downto 0);
begin
--Format:
--Block name: DFF (input, output, clock);
Reg1: DFF port map(input,W1,clk);
Reg2: DFF port map(W1,W2,clk);
Reg3: DFF port map(W2,W3,clk);
Reg4: DFF port map(W3,output,clk);
end Behavioral;

Synchronous FIFO Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FIFO_4reg_8bits_TB is
END FIFO_4reg_8bits_TB;
ARCHITECTURE behavior of FIFO_4reg_8bits_TB is
-- Declare the component for the Unit Under Test (UUT)
COMPONENT FIFO_4reg_8bits
PORT(
clk : in std_logic;
input : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Defining Inputs Outputs
signal clk : std_logic := '0';
signal input : std_logic_vector(7 downto 0) := (others => '0');
signal output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
--Assigning equivalent ports from Design to TB
uut: FIFO_4reg_8bits PORT MAP (
clk => clk,
input => input,
output => output
);
-- Clock process definitions
--Clock starts at 0, and toggles every clk_period/2 (10ns)
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold state for 200 ns.
input <= "11111111"; --FF
wait for 200 ns;
input <= "11101110"; --EE
wait for 200 ns;
input <= "11011101"; --DD
wait for 200 ns;
input <= "11001100"; --CC
wait for 200 ns;
input <= "10111011"; --BB
wait for 200 ns;
wait for clk_period*4;
wait;
end process;
END;

Complete Synthesis (.srr) Report for Synchronous FIFO:
Readings from the .srr report after synthesizing the design
Performance Summary
*******************
Worst slack in design: 8.368
Requested Estimated Requested
Estimated Clock Clock
Starting Clock Frequency Frequency Period
Period Slack Type Group
----------------------------------------------------------------------
----------------------------------------------------
FIFO_4reg_8bits|clk 100.0 MHz 612.8 MHz 10.000
1.632 8.368 inferred Inferred_clkgroup_0
======================================================================
====================================================
Clock Relationships
*******************
Clocks | rise to rise |
fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------
----------------------------------------------------------
Starting Ending | constraint slack |
constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------
----------------------------------------------------------
FIFO_4reg_8bits|clk FIFO_4reg_8bits|clk | 10.000 8.368 | No
paths - | No paths - | No paths -
======================================================================
==========================================================
Note: 'No paths' indicates there are no paths in the design for that
pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock
and ending clock are in different clock groups.
Interface Information
*********************

No IO constraint found
====================================
Detailed Report for Clock: FIFO_4reg_8bits|clk
====================================
Starting Points with Worst Slack
********************************
Starting
Arrival
Instance Reference Type Pin Net Time
Slack
Clock
----------------------------------------------------------------------
------------
Reg3.Q[0] FIFO_4reg_8bits|clk DFN1 Q W3[0] 0.737
8.368
8.368
8.368
8.368
8.368
8.368
8.368
8.368
8.368
8.368
======================================================================
============
Ending Points with Worst Slack
******************************
Starting
Required
Instance Reference Type Pin Net Time
Slack

Clock
----------------------------------------------------------------------
-------------
Reg4.Q[0] FIFO_4reg_8bits|clk DFN1 D W3[0] 9.427
8.368
8.368
8.368
8.368
8.368
8.368
8.368
8.368
8.368
8.368
======================================================================
=============
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.573
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.427
- Propagation time: 1.058
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 8.368
Number of logic level(s): 0
Starting point: Reg3.Q[0] / Q
Ending point: Reg4.Q[0] / D
The start point is clocked by FIFO_4reg_8bits|clk
[rising] on pin CLK
The end point is clocked by FIFO_4reg_8bits|clk
[rising] on pin CLK
Instance / Net Pin Pin Arrival No.
of

Name Type Name Dir Delay Time Fan
Out(s)
----------------------------------------------------------------------
-------
Reg3.Q[0] DFN1 Q Out 0.737 0.737 -
W3[0] Net - - 0.322 - 1
Reg4.Q[0] DFN1 D In - 1.058 -
======================================================================
=======
Total path delay (propagation time + setup) of 1.632 is 1.310(80.3%)
logic and 0.322(19.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-
to-out value, and is subtracted from setup time value
##### END OF TIMING REPORT #####]
----------------------------------------------------------------------
----------
Target Part: AFS600_PQFP208_STD
Report for cell FIFO_4reg_8bits.behavioral
Core Cell usage:
cell count area count*area
GND 5 0.0 0.0
VCC 5 0.0 0.0
DFN1 32 1.0 32.0
----- ----------
TOTAL 42 32.0
IO Cell usage:
cell count
CLKBUF 1
INBUF 8
OUTBUF 8
-----
TOTAL 17
Core Cells : 32 of 13824 (0%)
IO Cells : 17
RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)
Global Operating Voltage = 3.3V
Power-Specific unit information:
Voltage units = 1V

Capacitance Units = 1.000000ff
Time units = 1ns
Dynamic Power Units = 1uW (derived from V,C,T units)
Leakage Power Units = Unitless
Cell Internal Power = 393.4714 uW (100%)
Net Switching Power = 1.7854 uW (0%)
--------
Total Dynamic Power = 395.2568
Cell Leakage Power = 0.0000
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed
0h:00m:00s; Memory used current: 47MB peak: 111MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Apr 25 21:45:00 2015
###########################################################]

VHDL code (with Testbench) for Asynchronous FIFO:
Asynchronous Register:
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: Async_FIFO_reg.vhd
-- File history:
-- <Revision number>: <Date>: <Comments>
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::Fusion> <Die::AFS600> <Package::208 PQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library IEEE;
--Define ports of Async Reg
entity Async_FIFO_reg is
Port ( R_in : in STD_LOGIC;
A_out : in STD_LOGIC;
A_in : out STD_LOGIC;
R_out : out STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
D_out : out STD_LOGIC_VECTOR (7 downto 0));
end Async_FIFO_reg;
--Define behavior of one Async Reg
architecture Behavioral of Async_FIFO_reg is
begin
process(R_in, A_out)
--Statement for the process
begin
if ( R_in = '1' )
--This clocks the process

then
D_out <= D_in;
A_in <= '1';
R_out <= '1';
else if ( A_out = '1' )
then
R_out <= '0';
A_in <= '0';
end if;
end if;
end process;
end Behavioral;

Top Level Asynchronous FIFO:
--------------------------------------------------------------------------------
-- Company: <Name>
--
-- File: Async_Top.vhd
-- File history:
--
-- Description:
--
-- <Description here>
--
-- Targeted device: <Family::Fusion> <Die::AFS600> <Package::208 PQFP>
-- Author: <Name>
--
--------------------------------------------------------------------------------
library IEEE;
--Define top level ports of Async FIFO block
--Design contains 8 Async FIFO reg's
entity Async_Top is
Port ( R_in_Top : in STD_LOGIC;
A_in_Top : out STD_LOGIC;
A_out_Top : in STD_LOGIC;
R_out_Top : out STD_LOGIC;
D_in_Top : in STD_LOGIC_VECTOR (7 downto 0);
D_out_Top : out STD_LOGIC_VECTOR (7 downto 0));
end Async_Top;
--Describe architecture of sub-blocks
architecture Behavioral of Async_Top is
--Instanciate Async register
component Async_FIFO_reg
port (
R_in : in STD_LOGIC;
A_in : out STD_LOGIC;
A_out : in STD_LOGIC;
R_out : out STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
D_out : out STD_LOGIC_VECTOR (7 downto 0));

end component;
--Wires connecting the sub-blocks
signal Data_1,Data_2,Data_3 : STD_LOGIC_VECTOR(7 downto 0);
signal R_1, R_2, R_3 : STD_LOGIC;
signal A_1, A_2, A_3 : STD_LOGIC;
begin
Reg1: Async_FIFO_reg port map(R_in_Top, A_in_Top, A_1, R_1, D_in_Top, Data_1);
Reg2: Async_FIFO_reg port map(R_1, A_1, A_2, R_2, Data_1, Data_2);
Reg3: Async_FIFO_reg port map(R_2, A_2, A_3, R_3, Data_2, Data_3);
Reg4: Async_FIFO_reg port map(R_3, A_3, A_out_Top, R_out_Top, Data_3, D_out_Top);
end Behavioral;

Asynchronous FIFO Testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Async_Top_TB IS
END Async_Top_TB;
ARCHITECTURE behavior OF Async_Top_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Async_Top
PORT(
R_in_Top : IN std_logic;
A_in_Top : OUT std_logic;
A_out_Top : IN std_logic;
R_out_Top : OUT std_logic;
D_in_Top : IN std_logic_vector(7 downto 0);
D_out_Top : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Outputs
signal A_in_Top : std_logic;
signal R_out_Top : std_logic;
signal D_out_Top : std_logic_vector(7 downto 0);
--Inputs
signal A_out_Top : std_logic := '0';
signal R_in_Top : std_logic := '0';
signal D_in_Top : std_logic_vector(7 downto 0) := (others => '0');
-- No clocks in used port list.
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test UUT (Unit Under Test)
uut: Async_Top PORT MAP (
R_in_Top => R_in_Top,
A_in_Top => A_in_Top,
A_out_Top => A_out_Top,
R_out_Top => R_out_Top,
D_in_Top => D_in_Top,

D_out_Top => D_out_Top
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 50 ns.
wait for 50 ns;
-- Total time before data inputted is 150ns
-- Toggle R_in_Top & insert FEh for data input
R_in_Top <= not(R_in_Top); --Makes Rin high
D_in_Top <= "11111110"; --FE entered while Rin is high
wait for 10 ns; -- Rin stays high for 10ns
R_in_Top <= not(R_in_Top); -- Rin is now low
--
wait for 10 ns; -- Rin Stays low for 10ns
R_in_Top <= not(R_in_Top); -- Rin toggles high
-- 1 clock cycle
R_in_Top <= not(R_in_Top); -- Rin toggles low
wait for 10 ns; -- Rin Stays low for 10ns
-- 2nd clock cycle
-- Change data input to CB while clock is high
D_in_Top <= "11001011"; --CB
----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------

wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------
-- Change data input to CB while clock is high
D_in_Top <= "10000100"; --84
----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------
-----------------------------------------------------
-- Change data input to AE while clock is high
D_in_Top <= "10111110"; --AE
-----------------------------------------------------

wait for 10 ns;
-- After one clock cycle, change data input to 45
D_in_Top <= "00100101"; --45
----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
-- After one clock cycle, change data input to 94
D_in_Top <= "10010100"; --94
-----------------------------------------------------
wait for 10 ns;
-- After one clock cycle, change data input to 3D
D_in_Top <= "00111101"; --3D
-----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
-- After one clock cycle, change data input to EA
D_in_Top <= "11101010"; --EA
-----------------------------------------------------
----------------------------------------------------
wait for 10 ns;

wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------
----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------
wait for 10 ns;
wait for 10 ns;
wait for 10 ns;
-----------------------------------------------------

-----------------------------------------------------
-----------------------------------------------------
--Now, we will demonstrate when the clock stays high and
--low for different amounts of time.
-----------------------------------------------------
-----------------------------------------------------
-- After two clock cycles, change data input to 09
D_in_Top <= "00001001"; --09
----------------------------------------------------
wait for 10 ns;
wait for 30 ns;
wait for 10 ns;
-----------------------------------------------------
D_in_Top <= "00000110"; --06
----------------------------------------------------
wait for 20 ns;
wait for 10 ns;
wait for 15 ns;
-----------------------------------------------------
D_in_Top <= "00011001"; --19
----------------------------------------------------

wait for 20 ns;
wait for 15 ns;
wait for 25 ns;
-----------------------------------------------------
D_in_Top <= "10001000"; --88
----------------------------------------------------
wait for 15 ns;
wait for 40 ns;
wait for 30 ns;
-----------------------------------------------------
----------------------------------------------------
wait for 20 ns;
wait for 25 ns;
wait for 15 ns;
-----------------------------------------------------
----------------------------------------------------

wait for 25 ns;
wait for 10 ns;
wait for 15 ns;
-----------------------------------------------------
----------------------------------------------------
wait for 15 ns;
wait for 25 ns;
wait for 10 ns;
-----------------------------------------------------
--Ran several clock cycles to ensure the last D_in bit
--Can be processed through to the output
wait;
end process;
END;

Complete Synthesis (.srr) Report for Asynchronous FIFO:
#### START OF CLOCK OPTIMIZATION REPORT #####[
Clock optimization not enabled
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of
sequential element(s)
3 gated/generated clock tree(s) driving 24 clock pin(s) of sequential
element(s)
0 instances converted, 24 sequential instances remain driven by
gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks
============================
Clock Tree ID Driving Element Drive Element Type Fanout
Sample Instance
----------------------------------------------------------------------
-----------------
@K:CKID0004 R_in_Top port 8
Reg1.D_out[7]
======================================================================
=================
======================================================================
Gated/Generated Clocks
======================================================================
Clock Tree ID Driving Element Drive Element Type Fanout
Sample Instance Explanation
----------------------------------------------------------------------
----------------------------------------------------------------------
------------------------
@K:CKID0001 Reg1.R_out_1 DLN1P1C1 8
Reg2.D_out[7] No generated or derived clock directive on output
of sequential instance
======================================================================
======================================================================
========================
##### END OF CLOCK OPTIMIZATION REPORT ######]
Writing Analyst data base
C:Actel_PrjEE270_Async_projsynthesisAsync_Top.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU
Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
Writing EDIF Netlist and constraint files
I-2013.09M-SP1-1
Finished Writing EDIF Netlist and constraint files (Real Time elapsed
0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB
peak: 110MB)
@W: MT420 |Found inferred clock Async_Top|R_in_Top with period
10.00ns. Please declare a user-defined clock on object "p:R_in_Top"
@W: MT420 |Found inferred clock
Async_FIFO_reg|R_out_1_inferred_clock_1_0 with period 10.00ns. Please
declare a user-defined clock on object "n:Reg3.R_out_1"
@W: MT420 |Found inferred clock
Async_FIFO_reg|R_out_1_inferred_clock_1 with period 10.00ns. Please
declare a user-defined clock on object "n:Reg2.R_out_1"
@W: MT420 |Found inferred clock Async_FIFO_reg|R_out_1_inferred_clock
with period 10.00ns. Please declare a user-defined clock on object
"n:Reg1.R_out_1"
##### START OF TIMING REPORT #####[
# Timing Report written on Sun Apr 26 00:42:49 2015
#
Top view: Async_Top
Library name: fusion
Operating conditions: COMWCSTD ( T = 70.0, V = 1.42, P = 1.74,
tree_type = balanced_tree )
Requested Frequency: 100.0 MHz
Wire load mode: top
Wire load model: fusion
Paths requested: 5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look
at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with
the clock.
Performance Summary
*******************

Worst slack in design: NA
Requested Estimated
Requested Estimated Clock Clock
Starting Clock Frequency Frequency
Period Period Slack Type Group
----------------------------------------------------------------------
----------------------------------------------------------------------
----
Async_FIFO_reg|R_out_1_inferred_clock 100.0 MHz NA
10.000 NA NA inferred Inferred_clkgroup_1
Async_FIFO_reg|R_out_1_inferred_clock_1 100.0 MHz NA
Async_FIFO_reg|R_out_1_inferred_clock_1_0 100.0 MHz NA
Async_Top|R_in_Top 100.0 MHz NA
======================================================================
======================================================================
====
Clock Relationships
*******************
Clocks
| rise to rise | fall to fall | rise to fall |
fall to rise
----------------------------------------------------------------------
----------------------------------------------------------------------
------------------------------
Starting Ending
| constraint slack | constraint slack | constraint slack |
constraint slack
----------------------------------------------------------------------
----------------------------------------------------------------------
------------------------------
Async_Top|R_in_Top
Async_FIFO_reg|R_out_1_inferred_clock | No paths - | No
paths - | Diff grp - | No paths -
Async_FIFO_reg|R_out_1_inferred_clock
Async_FIFO_reg|R_out_1_inferred_clock_1 | No paths - |
Diff grp - | No paths - | No paths -
Async_FIFO_reg|R_out_1_inferred_clock_1
Async_FIFO_reg|R_out_1_inferred_clock_1_0 | No paths - |
Diff grp - | No paths - | No paths -

======================================================================
======================================================================
==============================
Note: 'No paths' indicates there are no paths in the design for that
pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock
and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
##### END OF TIMING REPORT #####]
----------------------------------------------------------------------
----------
Target Part: AFS600_PQFP208_STD
Report for cell Async_Top.behavioral
Core Cell usage:
cell count area count*area
CLKINT 3 0.0 0.0
GND 5 0.0 0.0
INV 4 1.0 4.0
VCC 5 0.0 0.0
DLN0 24 1.0 24.0
DLN1 8 1.0 8.0
DLN1P1C1 4 2.0 8.0
----- ----------
TOTAL 53 44.0
IO Cell usage:
cell count
CLKBUF 1
INBUF 9
OUTBUF 10
-----
TOTAL 20
Core Cells : 44 of 13824 (0%)
IO Cells : 20
RAM/ROM Usage Summary
Block Rams : 0 of 24 (0%)

Global Operating Voltage = 3.3V
Power-Specific unit information:
Voltage units = 1V
Capacitance Units = 1.000000ff
Time units = 1ns
Dynamic Power Units = 1uW (derived from V,C,T units)
Leakage Power Units = Unitless
Cell Internal Power = 508.2911 uW (100%)
Net Switching Power = 4.4557 uW (0%)
--------
Total Dynamic Power = 512.7468
Cell Leakage Power = 0.0000
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed
0h:00m:00s; Memory used current: 47MB peak: 111MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Apr 26 00:42:49 2015
###########################################################]

SW Used:
Design Suite:
Libero v11.4 SP1 Design Suite (Microsemi SoC)
Simulation:
ModelSim ME 10.3a
Synthesis:
Synopsys VCS
Synplify Pro Microsemi Edition I-2013.09M-SP1-1

References:
1. Cummings, Clifford E., and Sunburst Design. "Simulation and Synthesis Techniques for
Asynchronous FIFO Design." Simulation and Synthesis Techniques for Asynchronous FIFO
Design 1.2 (2002): 3-6. Web. 25 Apr. 2015. <www.sunburst-
design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf>.
2. Yun, Kenneth Y., Peter A. Beerel, and Julio Arceo. "High-Performance Asynchronous Pipeline
Circuits." High-Performance Asynchronous Pipeline Circuits 1.0 (n.d.): 3-4. Web. 21 Apr. 2015.

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