Trivium Cipher Design

EECT 6325- VLSI Design
Term Project: Trivium
Team Members:
Ozgen Sumer Lacin UTD ID: 2021227875
Muhammad Mohid Nabil UTD ID: 2021258403
Instructor: Dr. Jeyavijayan Rajendran
T.A: Vahid Moalemi

Table of Contents
Abstract.........................................................................................................................................................4
Introduction ..................................................................................................................................................4
Block Diagram of the System........................................................................................................................4
Building Blocks: Gates and registers used in the System..............................................................................5
Flip Flop.....................................................................................................................................................5
XOR Gate...................................................................................................................................................8
AND gate.................................................................................................................................................10
Schematic of the Trivium Stream (Complete Design).................................................................................11
Layout of Trivium ........................................................................................................................................13
Results.........................................................................................................................................................16
Simulation Results of the Schematic.......................................................................................................16
Simulation Results of the Layout ............................................................................................................19
Appendix .....................................................................................................................................................23
HSPICE Netlist (.sp file) for Schematic Simulation ..................................................................................23
HSPICE Netlist (.sp file) for Layout Simulation........................................................................................37

Figure 1: Block Diagram of the Trivium Stream............................................................................................5
Figure 2: Schematic of Dynamic FF...............................................................................................................6
Figure 3: Layout of Dynamic FF.....................................................................................................................7
Figure 4: Block Diagram of FF .......................................................................................................................7
Figure 5: Input Propagation when 10 FFs are cascaded...............................................................................8
Figure 6: Schematic of XOR Gate ..................................................................................................................9
Figure 7: Layout of XOR gate.........................................................................................................................9
Figure 8: Block of XOR.................................................................................................................................10
Figure 9: Schematics of NAND and Inverter gates......................................................................................10
Figure 10: Layout of NAND and Inverter gates...........................................................................................11
Figure 11: Complete Schematic of the Design............................................................................................11
Figure 12: Zoomed version of the transition point from Section A to Section B........................................12
Figure 13: Zoom out version of the Layout.................................................................................................13
Figure 14: Zoomed in version of the layout with pin names ......................................................................13
Figure 15: FFs with XOR attached...............................................................................................................14
Figure 16: End of layout with output pin labeled .......................................................................................14
Figure 17: Propagation of bits via FFs.........................................................................................................17
Figure 18: AND operation waveform..........................................................................................................17
Figure 19: XOR function..............................................................................................................................18
Figure 20: Clock to Q delay(tcq)..................................................................................................................19
Figure 21: Propagation Waveform of bits...................................................................................................20
Figure 22: AND Function.............................................................................................................................20
Figure 23: XOR Function..............................................................................................................................21
Figure 24: Waveform till 700ns...................................................................................................................21

Abstract
In this project, we designed a Trivium stream cipher, a hardware oriented synchronous stream cipher
which aims to provide a flexible trade-off between speed and area. For this design, we used three basic
gates and a FF register. Logic gates employed for this project are NAND, Inverter, and an XOR. We first
implemented the circuit in the schematic level and did pre-layout simulations then we draw layout and
performed post layout simulations. We decided to choose area optimization that’s why transistor sizes
are kept as small as possible especially for FF design. This report gives an overview about Trivium
stream cipher, explains the design metric, and shows the block diagram, circuit schematic and layout of
the complete design together with the simulation results as results and discussion part.
Introduction
Trivium is a stream cipher key designed to generate a cipher key by using minimum gate count in
hardware and provide fast results. It was first introduced in Profile II of the eStream competition by its
authors Christophe De Cannière and Bart Preneel. It is not patented and specified as International
Standard under ISO/IEC. Trivium generates up to 264
bits of output by using 80 bit secret key and 80 bit
initial values (IV). Even though it is a simple eSTREAM entrant, it is shown to have notable resistance to
cryptanalysis and performance. Trivium works as following: Initially secret key and initial values are
introduced into Trivium cipher key to create internal state then state is updated repeatedly and key
stream bits are generated. 288-bit internal state consists of three shift registers of different lengths. At
each round, a bit is shifted into all these three shift registers and one bit of output is produced. In the
initialization stage, key and IV values are written into the shift registers and rest of the values are kept
fixed as either 0s or 1s. The cipher state is then update 4*288 = 1152 times so that bits in the internal
state depend on the bits of the key and the IV in a complex nonlinear way.
Block Diagram of the System
Figure 1 shows the block diagram of the Trivium stream cipher. As can be seen, 288 bits are divided
mainly into three regions. All these regions are connected to each other with XOR and AND gates. These
gates take certain outputs from the corresponding states as defined in the algorithm and give them to
other register or logical gates as an input. These gates create the non-linear combination of taps. If there
were no XOR and AND gates in the system, it was just going to shift the values introduced to the system
till output.

Figure 1: Block Diagram of the Trivium Stream
Building Blocks: Gates and registers used in the System
There are 3 gates and 1 register used in the design of the Trivium. These gates are NAND, Inverter and
XOR whereas the register is Flip Flop. Each of these elements will be explained briefly and their
waveforms will be given.
Flip Flop
For this project, we designed a dynamic Flip Flop. There was no restriction on the type of the FF
however we decided to choose this FF type due to its smaller area compared to static CMOS
implementation. Typical static FF uses 18 transistors whereas the dynamic FF employs 10 transistors and
this configuration saves from area dramatically. The capacitors in the original design were replaced with
PMOS and NMOS transistors to make the FF asynchronous. Original usage of asynchronous reset FF is to
pull down the output voltage to ground whenever the reset is applied independent of CLK, or the data
stored in the FF. We use this function of reset to load initial values in parallel. This saves a lot of time
since we have 288 bits to initialize. Loading them 1 by 1 with shifting method would take really long
that’s why we exploit this feature of reset to save time. The schematic of the dynamic FF we designed is
given in Figure 2. Additional transistors are just for creating signals such as CLK, reset and IV rather than
a part of the generic dynamic FF design. Including all these, the total transistor count reaches up to 16.
The layout of the dynamic FF is shown in Figure 2 with necessary dimensions. Total size of the layout is
7.3µm x 5.39µm. All PMOS transistors are 560nm and NMOS transistor are 280nm in this FF design.
Block diagram of the structure is created for easy connection in the schematic.

Figure 2: Schematic of Dynamic FF

Figure 3: Layout of Dynamic FF
Figure 4: Block Diagram of FF

FFs are connected back to back and propagation is obtained successfully as shown in Figure 5. For the
size of the graph, here we show just 10 FFs connected back to back but in the real case where there are
288 FFs we get a smooth propagation of the input signal fed into the system.
Figure 5: Input Propagation when 10 FFs are cascaded
.
XOR Gate
There are 11 XOR gates in total in the system. These gates are used for addition over Galois Field 2 (GF2)
in the Trivium stream cipher. We came up with a custom XOR design instead of using a static CMOS
design due to the same reasons stated above for FF such as decreasing the area while achieving
reasonable delay and energy. The schematic and layout of the XOR gate are shown in Figure 6 and
Figure 7 respectively. As it is seen XOR gate has a total area of 5.710µm*3.280 µm. Width of PMOS and
NMOS are 2.16µm and 780nm respectively.

Figure 6: Schematic of XOR Gate
Figure 7: Layout of XOR gate

Figure 8: Block of XOR
AND gate
AND gate is constructed by using one NAND gate and an inverter appended to its output. These gates
are instantiated from the library we created for our Lab assignments. Schematics and layouts of NAND
and Inverter are given below.
Figure 9: Schematics of NAND and Inverter gates
Sizes of all of the transistors in NAND gate are 840nm whereas in inverter PMOS is 1.18 µm and NMOS is
280nm.

Figure 10: Layout of NAND and Inverter gates
Schematic of the Trivium Stream (Complete Design)
The complete schematic is built by adding all 288 FFs back to back and placing AND and XOR gates to the
corresponding places respectively. The snapshot of the complete schematic is shown below but this
image doesn’t show the elements clearly due to poor aspect ratio of the diagram however to give a
better view to the reader we also show the zoomed version of the critical part of our system where FFs,
XORs and AND gates exist.
Figure 11: Complete Schematic of the Design

Figure 12: Zoomed version of the transition point from Section A to Section B
Figure 12 shows a critical part of the design. We basically divided the 288 bits into three sections A, B
and C, we introduced secret keys to A, initial values (IVs) to B and the static inputs (0s and 1s) to C.
Complexity of the design lies in the part between these sections where sections (A, B and C) are
interacting with each other and this section is basically where we implement the algorithm. Based on

the algorithm provided to us, specific outputs should be XOR’ed or AND then provided as an input to
another FF. For example, in Figure 12 output of 91st
and 92nd
FFs are fed into NAND gate then inverted
(AND operation) and provided as an input to an XOR gate whereas the other this XOR gate is actually
coming from the output of the 1st
XOR gate where 93rd
and 66th
state bits are the inputs.
Layout of Trivium
Figure 13: Zoom out version of the Layout
Figure 14: Zoomed in version of the layout with pin names

Figure 15: FFs with XOR attached
Figure 16: End of layout with output pin labeled
Our layout’s aspect ratio is 400. We designed our layout in rectangular form that’s why its length is 400
time bigger than its width. We tried not to create off-paths so that we wouldn’t deviate from the
rectangular shape and not increase the area. Putting everything in square form would be a nicer
approach and look more compact but since we didn’t have a requirement on the area we instantiated all
the layouts back to back and got this form.
Total Area of this design is: 10.39µm*2093µm= 0.0213 〖mm〗^2

Results
Note: Before we discuss any simulation results, we would like to state that due to technical problems
related to our quota on H drive we couldn’t run a simulation longer than 700ns. University provides
2.0GB of storage on H drive to graduate students and every time we ran the simulations for 4*288
cycles (which is equal to 1152ns for our simulations, CLK period was 1ns) just to initialize the keys, we
filled all our quota provided to us and eventually lost both of our spaces. Simulations were taking
more than 2GB therefore not giving results after 700ns for our case. Even though we deleted all the
unnecessary files on our H drive after we are done analyzing the results and start a new run for each
analysis, eventually both of us lost our access to the shared folders and just left with 200MB. We
talked to IT Service and they got back to us after 5 days and the additional space provided to us was
still not enough to run a complete simulation to see if our chip is capable of creating the cipher key or
not. All 2GB of storage was filled with unknown data that neither us nor them could find. We
explained this situation also to Prof. Rajendran. Due to insufficient storage provided to us, in this and
next section where we also include the post layout simulations, functionality of each basic block
together with a 700ns simulation results will be shown to prove that our design works but just can’t
complete the required simulation time due to space issues and we would be able to achieve the
required output values if we had enough storage.
Simulation Results of the Schematic
Before we implemented our layout, we did pre-layout simulations to see if our circuit is working fine or
not. That’s why we built our circuit on Cadence Virtuoso and extracted the netlist from Analog
environment and loaded this netlist into HSPICE. This model doesn’t include the parasitic capacitances
coming from the metal layer connections that’s why we expect a smaller delay compared to the post-
layout simulations. Simulation results show that our circuit works fine and is able to propagate the
introduced secret keys and initial values to the output without any loss. It is worthwile to mention here
one more time that all the secret key and initial values are introduced in parallel by exploiting the reset
function in FF. It only takes one clock cycle for us to initialize all these values into the system.
Simulation results for both schematic and layout were divided into three main sections which are: bit
propagation, AND function and XOR function outputs. After we run our simulations, we checked specific
outputs to prove that our circuit works in correct way. The net names put in the graph indicates specific
output nodes and explained in a detailed way in the following.
1) Propagation Function
In this waveform, we measured 8 different output values which are 1st
, 10th
, 20th
, 30th
, 70th
103rd
, 178th
and 288th
outputs of the FFs. Net names corresponding to these outputs are net3901, net3824, net3768,
net 3782, net 3355, net 2977, net 3124 and net q respectively as can also be seen from the figure below.
These values are written in the same order in the graph. For example, CLK is the green pulse followed by
net3901 (the yellow pulse) then net3824 (the blue pulse) and so on. As it is seen from the graph, output
of each of these FFs are propagated without any problems to the primary output.

Figure 17: Propagation of bits via FFs
2) AND Function
To implement the AND function, we used a NAND gate and an Inverter. To show the functionality of this
function, we took the outputs of 91st
and 92nd
FFs and provided as an input to our NAND gate. Output of
this NAND gate is given as an input to inverter and output of the inverter gave us the AND function.
Waveform below proves that initial value (K1=1 and rest is 0) is propagated to the 91st
and 92nd
FF
without any problem and AND operation is performed correctly.
Figure 18: AND operation waveform

In Figure 18, pink and red pulses (net 3243 and net 3236) are the inputs to NAND gate and the blue
pulse(net 1847) is the output of NAND whereas the yellow pulse in the bottom of the graph is the
output of the inverter. As it is seen, our bits are being ANDed without any problem as well.
3) XOR Function
To prove the functionality of XOR, we used 93rd
bit and 66th
bit (first XOR operation of Trivium that gives
us t1). Figure 19 shows the operation. Similar to previous graphs, green pulse is the CLK pulse with 1 GHz
and yellow pulses (net3292) are the 1st
input of the XOR and white pulses (s66) are the other input. Blue
pulses are the output of our XOR gate and as it is seen, they work well and direct their result to the
required stages as well.
Figure 19: XOR function
After we observed correct functionality of all the basic blocks, we measured our delay, power energy
and EDP and power results and tabulated them. Table 1 shows the summary of our results.
Delay Energy EDP Power
Schematic
Results
325ps 0.2nJ 1.23e-29 0.78mW
Delay is measured from second clock cycle to second pulse in output because the first output pulse is
coming from the initialization part. It is calculated in Waveview software by measure tool and shown in
Figure 20.

Power and GND wire Sizing Formula is calculated as follows:
Measured power of the chip is 0.78mW.
Thus 0.78mW = VI
Thus I= 0.78mW/1.2 = 0.65mA
The current density due to electron migration is 0.5mA/µm
Thus the vdd and gnd widths are 0.65/0.5 = 1.3µm
Figure 20: Clock to Q delay(tcq)
Simulation Results of the Layout
After getting successful results from the schematic we draw the layout of our design and did post layout
simulations and compared them with circuit schematic simulations. As will be seen from the following
analyses, circuit and layout schematic simulations match and they give the same output. To provide a
good comparison, we used exactly the same nets. Three analyses are performed as in the previous case
and results are tabulated. Since detailed analyses of how we choose the nodes are explained in the
schematic simulation results section, this section will just show the graphs and prove that post layout
simulations give the same results with schematic results. The only addition done to this part is putting
the complete simulation results that we ran for 700ns. We included the Figure showing the waveform of
Multiple signals including XORs, ANDs propagation and primary output and proved that our circuit
behavior doesn’t get distorted when we run for multiple cycles as well.

1) Propagation Function
Figure 21: Propagation Waveform of bits
2) AND Function
Figure 22: AND Function

3) XOR Function
Figure 23: XOR Function
4) Complete Simulation
Simulation time was set to 1440 (4cycle to initialize and 1 cycle to create one bit of key stream) ns
however due to storage issues and simulation stopped displaying results after 700ns.
Figure 24: Waveform till 700ns

Delay Energy EDP Power Power and
GND Wire
Sizing
Layout Results 339ps 0.3nJ 101.7e-21 1.18mW 1.16µm
Conclusion
In this Term Project, we designed Trivium Stream cipher by optimizing the area of the layout. Circuit
schematic and Layout are both built in Cadence Virtuoso and simulated using HSPICE simulator. Results
showed that designed circuit functions as expected but due to storage problems we couldn’t run our
simulation more than 3 clock cycles but in that 3 clock cycles we showed that both schematic and layout
simulations provided satisfactory outputs. Delay, area, energy, power, EDP and Power and GND rails
Wire sizing are measured in tabulated. Total area of the chip is measured as 0.0213 𝑚𝑚2
.
(10.39µm*2093µm). Total power consumption and energy consumption are measured to be 1.18mW,
and 0.3nJ respectively. Total number of 4736 transistors are used in this design.

Appendix
HSPICE Netlist (.sp file) for Schematic Simulation
** Generated for: hspiceD
** Generated on: Apr 29 19:43:06 2016
** Design library name: Oz
** Design cell name: Triviumproject
** Design view name: schematic
*.include "/home/cad/kits/IBM_CMRF8SF-
LM013/IBM_PDK/cmrf8sf/V1.2.0.0LM/HSPICE/models/model013.lib_inc"
.TEMP 25
.OPTION
+ ARTIST=2
+ INGOLD=2
+ MEASOUT=1
+ PARHIER=LOCAL
+ PSF=2
** Library name: Oz
** Cell name: inverter
** View name: schematic
.subckt inverter gnd in out vdd
mt1 out in vdd vdd pfet l=120e-9 w=1.08e-6 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=251.2e-3
nrs=251.2e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0 pam2=0 panw1=0 panw2=0
panw3=0 panw4=0 panw5=0 panw6=0 panw7=0 panw8=0 panw9=0 panw10=0 dtemp=0
mt0 out in gnd gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=1.1064
nrs=1.1064 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0 pam2=0 panw1=0 panw2=0
.ends inverter
** End of subcircuit definition.
** Library name: Oz
** Cell name: NAND
.subckt NAND a b gnd out vdd
mt3 net018 b gnd gnd nfet l=120e-9 w=840e-9 nf=1 m=1 rf=0 ngcon=1 ad=419e-15 as=419e-15
pd=2.645e-6 ps=2.645e-6 nrd=327e-3 nrs=327e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1
pam1=0 pam2=0 panw1=0 panw2=0 panw3=0 panw4=0 panw5=0 panw6=0 panw7=0 panw8=0
panw9=0 panw10=0 dtemp=0
mt2 out a net018 gnd nfet l=120e-9 w=840e-9 nf=1 m=1 rf=0 ngcon=1 ad=419e-15 as=419e-15
pd=2.645e-6 ps=2.645e-6 nrd=327e-3 nrs=327e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1
mt1 out b vdd vdd pfet l=120e-9 w=840e-9 nf=1 m=1 rf=0 ngcon=1 ad=419e-15 as=419e-15 pd=2.645e-6
ps=2.645e-6 nrd=327e-3 nrs=327e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0

pam2=0 panw1=0 panw2=0 panw3=0 panw4=0 panw5=0 panw6=0 panw7=0 panw8=0 panw9=0
panw10=0 dtemp=0
mt0 out a vdd vdd pfet l=120e-9 w=840e-9 nf=1 m=1 rf=0 ngcon=1 ad=419e-15 as=419e-15 pd=2.645e-6
ps=2.645e-6 nrd=327e-3 nrs=327e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0
pam2=0 panw1=0 panw2=0 panw3=0 panw4=0 panw5=0 panw6=0 panw7=0 panw8=0 panw9=0
panw10=0 dtemp=0
.ends NAND
** Library name: Oz
** Cell name: XOR
.subckt XOR a b gnd out vdd
mt10 net24 net29 vdd vdd pfet l=120e-9 w=2.16e-6 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
nrd=122.9e-3 nrs=122.9e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0 pam2=0
panw1=0 panw2=0 panw3=0 panw4=0 panw5=0 panw6=0 panw7=0 panw8=0 panw9=0 panw10=0
dtemp=0
mt6 net29 b net12 vdd pfet l=120e-9 w=2.16e-6 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
dtemp=0
mt7 net12 a vdd vdd pfet l=120e-9 w=2.16e-6 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=122.9e-
3 nrs=122.9e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0 pam2=0 panw1=0
panw2=0 panw3=0 panw4=0 panw5=0 panw6=0 panw7=0 panw8=0 panw9=0 panw10=0 dtemp=0
mt4 out b net24 vdd pfet l=120e-9 w=2.16e-6 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=122.9e-
mt1 out a net24 vdd pfet l=120e-9 w=2.16e-6 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=122.9e-
mt8 net29 a gnd gnd nfet l=120e-9 w=780e-9 nf=1 m=1 rf=0 ngcon=1 ad=388e-15 as=388e-15
pd=2.525e-6 ps=2.525e-6 nrd=353.7e-3 nrs=353.7e-3 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1
pwd100=-1 pam1=0 pam2=0 panw1=0 panw2=0 panw3=0 panw4=0 panw5=0 panw6=0 panw7=0
panw8=0 panw9=0 panw10=0 dtemp=0
mt11 out net29 gnd gnd nfet l=120e-9 w=780e-9 nf=1 m=1 rf=0 ngcon=1 ad=388e-15 as=388e-15
mt3 out a net41 gnd nfet l=120e-9 w=780e-9 nf=1 m=1 rf=0 ngcon=1 ad=388e-15 as=388e-15

.ends XOR
** Library name: Oz
** Cell name: FFforProj
.subckt FFforProj clk iv data gnd q reset vdd
mt5 net11 clkbar net47 vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=272e-15 as=272e-15
mt8 clkbar clk vdd vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
dtemp=0
mt13 ivbar iv vdd vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=504.9e-
mt10 resetbar reset vdd vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
dtemp=0
mt1 net47 net39 vdd vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
dtemp=0
mt7 net11 resetbar ivbar vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
dtemp=0
mt17 q net11 vdd vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
dtemp=0
mt0 net39 clk data vdd pfet l=120e-9 w=560e-9 nf=1 m=1 rf=0 ngcon=1 ad=272e-15 as=272e-15
mt4 net11 clk net47 gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=124e-15 as=124e-15
pd=1.525e-6 ps=1.525e-6 nrd=1.1064 nrs=1.1064 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1
mt3 net47 net39 gnd gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
nrd=1.1064 nrs=1.1064 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0 pam2=0
dtemp=0

mt6 net39 reset iv gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=1.1064
mt2 net39 clkbar data gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=124e-15 as=124e-15
pd=1.525e-6 ps=1.525e-6 nrd=1.1064 nrs=1.1064 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1
mt12 ivbar iv gnd gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=1.1064
mt15 q net11 gnd gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=1.1064
mt11 resetbar reset gnd gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0
nrd=1.1064 nrs=1.1064 rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 pam1=0 pam2=0
dtemp=0
mt9 clkbar clk gnd gnd nfet l=120e-9 w=280e-9 nf=1 m=1 rf=0 ngcon=1 ad=0 as=0 pd=0 ps=0 nrd=1.1064
.ends FFforProj
** Library name: Oz
** Cell name: Triviumproject
xi341 gnd net1837 net1824 vdd inverter
xi225 net2354 net2851 gnd net1842 vdd NAND
xi348 bxor net1862 gnd net01841 vdd XOR
xi343 net1824 net1852 gnd net1862 vdd XOR
xi349 axor net01841 gnd q vdd XOR
xi344 s69 net1862 gnd loop vdd XOR
xi227 net1828 net1892 gnd bxor vdd XOR
xi228 s264 bxor gnd net1872 vdd XOR
xi193 s66 net3292 gnd net1877 vdd XOR
xi194 net1832 net1877 gnd axor vdd XOR
xi195 s171 axor gnd net1887 vdd XOR
xi239 clk gnd net2564 gnd net2095 reset vdd FFforProj

xi333 clk gnd net1927 gnd s264 reset vdd FFforProj
xi335 clk gnd s264 gnd net1941 reset vdd FFforProj

xi148 clk k52 net2753 gnd net2340 reset vdd FFforProj
xi118 clk k70 s162 gnd net2375 reset vdd FFforProj

xi338 clk vdd net1913 gnd net1920 reset vdd FFforProj
xi119 clk k69 net2557 gnd s162 reset vdd FFforProj
xi114 clk k79 s171 gnd net2935 reset vdd FFforProj
xi127 clk k78 net2522 gnd s171 reset vdd FFforProj

xi347 clk gnd net2200 gnd s243 reset vdd FFforProj
xi241 clk gnd s243 gnd net3082 reset vdd FFforProj
xi104 clk iv75 net3390 gnd net3229 reset vdd FFforProj
xi106 clk iv67 s66 gnd net3264 reset vdd FFforProj

xi107 clk iv66 net3467 gnd s66 reset vdd FFforProj
xi97 clk iv70 s69 gnd net3355 reset vdd FFforProj
xi96 clk iv69 net3334 gnd s69 reset vdd FFforProj

xi0 clk iv1 loop gnd net3901 reset vdd FFforProj
.include"/home/cad/kits/IBM_CMRF8SF-

*==Supply Voltage==*
VDD1 vdd gnd DC 1.2V
*==Pulse Voltages==*
Vin2 CLK gnd pulse (0V 1.2V 1ns 100ps 100ps 0.5ns 1ns)
Vin3 reset gnd pulse (0V 1.2V 500ps 100ps 100ps 1ns 288ns)
Vin4 IV1 gnd pulse (0V 1.2V 0s 100ps 100ps 2ns 288ns)
Vin5 IV2 gnd pulse (0V 0V 0s 0ps 0ps 3ns 20ns)

Vin84 K1 gnd pulse (0V 0V 0s 100ps 100ps 2ns 10ns)
Vin666 k3 gnd pulse (0V 0V 0s 100ps 100ps 2ns 10ns)

.tr 0.5ns 288ns
.measure tran iavg avg I(VDD1) from=1n to=288n
.measure energy param = '-1.2*iavg*288e-9'
.measure power param = '-1.2*iavg'
.measure edp param = 'edp*325e-12'
.options post=2 nomod
.op
.option accurate
.END

HSPICE Netlist (.sp file) for Layout Simulation
.include "/home/cad/kits/IBM_CMRF8SF-
.include Triviumproject.sp
*==Supply Voltage==*
VDD1 vdd gnd DC 1.2V
*==Pulse Voltage==*
Vin2 CLK gnd pulse (0V 1.2V 1ns 100ps 100ps 0.5ns 1ns)
Vin3 reset gnd pulse (0V 1.2V 500ps 100ps 100ps 1ns 288ns)
Vin4 IV1 gnd pulse (0V 1.2V 0s 100ps 100ps 2ns 288ns)

.options post=2 nomod
.op
.option accurate
x1 CLK IV1 IV10 IV11 IV12 IV13 IV14 IV15 IV16 IV17 IV18 IV19
+ IV2 IV20 IV21 IV22 IV23 IV24 IV25 IV26 IV27 IV28 IV29 IV3 IV30 IV31 IV32 IV33
+ IV78 IV79 IV8 IV80 IV9 k1 k10 k11 k12 k13 k14 k15 k16 k17 k18 k19 k2 k20 k21
+ k22 k23 k24 k25 k26 k27 k28 k29 k3 k30 k31 k32 k33 k34 k35 k36 k37 k38 k39 k4
+ k77 k78 k79 k8 k80 k9 reset q Triviumproject
*x2 vdd gnd! CLK IV q1 q2 reset FFforProj

.tr 0.5ns 288ns
.measure tran iavg avg I(VDD1) from=1n to=288n
.measure energy param = '-1.2*iavg*288e-9'
.measure power param = '-1.2*iavg'
*sweep beta 0.1 5 0.1
*.measure tran tcq1 trig v(CLK) val = 0.6v rise=3 targ v(q1) val=0.6v rise=2
*.measure tran tcq2 trig v(CLK) val = 0.6v rise=2 targ v(q1) val=0.6v fall=1
*.measure tran trq trig v(reset) val = 0.6v rise=1 targ v(q1) val=0.6v rise=1
*.measure tran energy integral p(x1) from=0ns to 25ns
.end

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