A Barrel Shifter is a logic component that perform shift or rotate operations. Barrel shifters are applicable for digital signal processors and processors, here we designed 16-bit barrel shifter using 2X1 MUXs in Logisim simulation
This document discusses Verilog data types. There are two main groups: nets and variables. Nets like wire are used for connections and have a default value of Z. Variables like reg store values and have a default of X. Important net types are wire, tri, and trireg; wire is used for single-driver nets while tri is for multiple drivers. Variables include reg for storage in procedural blocks, integer for integers, and real for real numbers.
The document summarizes different types of shifters used in microprocessor design including logical, arithmetic, barrel, and funnel shifters. It describes the function of each shifter type and provides examples. It then focuses on funnel shifters, explaining they can perform all shift operations, and describes two types of funnel shifter designs - array and multilevel funnel shifters. The array design uses an array of multiplexers while the multilevel design uses multiple levels of smaller multiplexers.
This document discusses the design of a floating point multiplier. It begins by explaining the representation of floating point numbers with sign, exponent, and significand. It then describes why floating point is used over fixed point for its wider range of values and greater precision over integers. The key steps for multiplying floating point numbers are described as adding the exponents and multiplying the significands, while XORing the signs. Block diagrams and techniques for partial product generation and accumulation are presented, including radix-4 Booth multiplication and use of carry save adders and ripple carry adders. Finally, floating point formats for single, double, and quadruple precision are shown along with using the divide and conquer technique for higher precision multiplication.
This document discusses interfacing a digital-to-analog converter (DAC) with an 8051 microcontroller. It explains that a DAC is used to convert digital pulses from the 8051 into analog signals that can be read by systems requiring analog inputs. Specifically, it describes using an 8-bit DAC 0808 chip to convert digital data from the 8051 into a corresponding analog output voltage. It also provides 8051 assembly code examples to generate triangular and square wave outputs using a DAC interfaced with an 8051 port.
VLSI subsystem design processes and illustrationVishal kakade
This document discusses the design processes for digital subsystem design. It begins by outlining the objectives of design consideration, problem and solution, basic digital processor structure, and datapath. It then discusses general considerations for subsystem design such as lower unit cost and higher reliability. It presents some common problems in design like how to design complex systems efficiently. It proposes solutions like top-down design and partitioning the system. The document then illustrates the design processes through examples like designing a 4-bit shifter and ALU subsystem. It provides block diagrams, logic diagrams and layouts at different stages of the design process.
The document contains programs to perform various operations on 8-bit numbers like addition, subtraction, multiplication, division using 8085 microprocessor. It also contains programs to find the largest/smallest number in an array, and to arrange an array of numbers in ascending order. The programs demonstrate various instructions of 8085 like load, move, add, subtract, compare, jump etc to perform the given tasks.
1) The document discusses parallel adders and subtractors for n-bit binary numbers. It specifically examines a 4-bit parallel adder that uses full adders connected in cascade, with the carry output of one full adder connected to the next's carry input.
2) A 4-bit parallel subtractor is also examined, which takes the 2's complement of the number to be subtracted and adds it to the other number using a 4-bit parallel adder.
3) Carry propagation time is discussed, which is the time it takes the carry to ripple through all the full adders in the parallel adder from the least to most significant bit.
The document discusses the instruction set of the 8086 microprocessor. It describes that the 8086 has over 20,000 instructions that are classified into several categories like data transfer, arithmetic, bit manipulation, program execution transfer, and string instructions. Under each category, it provides details about specific instructions like MOV, ADD, AND, CALL, etc. and explains their functionality and operand usage.
This document discusses Verilog data types. There are two main groups: nets and variables. Nets like wire are used for connections and have a default value of Z. Variables like reg store values and have a default of X. Important net types are wire, tri, and trireg; wire is used for single-driver nets while tri is for multiple drivers. Variables include reg for storage in procedural blocks, integer for integers, and real for real numbers.
The document summarizes different types of shifters used in microprocessor design including logical, arithmetic, barrel, and funnel shifters. It describes the function of each shifter type and provides examples. It then focuses on funnel shifters, explaining they can perform all shift operations, and describes two types of funnel shifter designs - array and multilevel funnel shifters. The array design uses an array of multiplexers while the multilevel design uses multiple levels of smaller multiplexers.
This document discusses the design of a floating point multiplier. It begins by explaining the representation of floating point numbers with sign, exponent, and significand. It then describes why floating point is used over fixed point for its wider range of values and greater precision over integers. The key steps for multiplying floating point numbers are described as adding the exponents and multiplying the significands, while XORing the signs. Block diagrams and techniques for partial product generation and accumulation are presented, including radix-4 Booth multiplication and use of carry save adders and ripple carry adders. Finally, floating point formats for single, double, and quadruple precision are shown along with using the divide and conquer technique for higher precision multiplication.
This document discusses interfacing a digital-to-analog converter (DAC) with an 8051 microcontroller. It explains that a DAC is used to convert digital pulses from the 8051 into analog signals that can be read by systems requiring analog inputs. Specifically, it describes using an 8-bit DAC 0808 chip to convert digital data from the 8051 into a corresponding analog output voltage. It also provides 8051 assembly code examples to generate triangular and square wave outputs using a DAC interfaced with an 8051 port.
VLSI subsystem design processes and illustrationVishal kakade
This document discusses the design processes for digital subsystem design. It begins by outlining the objectives of design consideration, problem and solution, basic digital processor structure, and datapath. It then discusses general considerations for subsystem design such as lower unit cost and higher reliability. It presents some common problems in design like how to design complex systems efficiently. It proposes solutions like top-down design and partitioning the system. The document then illustrates the design processes through examples like designing a 4-bit shifter and ALU subsystem. It provides block diagrams, logic diagrams and layouts at different stages of the design process.
The document contains programs to perform various operations on 8-bit numbers like addition, subtraction, multiplication, division using 8085 microprocessor. It also contains programs to find the largest/smallest number in an array, and to arrange an array of numbers in ascending order. The programs demonstrate various instructions of 8085 like load, move, add, subtract, compare, jump etc to perform the given tasks.
1) The document discusses parallel adders and subtractors for n-bit binary numbers. It specifically examines a 4-bit parallel adder that uses full adders connected in cascade, with the carry output of one full adder connected to the next's carry input.
2) A 4-bit parallel subtractor is also examined, which takes the 2's complement of the number to be subtracted and adds it to the other number using a 4-bit parallel adder.
3) Carry propagation time is discussed, which is the time it takes the carry to ripple through all the full adders in the parallel adder from the least to most significant bit.
The document discusses the instruction set of the 8086 microprocessor. It describes that the 8086 has over 20,000 instructions that are classified into several categories like data transfer, arithmetic, bit manipulation, program execution transfer, and string instructions. Under each category, it provides details about specific instructions like MOV, ADD, AND, CALL, etc. and explains their functionality and operand usage.
Registers are groups of flip-flops that store binary data. Shift registers can transfer data in serial or parallel formats. There are four basic modes of shift registers: serial-in serial-out, serial-in parallel-out, parallel-in serial-out, and parallel-in parallel-out. Counters are circuits made of flip-flops that count clock pulses and can be asynchronous, synchronous, decade, up/down, or cascaded to achieve different counts.
Shift registers allow for storage and movement of digital data. They consist of flip-flops connected in a chain so the output of one becomes the input of the next. There are several types of shift registers including serial in-serial out, serial in-parallel out, parallel in-serial out, and parallel in-parallel out. Special shift registers also exist like bidirectional and counter shift registers.
This document summarizes different types of adders used in digital circuits. It introduces half adders, full adders, ripple carry adders, look ahead carry adders, and carry save adders. Half adders add two bits and produce a sum and carry output. Full adders add three bits. Ripple carry adders are made of cascaded full adders to add multiple bits, with each full adder inputting the carry from the previous stage. Look ahead carry adders reduce delay by calculating carry signals in parallel rather than series. Carry save adders add three bits in parallel and store the carry rather than propagating it to reduce delay.
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
This document describes the design and simulation of different 8-bit multipliers using Verilog code. It summarizes four multipliers: array, Wallace tree, Baugh-Wooley, and Vedic. It finds that the Baugh-Wooley multiplier has advantages in speed, delay, area, complexity, and power consumption compared to the other multipliers. The document also discusses half adders, full adders, ripple carry adders, carry save adders, and multiplication algorithms. It aims to compare the multipliers based on area, speed, and delay.
This tutorial tries to define and describe the concept of Auto and Cross Correlation and how to calculate the coefficients. The procedure for finding the auto and cross correlation coefficients are described with examples.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
The document describes five experiments performed using an 8085 microprocessor kit to understand various arithmetic operations. Experiment 1 adds two 8-bit numbers and stores the 8-bit sum. Experiment 2 adds two 8-bit numbers and stores the 16-bit sum. Experiment 3 adds two 16-bit numbers and stores the 16-bit sum. Experiment 4 performs decimal addition of two 8-bit numbers and stores the 8-bit sum. Experiment 5 finds the one's complement of an 8-bit number.
Question paper with solution the 8051 microcontroller based embedded systems...manishpatel_79
This document contains a question paper with solutions for the subject Microcontrollers from VTU's 4th semester B.E. examination from June-July 2013. The paper tests knowledge of CPU architectures like CISC, RISC, von Neumann, and Harvard. It also compares microprocessors and microcontrollers and tests understanding of interfacing 8051 microcontrollers to external memory. Finally, it examines the five addressing modes of 8051 - immediate, register, direct, indirect and indexed addressing - providing examples of each.
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
IMPLEMENTATION OF UPSAMPLING & DOWNSAMPLINGFAIZAN SHAFI
The process of converting the sampling rate of a digital signal from one rate to another is Sampling Rate Conversion. Increasing the rate of already sampled signal is Upsampling whereas decreasing the rate is called downsampling.
The purpose of Upsampling is to manipulate a signal in order to artificially increase the sampling rate.
To make a digital audio signal smaller by lowering its sampling rate or sample size (bits per sample). Downsampling is done to decrease the bit rate when transmitting over a limited bandwidth or to convert to a more limited audio format.
It depends on the level of certainty you need. If you don't need mathematical certainty and just want a heuristic, downsampling is faster and upsampling is more accurate.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has two main components: the Bus Interface Unit (BIU) handles bus operations like instruction fetching and memory access, while the Execution Unit (EU) decodes and executes instructions. The BIU contains registers for the code, data, extra, and stack segments as well as an instruction queue. The EU has registers for accumulation, base, count, data, pointers, and flags, and contains an ALU and decoder. It executes instructions from the queued bytes using a pipeline architecture.
Assembler directives and basic steps ALP of 8086Urvashi Singh
The document discusses various assembler directives used in assembly language programming. It describes directives like DB, DW, DD, DQ, DT for data declaration; ASSUME to define logical segments; END, ENDP, ENDS to mark ends; EQU to define constants; PROC and ENDP to define procedures; ORG to set the location counter; SEGMENT to define logical segments; GROUP, INCLUDE, EVEN, and ALIGN for segment organization; EXTRN and PUBLIC for external references; and TYPE and PTR for defining variable types. The directives provide necessary information to the assembler to understand assembly language programs and generate machine code.
The document discusses various jump, loop, and call instructions for the 8051 microcontroller. It provides examples of using conditional and unconditional jumps to transfer program flow. Looping is achieved using decrement and jump if not zero instructions. Nested loops allow repeating an action more than 256 times. Subroutines are called using call instructions which save the return address on the stack. Parameters can be passed into subroutines using registers or push/pop instructions.
The program demonstrates linear and circular convolution of sequences using MATLAB. For linear convolution, the conv function is used to convolve two input sequences and plot the results. For circular convolution, the FFT of each sequence is taken, multiplied together and inverse FFT applied to obtain the output, which is also plotted. The program thus allows generation and visualization of linear and circular convolution.
A 4x4 matrix keypad can be interfaced with an 8051 microcontroller to detect key presses. The rows of the keypad are connected to output port pins on the microcontroller, which are set high or low to scan each row. The columns are connected to input port pins, which the microcontroller reads to detect a low value, indicating a key press. By scanning each row and detecting the low column, the microcontroller can identify the specific key pressed. The document provides a circuit diagram and pin assignments for interfacing a 4x4 keypad with an 8051 development board to allow scanning and detecting keys.
Data Communication & Computer Networks: Multi level, multi transition & block...Dr Rajiv Srivastava
These slides cover the fundamentals of data communication & networking. It covers Multi level, Multi transition and Block codes which are used in communication of data. It is useful for engineering students & also for the candidates who want to master data communication & computer networking.
The document describes the goals of a project to design a dual-core superscalar computer system. It involves:
1. Designing each core with two pipelines, buffer registers at the beginning and end of each pipeline, and a finite state machine to control the instruction cycle.
2. Duplicating the design of the first core to create a second identical core.
3. Adding a shared memory for the cores to communicate through and share data.
4. Implementing new instructions using the wait state of the pipelines that allow writing to and reading from the shared memory and a general purpose register.
5. Creating a test methodology to demonstrate the full functioning of the dual-core superscal
Designed a 21b X 21b multiplier using Booth-2 algorithm by constructing schematic of decoder, partial product generation & compression and Adder (Carry Look Ahead). Performed Hspice simulation to verify the correct functionality, library characterization of assembled Netlist using Siliconsmart ACE, RTL synthesis of generated library. Timing and power consumed is analyzed through static timing analysis using Synopsys Primetime.
Registers are groups of flip-flops that store binary data. Shift registers can transfer data in serial or parallel formats. There are four basic modes of shift registers: serial-in serial-out, serial-in parallel-out, parallel-in serial-out, and parallel-in parallel-out. Counters are circuits made of flip-flops that count clock pulses and can be asynchronous, synchronous, decade, up/down, or cascaded to achieve different counts.
Shift registers allow for storage and movement of digital data. They consist of flip-flops connected in a chain so the output of one becomes the input of the next. There are several types of shift registers including serial in-serial out, serial in-parallel out, parallel in-serial out, and parallel in-parallel out. Special shift registers also exist like bidirectional and counter shift registers.
This document summarizes different types of adders used in digital circuits. It introduces half adders, full adders, ripple carry adders, look ahead carry adders, and carry save adders. Half adders add two bits and produce a sum and carry output. Full adders add three bits. Ripple carry adders are made of cascaded full adders to add multiple bits, with each full adder inputting the carry from the previous stage. Look ahead carry adders reduce delay by calculating carry signals in parallel rather than series. Carry save adders add three bits in parallel and store the carry rather than propagating it to reduce delay.
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
This document describes the design and simulation of different 8-bit multipliers using Verilog code. It summarizes four multipliers: array, Wallace tree, Baugh-Wooley, and Vedic. It finds that the Baugh-Wooley multiplier has advantages in speed, delay, area, complexity, and power consumption compared to the other multipliers. The document also discusses half adders, full adders, ripple carry adders, carry save adders, and multiplication algorithms. It aims to compare the multipliers based on area, speed, and delay.
This tutorial tries to define and describe the concept of Auto and Cross Correlation and how to calculate the coefficients. The procedure for finding the auto and cross correlation coefficients are described with examples.
The document provides information on the 8086 microprocessor, including:
- It was designed by Intel in the late 1970s and was used in early PCs.
- It has a 16-bit architecture and 20-bit address bus, allowing access to 1MB of memory.
- The 8086 CPU logic is partitioned into a Bus Interface Unit and Execution Unit, with the BIU handling bus operations and the EU executing instructions.
- The BIU generates physical addresses from logical addresses using segment registers and the instruction pointer. It also contains an instruction queue and registers.
- The EU contains general purpose registers, flags, and an ALU for arithmetic and logical operations.
The document describes five experiments performed using an 8085 microprocessor kit to understand various arithmetic operations. Experiment 1 adds two 8-bit numbers and stores the 8-bit sum. Experiment 2 adds two 8-bit numbers and stores the 16-bit sum. Experiment 3 adds two 16-bit numbers and stores the 16-bit sum. Experiment 4 performs decimal addition of two 8-bit numbers and stores the 8-bit sum. Experiment 5 finds the one's complement of an 8-bit number.
Question paper with solution the 8051 microcontroller based embedded systems...manishpatel_79
This document contains a question paper with solutions for the subject Microcontrollers from VTU's 4th semester B.E. examination from June-July 2013. The paper tests knowledge of CPU architectures like CISC, RISC, von Neumann, and Harvard. It also compares microprocessors and microcontrollers and tests understanding of interfacing 8051 microcontrollers to external memory. Finally, it examines the five addressing modes of 8051 - immediate, register, direct, indirect and indexed addressing - providing examples of each.
The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.
IMPLEMENTATION OF UPSAMPLING & DOWNSAMPLINGFAIZAN SHAFI
The process of converting the sampling rate of a digital signal from one rate to another is Sampling Rate Conversion. Increasing the rate of already sampled signal is Upsampling whereas decreasing the rate is called downsampling.
The purpose of Upsampling is to manipulate a signal in order to artificially increase the sampling rate.
To make a digital audio signal smaller by lowering its sampling rate or sample size (bits per sample). Downsampling is done to decrease the bit rate when transmitting over a limited bandwidth or to convert to a more limited audio format.
It depends on the level of certainty you need. If you don't need mathematical certainty and just want a heuristic, downsampling is faster and upsampling is more accurate.
The Intel 8086 is a 16-bit microprocessor that can access up to 1 MB of memory. It has two main components: the Bus Interface Unit (BIU) handles bus operations like instruction fetching and memory access, while the Execution Unit (EU) decodes and executes instructions. The BIU contains registers for the code, data, extra, and stack segments as well as an instruction queue. The EU has registers for accumulation, base, count, data, pointers, and flags, and contains an ALU and decoder. It executes instructions from the queued bytes using a pipeline architecture.
Assembler directives and basic steps ALP of 8086Urvashi Singh
The document discusses various assembler directives used in assembly language programming. It describes directives like DB, DW, DD, DQ, DT for data declaration; ASSUME to define logical segments; END, ENDP, ENDS to mark ends; EQU to define constants; PROC and ENDP to define procedures; ORG to set the location counter; SEGMENT to define logical segments; GROUP, INCLUDE, EVEN, and ALIGN for segment organization; EXTRN and PUBLIC for external references; and TYPE and PTR for defining variable types. The directives provide necessary information to the assembler to understand assembly language programs and generate machine code.
The document discusses various jump, loop, and call instructions for the 8051 microcontroller. It provides examples of using conditional and unconditional jumps to transfer program flow. Looping is achieved using decrement and jump if not zero instructions. Nested loops allow repeating an action more than 256 times. Subroutines are called using call instructions which save the return address on the stack. Parameters can be passed into subroutines using registers or push/pop instructions.
The program demonstrates linear and circular convolution of sequences using MATLAB. For linear convolution, the conv function is used to convolve two input sequences and plot the results. For circular convolution, the FFT of each sequence is taken, multiplied together and inverse FFT applied to obtain the output, which is also plotted. The program thus allows generation and visualization of linear and circular convolution.
A 4x4 matrix keypad can be interfaced with an 8051 microcontroller to detect key presses. The rows of the keypad are connected to output port pins on the microcontroller, which are set high or low to scan each row. The columns are connected to input port pins, which the microcontroller reads to detect a low value, indicating a key press. By scanning each row and detecting the low column, the microcontroller can identify the specific key pressed. The document provides a circuit diagram and pin assignments for interfacing a 4x4 keypad with an 8051 development board to allow scanning and detecting keys.
Data Communication & Computer Networks: Multi level, multi transition & block...Dr Rajiv Srivastava
These slides cover the fundamentals of data communication & networking. It covers Multi level, Multi transition and Block codes which are used in communication of data. It is useful for engineering students & also for the candidates who want to master data communication & computer networking.
The document describes the goals of a project to design a dual-core superscalar computer system. It involves:
1. Designing each core with two pipelines, buffer registers at the beginning and end of each pipeline, and a finite state machine to control the instruction cycle.
2. Duplicating the design of the first core to create a second identical core.
3. Adding a shared memory for the cores to communicate through and share data.
4. Implementing new instructions using the wait state of the pipelines that allow writing to and reading from the shared memory and a general purpose register.
5. Creating a test methodology to demonstrate the full functioning of the dual-core superscal
Designed a 21b X 21b multiplier using Booth-2 algorithm by constructing schematic of decoder, partial product generation & compression and Adder (Carry Look Ahead). Performed Hspice simulation to verify the correct functionality, library characterization of assembled Netlist using Siliconsmart ACE, RTL synthesis of generated library. Timing and power consumed is analyzed through static timing analysis using Synopsys Primetime.
The document discusses Monolithic Microwave Integrated Circuits (MMICs) and their fabrication process. MMICs are integrated circuits that operate at microwave frequencies between 300 MHz to 300 GHz. They are commonly made from gallium arsenide instead of silicon due to its advantages for high frequency applications. The document notes that MMICs are small in size, can be mass produced, and have allowed proliferation of devices like cell phones. It also provides background on the Solid State Physics Laboratory (SSPL) under India's Defense Research and Development Organization (DRDO) where the author conducted their internship work related to introduction of photolithography and study of metallization in gallium arsenide.
For more details: www.nick-let.com
For any enquires contact us @
E-mail id : rajbyrav7@gmail.com
Mobile No : 9790 89 1917.
Address:
#82,Station road,
Radha nagar,
Chrompet,
Chennai-44.
The proposed Vedic multiplier is based on traditional Vedic Sutras multiplication techniques that were used to multiply numbers in the decimal system. It uses the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" to multiply two numbers faster and with less area than other multipliers like booth and array multipliers. The Vedic multiplier proves to be highly efficient for applications like digital signal processing in terms of both speed and smaller area compared to other designs.
Fpga implementation of high speed 8 bit vedic multiplier using barrel shifter(1)Karthik Sagar
This document describes the implementation of an 8-bit Vedic multiplier using a barrel shifter on an FPGA. It begins with an introduction to Vedic mathematics and the Nikhilam sutra technique for multiplication. This technique reduces the number of partial products generated. The design uses a 64-bit barrel shifter in the base selection module and multiplier to significantly reduce the propagation delay compared to conventional multipliers. The 8-bit Vedic multiplier was implemented on a Xilinx Spartan-6 FPGA. Simulation results showed the design achieved a propagation delay of 6.781ns, demonstrating the speed improvement from using a barrel shifter.
DESIGN OF SIMULATION DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SAIKIR...Saikiran perfect
This project compares 4 different 8-bit multipliers - Wallace tree, array, Baugh-Wooley, and Vedic multipliers - using Verilog code. Simulations show that Wallace tree multipliers consume more power than array multipliers. Array multipliers are preferred for low power applications. The project designs and simulates the multipliers to analyze power consumption and determine the best option for low power, high speed applications like DSP systems.
Greetings from IGeekS Technologies ….
We were humbled to receive your enquiry regarding your academic project. We assure you to give all kinds of guidance for you to successfully complete your project.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Academic Projects
As a part of our vision to provide a field experience to young graduates, we offering academic projects to MCA/B.Tech/BE/M.Tech/BCA students. Normally our way of project guidance will start with in-depth training. Why because unless and until a student know the technology, he cannot implement a project. We designed such courses based on industry requirements.
Placements
Our support never ends with training. We are maintaining a dedicated consulting division with 5 HR executives to assist our students to find good opportunities. Once a student finishes his course and project, immediately we will collect their profiles and will contact with the companies. Since January 2010, more than 450 students got placed with the help of our quality training, project assistance and placement support.
Facilities
• Project confirmation and completion certificate.
• Project base paper, synopsis and PPT.
• In-depth training by industry experts
• Project guidance from experienced people
• Regular seminars and group discussions
• Lab facility
• Good placement assistance
• A CD which contains all the required softwares and materials.
• Lab modules with 100s of examples to improve students programming skills.
Please visit our websites for further information:-
www.makefinalyearproject.com
www.igeekstechnoloiges.com
We look forward to have you in our office for a detailed technical discussion for in-depth understanding of the base paper and synopsis. Our training methodology includes to first prepare the candidates to the relevant technology used in the selected project and then start the project implementation; this gives the candidate the pre-requisite knowledge to understand not only the project but also the code in which the project is implemented.The program concludes by issuing of project completion certificate from our organization.
We attached the proposed project titles for the academic year 2015. Find the attachment. Select the titles we will send the synopsis and base paper...If have any own topic (base paper) pls send us.we will check and confirm the implementation.
We will explain the base paper and synopsis, for technical discussion or admission contact Mr. Nandu-9590544567.
Presenation originally wrtten to support the teaching of OCR GCSE Mathematics Module 6, chapter 1: Using a calculator effectively.
BIDMAS/BODMAS (PEMDAS) and negative numbers.
Charles Roady has experience in programming, teaching technical skills, and working in food service. He has a Bachelor's degree in Physics from the University of California Berkeley with a minor in Computer Science. He is proficient in Python, Java, C, C++, C#, HTML, SQL and other languages. His most recent role was as a Technical Trainer at Kibo where he taught software engineering and client development skills. He is looking for an engaging position in the software industry applying his programming and analytical skills.
VLSI Implementation of Vedic Multiplier Using Urdhva– Tiryakbhyam Sutra in VH...iosrjce
This paper anticipated the design of a novel Vedic Multiplier using the techniques of Ancient Indian
Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly
on the multiplier as it is one of the key hardware blocks in most digital signal processing system as well as in
general processors. Currently the speed of the multipliers is limited by the speed of the adders used for partial
product addition. In this paper, we proposed an 8-bit multiplier using the new methodology of Vedic
Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products. The partial
product addition in Vedic multiplier is realized using carry-skip technique. This paper depicts the design of an
efficient 8×8 binary arithmetic multiplier by using Vedic Mathematics. From various multiplication techniques,
Urdhva-Tiryagbhyam sutra is being implemented because this sutra is applicable to all cases of algorithms for
N×N bit numbers and the minimum delay is obtained. A 4×4 Vedic Multiplier is designed using 9 –full adder
and a special 4-bit adder which is having reduced delay. Then 8-bit multiplier is designed using four 4-bit
multiplier and 3-ripple carry adder. Then 8×8 Vedic Multiplier is coded in VHDL, synthesized and simulated
using Xilinx ISE8.2 Software. Finally the objective of this paper lies in design of an efficient vedic multiplier
using Urdhva–Tiryakbhyam Sutra in VHDL Environment.
This document summarizes the history and development of scientific calculators. It discusses how the first calculators used vacuum tubes and transistors in the 1940s-1950s. The first pocket calculator was introduced in 1970 and used integrated circuits. Programmable calculators appeared in the mid-1960s and the first programmable pocket calculator was the HP-65 in 1974. The document also outlines the basic functions of calculators, improvements over time including the introduction of LCD displays, applications of calculators in education, and potential future modifications like touchscreens.
This document describes a MATLAB GUI project to create a graphical user interface for various signal processing and control systems functions. The project includes modules for a basic calculator, plotting functions, convolution, impulse response, step response, and bode plots. It aims to allow users to access these functions through a simple GUI without needing to write MATLAB code. The document outlines the functions, algorithms, and testing used for each module. It concludes that the project was successful in creating a user-friendly interface but that further improvements could allow for more customization and user-defined inputs.
- A scientific calculator is an invaluable tool for learning math and science that can help solve complex problems, as they provide functions like trigonometric, exponential, logarithmic, and statistical operations.
- Scientific calculators use different input methods, like algebraic notation where terms are entered in order of appearance or reverse polish notation (RPN) where values are entered before the operator.
- It is important to learn the functions and input methods of your specific scientific calculator by referring to the owner's manual. Understanding how to properly use the calculator ensures accurate results.
This document provides a summary of a scientific calculator project. It includes sections on the introduction, basic functions, proposed system description, system requirements, system design, source code, testing, and future scope. The introduction describes the calculator as a fully featured scientific calculator implemented with proper operator precedence and various mathematical functions. The basic functions section lists the addition, subtraction, multiplication, division, and other core functions included. The proposed system section outlines improving user friendliness, restricting access to data, and helping users view privileges. It also lists some key functions to be provided like viewing, adding, deleting and modifying data. The system requirements include operating system, language, processor, RAM, and hard disk needs.
This document discusses SQL and relational database management systems. It provides definitions of SQL, DML, DDL, and DCL. Common SQL commands like select, delete, update, and insert are listed. The differences between database management systems and relational database management systems are explained. Examples of database systems like Microsoft Access and SQL Server are provided. Finally, some sample tables for a library database are shown, along with recommendations to computerize the library's customer service and use RFID chips and access restrictions for security.
Design of low power barrel shifter and rotator using two phase clocked adiaba...eSAT Publishing House
This document summarizes the design of low power barrel shifters and rotators using two phase clocked adiabatic static CMOS logic. Barrel shifters and rotators were designed using a multiplexer-based approach and simulated in a 45nm CMOS process. The power consumption of the 2PASCL barrel shifter, rotator, and shifter/rotator circuits were compared to their static CMOS counterparts, showing a 69.67% reduction in power consumption for the 2PASCL circuits. Simulation results demonstrated the suitability of 2PASCL logic for low power applications like digital signal processors that require high speed and low power operation.
This document provides instructions for finding the perimeter of a triangle using the distance formula. It defines perimeter as the distance around a shape and explains it is calculated by adding the lengths of the sides. As an example, it gives the coordinates of points A, B, and C of triangle ABC and shows how to use the distance formula to calculate the lengths of sides AB and BC. It then prompts the reader to find the length of side AC and provides the steps to add the side lengths and calculate the perimeter of triangle ABC as 18.8.
This document describes a project report on implementing a 4-bit barrel shifter. It discusses using 2:1 multiplexers to build the barrel shifter circuit with 72 transistors. Code is provided to design the 4-bit barrel shifter using Verilog. Output waveforms show the barrel shifter shifting the input bits as determined by the select lines. Barrel shifters are useful for address decoding, arithmetic operations, and DSP applications as they can rapidly shift data based on control inputs.
A Fast Floating Point Double Precision Implementation on FpgaIJERA Editor
In the modern day digital systems, floating point units are an important component in many signal and image
processing applications. Many approaches of the floating point units have been proposed and compared with
their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for
floating point operations, single and double. In the proposed architecture double precision floating point unit is
used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high
speed adder, which is shared among other operations and can perform operations independently as a separate
unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing
technique which allows performing the operations with the minimum usage of the resources while computing
the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results
show the 23% improvement in the speed of the designed circuit
This document is a project report submitted by four students at the Institute of Engineering and Technology in Lucknow, India. It describes their work to improve the gain of an operational amplifier designed using 90nm technology. The students declare that the work is original and was conducted under the guidance of Dr. Tanmay Dubey. The report includes an abstract, introduction on operational amplifiers, description of the CMOS design process, simulation results, and conclusions on matching calculations to simulations. The head of the electronics department certifies that the project fulfills requirements for a Bachelor of Technology degree.
IRJET- Design of 16 Bit Low Power Vedic Architecture using CSA & UTSIRJET Journal
The document proposes a 16-bit low power Vedic architecture using the Urdhava Tiryakbhyam Sutra (UTS) method of Vedic mathematics and carry select adders. UTS allows for the parallel generation of partial products in multiplication, improving speed. The proposed design decomposes 16-bit numbers into pairs of 8-bit blocks, uses 8-bit UTS multipliers, and adds results with carry select adders. This structure is expected to reduce power consumption and delay compared to other multipliers.
Low power cmos binary counter using conventional flip flopsIAEME Publication
This document discusses low power CMOS binary counters. It proposes a clock gating technique for flip-flops to reduce power consumption in counters. It compares conventional non-clock gated, clock gated, and the proposed conditionally pulsed clock gating flip-flop designs. Simulation results in 0.18um CMOS technology show the proposed technique reduces power by 12% over conventional clock gating. Synchronous counters are chosen over asynchronous ones for their ability to scale to more bits with less delay per bit, important for reducing leakage power in high leakage technologies.
Implementation of 32 Bit Binary Floating Point Adder Using IEEE 754 Single Pr...iosrjce
Field Programmable Gate Arrays (FPGA) are increasingly being used to design high- end
computationally intense microprocessors capable of handling both fixed and floating- point mathematical
operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking
significant area. Over the years, the VLSI community has developed many floating-point adder algorithms
mainly aimed to reduce the overall latency. The Objective of this paper to implement the 32 bit binary floating
point adder with minimum time. Floating point numbers are used in various applications such as medical
imaging, radar, telecommunications Etc. Here pipelined architecture is used in order to increase the
performance and the design is achieved to increase the operating frequency. The logic is designed using VHDL.
This paper discusses in detail the best possible FPGA implementation will act as an important design resource.
The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area,
and levels of logic and analyzed specifically for one of the latest FPGA architectures provided by Xilinx.
High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Find...IJERA Editor
Addition is one of the common and widely used fundamental arithmetic operation in many VLSI systems. The critical elements in general purpose and digital-signal processing processors are High performance VLSI integer adders as they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. The performance parameters for any adder are area, speed and delay. By using Square Root Carry Select Adder (SQRT CSLA), speed can be achieved. In designing new architecture, the Tradeoff between those parameters plays the major role. We can reduce area by using Zero Finding Logic (ZFC) technique, from the structure of SQRT CSLA. By using the Modified architecture we can reduce area. We can implement Booth multiplier by using the CSLA and SQRT CSLA with Zero finding logic. Implementation of Booth multiplier by using CSLA and SQRT CSLA with Zero finding logic is proposed for better speed applications and efficient area applications.
DESIGN AND IMPLEMENTATION OF BIT TRANSITION COUNTERcsijjournal
In today’s VLSI system design, power consumption is gaining more attention as compared to performance and area. This is due to battery life in portable devices and operating frequency of the design. Power consumption
mainly consists of static power, dynamic power, leakage power and short circuit power. Dynamic power is dominant among all which depends on many factors viz. power supply, load capacitance and frequency. Switching
activity also affects dynamic power consumption of bus which is determined by calculating the number of bit transitions on bus. The purpose of this paper is to design a bit transition counter which can be used to calculate the
switching activity of the circuit nodes. The novel feature is that it can be inserted at any node of the circuit, thus helpful for calculating power consumption of bus.
Performance analysis of gesture controlled robotic careSAT Journals
Abstract
“ROBOT” is any automatically operated machine or a device that reduces human effort, though it may not look much like a
human being or function in a humanlike manner. Advanced, high-performance robots are used today in automobile
manufacturing and aircraft assembly, and electronics firms use robotic devices together with other computerized instruments to
sort or test finished products. Due to the demand of intelligent systems in every field of technology, automated systems are
preferred much for the betterment of the society.The main objective of designing this robo car is to make the world work with
more comfort and more easier way with the way they use today ,as in the recent era there were too many research in the field of
robotics and communication has happened ,so we tried to focus both robotics as by designing a small robocar and controlling
over RF frequency wirelessly for communication as the ease of access is our main priority we tried to focus also the comfort
ability and design a gesture based robotic car. This car not only detects the motion of a human hand but also reacts according to
the gesture, the main purpose of the bot is to make the world work with more ease or where the work of precision or accuracy is
needed it can also be used for the spying and for the field observation or in the industries where the work precision is made with
the use of human hand but it’s not comfortable due to hazardous object, we can have example of industries where furnace
temperature or a pressure is controlled through the accuracy of a knob controlled with human hand but working beside the boiler
or a furnace is always a risk task hence it is not possible so can be operated through gesture at a distance and operated can
operate knob by simply sitting in the cabin and through gesture of the handjust like virtually adjusting the knob or the control of
the robotic car.
Keywords: Gesture Based Robotic Car, Robotic Car, Robocar,
IRJET - Design of a Low Power Serial- Parallel Multiplier with Low Transition...IRJET Journal
This document describes the design of a low power serial-parallel multiplier that uses a modified radix-4 Booth algorithm. It aims to improve performance over a standard serial-parallel Booth multiplier in terms of area, delay, and power. The proposed multiplier generates partial products conditionally, adding only non-zero Booth encodings and skipping zero operations to reduce transitions and increase throughput. It is implemented using FPGA technology to evaluate its utility for applications like digital signal processing and machine learning that require high performance multiplication.
IRJET - Low Power M-Sequence Code Generator using LFSR for Body Sensor No...IRJET Journal
The document describes a proposed low power m-sequence code generator using a linear feedback shift register (LFSR) for body sensor node applications. An LFSR generates pseudo-random binary sequences through a linear feedback function combining bits in the shift register. The document evaluates different designs for the XOR gates used in the feedback function, finding a transmission gate based design consumes significantly less power than other designs. It then proposes a 7-bit m-sequence code generator using a 3-stage LFSR with XOR gates in the feedback loop for low power consumption, suitable for use in wireless body sensor nodes.
IRJET- Data Acquisition using Tensile Strength Testing MachineIRJET Journal
This document describes a tensile strength testing machine that was designed to test the strength of textile materials. It discusses the various components of the machine, including the load cell, rotary encoder, microcontroller, analog-to-digital converter (ADC), and other electronic components. The machine is able to automatically record the load and elongation of a specimen as it is placed under increasing tensile stress. The load, elongation, and other data are sent to a computer for analysis. The design of the data acquisition system and electronic components is explained, and the machine is able to accurately measure and record the load-elongation curve of textile specimens during strength testing.
This document is a project report submitted by a group of students for their Design Engineering course. It details the development of an Automatic Railway Crossing System (ARC) over multiple semesters. In the 6th semester, the students developed a PLC circuit board and program to control the ARC. They tested the circuit and program on a DELTA DVP-14SS2 PLC. The report provides snapshots of the PLC program and discusses modeling software, engineering economics, prototyping, materials selection, and future improvements including using renewable energy sources.
IRJET- MAC Unit by Efficient Grouping of Partial Products along with Circular...IRJET Journal
This document describes a proposed MAC (multiply and accumulate) unit design that aims to improve performance and reduce resource usage compared to conventional pipeline MAC unit designs. The proposed design uses Booth encoding to reduce the number of partial products, groups the partial products into blocks that are added using multi-operand adders, and implements circular convolution by rearranging the partial products. Simulation results show that the proposed design achieves higher performance and lower resource usage than conventional pipeline and redundant carry-save MAC unit designs. The design is synthesized on an Altera Stratix III FPGA to take advantage of fast carry chains.
Layout Design Analysis of SR Flip Flop using CMOS TechnologyIJEEE
This paper presents an area, delay and power efficient design of SR flip flop. As the chip manufacturing technology is on the threshold of evaluation, which shrinks a chip in size and enhances its performance, here the flip flop is implemented in a layout level which develops an optimized design using recent CMOS layout tools. The proposed SR flip flop has been designed and simulated using 45nm technology. After that, parametric analysis has been done. In this paper, flip flop has been developed using full automatic design flow and semi-custom design flow. The performance of SR flip flop layouts using different design flows has been analyzed and compared in terms of area, delay and power consumption. The simulation results show that the design of SR flip flop using semi-custom design flow improved the area occupied by 46.9% and power consumption is reduced by 38.4%.
IRJET-Fuzzy Logic Based Path Navigation for Robot using MatlabIRJET Journal
This document describes a fuzzy logic-based path navigation system for a robot using MATLAB. The system uses infrared sensors to detect obstacles and a fuzzy logic controller with four input and two output variables to navigate around static obstacles. If moving obstacles are detected, the system generates a trajectory prediction table to plan a new path to avoid collisions. The system was tested in a simulator environment with static and moving obstacles and was able to successfully navigate to a target location while avoiding obstacles. The fuzzy logic controller provided an effective way to control the robot's direction and generate smooth motion to reach the target safely.
AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION...VLSICS Design
Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.
IRJET- Single Precision Floating Point Arithmetic using VHDL CodingIRJET Journal
The document describes a VHDL implementation of single precision floating point arithmetic operations using an FPGA. It begins with an introduction to floating point arithmetic and FPGAs. It then discusses related work on floating point implementations and the IEEE 754 single precision format. The proposed algorithm and block diagram for a single precision floating point adder are presented. Simulation results demonstrating addition, subtraction, multiplication and division are also shown. The implementation of single precision floating point arithmetic using VHDL coding allows for low-cost and reprogrammable hardware. The design was synthesized using Xilinx tools and implemented on a Virtex-7 FPGA.
This document describes a project to design a 4-bit arithmetic circuit using multiplexers and full adders. It begins with an abstract stating that combinational logic circuits will be used to perform arithmetic operations on 4-bit binary numbers. It then provides descriptions of the key components used - multiplexers, full adders, and arithmetic logic units. The design section explains that the project will implement a 4-bit arithmetic circuit using multiplexers and full adders. Pin diagrams are also provided for the IC chips used in the multiplexers and full adders.
Similar to A Computers Architecture project on Barrel shifters (20)
Simple Blockchain Eco System for medical data managementsvrohith 9
The blockchain is one of the most ingenious inventions. It changed traditional approach to the transactions that are made between computers virtually, Blockchain allows digital format of information to travel across the world without being tampered, was originally made for bitcoin exchanges which were a virtual currency that was circulated by open source developers and certain hosting companies. Since it is secure and incorruptible digital ledger, we made our project to store all the transactions based on custom SHA-256 and Base64 encoding methods, since blockchain is based on the peer-to-peer network the other mediums never know the hashed content. The database updates are shared across the network and so it resists from single point failure, being controlled by certain authority, Overriding of data.
A mini project on designing a DATABASE for Library management system using mySQLsvrohith 9
It keeps track of all the information about the books in the library, their cost, status and total number of books available in the Library. The user will find it easy in this automated system rather than using the manual writing system. The system contains a database where all the information will be stored safely.
~> All the data types and variables,
~> test SQL-QUERIES
~> database is in the above document
A Measurements Project on Light Detection sensorsvrohith 9
The main aim of this project is to saving system with LDR this is to save the power. We want to save power automatically instead of doing manual. So it’s easy to cost effectiveness. This saved power can be used in some other cases. So in villages, towns etc. we can design intelligent systems for the usage of light or we can also use this to reduce the electricity bill of our home. This project can also be used for security of the houses, banks, etc.
A Software Engineering Project on Cyber cafe managementsvrohith 9
Cyber Café Management is a complete package developed for management of systems in a cyber café. This project is intended to be used in a Cyber Café. All cyber cafes have some basic needs likeable to control the systems that are being rented to the customers and are charged on timely basis.
The present project presented in:-
1. Use case diagram
2. Sequence diagram
3. Activity diagram
4. Class diagram
This document contains a case study on pollution from pesticides and chemicals on plants. It begins with an introduction that defines pesticides and discusses how while they can protect plants from pests, they also pose risks to humans, animals, and the environment. The case study objectives are to discuss the effects of pesticide pollution on plants and the environment, conclude with advantages and disadvantages, and provide suggestions. It focuses on the impacts of pesticide use and potential alternatives.
This lab report describes developing a program to perform string operations using suffix arrays. It includes 3 modules: 1) Finding the longest repeated substring, 2) Finding the longest common substring, and 3) Finding the longest palindrome in a string. The report provides code for building a suffix tree from a string and performing traversal to solve each problem. It also includes sample outputs and references.
This document discusses using MATLAB to solve differential equations related to electric circuits. It begins by explaining some advantages of MATLAB, such as its use of matrices, vectorized operations, and graphical output capabilities. It then provides an example of using MATLAB to solve the first order differential equation iR+Ldi/dt=E(t), which models an LCR circuit. The document also discusses solving second order differential equations manually and with MATLAB code. It provides an example of solving the second order equation d2q/dt2+10dq/dt+250q=0 both manually and using MATLAB code.
Taipai 101 Tower is a 508m tall skyscraper located in Taipei, Taiwan. It has 101 floors and was designed by C.Y. Lee & Partners with structural engineering by Thornton Tomasetti. The tower uses tuned mass dampers and a strong foundation of 380 piles to resist earthquakes and typhoon winds common in coastal Taipei. It is a landmark in Taipei known for its eco-friendly design including energy efficiency, rainwater harvesting, and prohibiting smoking.
The document summarizes the key features and design of the new MacBook laptop. It has a 12-inch LED-backlit display, Intel Core M processor, 8GB RAM, and up to 10 hours of battery life. It features a redesigned butterfly keyboard that is thinner and has individual key backlighting. The trackpad was also redesigned and uses force sensors in each corner along with haptic feedback. The logic board was shrunk by 67% and the fan was removed due to the efficient Intel Core M chip. The battery uses a custom terraced design for more capacity in the thin enclosure. The laptop has a single USB-C port that handles power and connectivity. It was designed for maximum energy efficiency and
The document describes the technical specifications, design, software capabilities, and competitive advantages of the original Apple iPhone. It includes details on the 3.5 inch screen, OS X operating system, 2 megapixel camera, battery life, dimensions, weight, touch screen interface, audio capabilities, full OS X functionality, and how the iPhone compared favorably to competitors on factors like ease of use, fashionability, and media playback. Recycling and pricing strategies are proposed to make the iPhone more environmentally friendly and maintain its premium brand image.
Building a Raspberry Pi Robot with Dot NET 8, Blazor and SignalRPeter Gallagher
In this session delivered at NDC Oslo 2024, I talk about how you can control a 3D printed Robot Arm with a Raspberry Pi, .NET 8, Blazor and SignalR.
I also show how you can use a Unity app on an Meta Quest 3 to control the arm VR too.
You can find the GitHub repo and workshop instructions here;
https://bit.ly/dotnetrobotgithub
A Computers Architecture project on Barrel shifters
1. 1
COMPUTER ORGANIZATION AND ARCHITECTURE
PROJECT BASED LAB REPORT
On
16-BIT BARREL SHIFTER
Submitted in partial fulfillment of the
Requirements for the award of the Degree of
Bachelor of Technology
In
COMPUTER SCIENCE ENGINEERING
By
V.Sowjanya (150030965)
V.V.S. Hari Krishna (150030998)
S.V. Rohith (150031000)
UNDER THE GUIDENCE
OF
M.VASUJA DEVI
DEPARTMENT OF COMPUTER SCIENCE ENGINEERING
K L UNIVERSITY
Green Fields, Vaddeswaram, Guntur district-522 502
2. 2
CERTIFICATE
This is to certify that the course based project titled 16 BIT BARRREL SHIFTER being
submitted by
V.SOWJANYA (150030965)
V.V.S.HARI KRISHNA (150030998)
S.V.ROHITH (150031000)
in partial fulfilment for the award of degree of Bachelor of Technology in COMPUTER
SCIENCE ENGINEERING is a record of bonfide work carried out by them under my
guidance during the academic year 2016-2017 and it has been found worthy of acceptance
according to the requirements of the university.
UNDER THE GUIDENCE
OF
M.VASUJA DEVI
3. 3
DECLARATION
We hereby declare that this project based lab report entitled “16-BIT BARREL
SHIFTER” has been prepared by using logisim partial fulfilment of the requirement for
the award of degree “BACHELOR OF TECHNOLOGY in COMPUTER SCIENCE
AND ENGINEERING” during the academic year 2016-17.
I also declare that this project based lab report is of our own effort and it has not been
submitted to any other university for the award of any degree.
Place: KLU
Date: Signature of the Student
4. 4
ACKNOWLEDGEMENTS
My sincere thanks to Mr. SIDHESWAR ROVATRAY in the Lab for his outstanding
support throughout the project for the successful completion of the work.
We express our gratitude to Dr.V. SRIKANTH, Head of the Department for Computer
Science and Engineering for providing us with adequate facilities, ways and means by which
we are able to complete this term paper work.
We would like to place on record the deep sense of gratitude to the honorable Vice
Chancellor, K L University for providing the necessary facilities to carry the concluded term
paper work.
Last but not the least, we thank all Teaching and Non-Teaching Staff of our department and
especially my classmates and my friends for their support in the completion of our term paper
work.
By
S.V. Rohith-150031000
V.V.S. Hari Krishna-150030998
6. 6
1. Abstract
This project aims to build a 'BARREL SHIFTER' which is a digital circuit that
can shift a data word by a specified number of bits without the use of any sequential
logic, only pure combinatorial logic. One way to implement it is as a sequence of
multiplexers where the output of one multiplexer is connected to the input of the next
multiplexer in a way that depends on the shift distance. A barrel shifter is often used
to shift and rotate n-bits in modern microprocessors, typically within a single clock
cycle. Hence we intend on designing the circuit which could shift the given input of 8-
bits using the multiplexors. A common usage of a barrel shifter is in the hardware
implementation of floating-point arithmetic. For a floating-point add or subtract
operation, the significands of the two numbers must be aligned, which requires
shifting the smaller number to the right, increasing its exponent, until it matches the
exponent of the larger number. This is done by subtracting the exponents, and using
the barrel shifter to shift the smaller number to the right by the difference, in one
cycle. If a simple shifter were used, shifting by n bit positions would require n clock
cycles. Hence this shifter is useful for shifting n bits’ same time and has a real time
application in the microprocessors of the computers. So we intend to design the circuit
in the logisim software and simulate it to check the results of the circuit.
A Barrel Shifter is a logic component that perform shift or rotate
operations. Barrel shifters are applicable for digital signal processors and processors.
This component design is for a natural size (4,8,16…) barrel shifters that perform shift
right logical, rotate right, shift left logical, and rotate left operations depending on the
instantiation parameters. The left and right operation is implemented through
inversion of the input and output vectors, so the basic multiplexing function can
perform both operations. The number of multiplexing stages is relative to the width of
the input vector.
7. 7
2. INTRODUCTION
A Barrel Shifter is a logic component that
perform shift or rotate operations. Barrel shifters are applicable for digital signal
processors and processors. This component design is for a natural size (4,8,16…)
barrel shifters that perform shift right logical, rotate right, shift left logical, and rotate
left operations depending on the instantiation parameters. The left and right operation
is implemented through inversion of the input and output vectors, so the basic
multiplexing function can perform both operations. The number of multiplexing
stages is relative to the width of the input vector.
A barrel shifter is a digital circuit that can shift a data word by a specified number of
bits. It can be implemented as a sequence of multiplexers. In this implementation, the
output of one MUX is connected to the input of the next MUX in a way that depends
on the shift distance. The number of multiplexers required is n*log2(n), for an n bit
word. Four common word sizes and the number of multiplexers needed are listed
below:
64-bit — 64 * log2(64) = 64 * 6 = 384
32-bit — 32 * log2(32) = 32 * 5 = 160
16-bit — 16 * log2(16) = 16 * 4 = 64
8-bit — 8 * log2(8) = 8 * 3 = 24
Basically, a barrel shifter works to shift data by incremental stages which avoids extra
clocks to the register and reduces the time spent shifting or rotating data (the specified
number of bits are moved/shifted/rotated the desired number of bit positions in a
single clock cycle). A barrel shifter is commonly used in computer-intensive
applications, such as Digital Signal Processing (DSP), and is useful for most
applications that shift data left or right - a normal style for C programming code.
Rotation (right) is similar to shifting in that it moves bits to the left. With rotation,
however, bits which "fall off" the left side get tacked back on the right side as lower
order bits, while in shifting the empty space in the lower order bits after shifting is
filled with zeros. Data shifting is required in many key computer operations from
address decoding to computer arithmetic. Full barrel shifters are often on the critical
path, which has led most research to be directed toward speed optimizations. With the
advent of mobile computing, power has become as important as speed for circuit
8. 8
designs. In this project we present a range of 32-bit barrel shifters that vary at the gate,
architecture, and environment levels.
3. Design specification of circuit
Barrel shifter functionality
The Barrel shifter component is applicable for cases where an efficient logical shift or
rotate with a selectable shift amount is required. The component supports either shift
or rotate operations depending on the ROTATION parameter. When the ROTATION
parameter is set to 1, the barrel shifter performs rotation and when it is set to 0, a
logical shift operation is performed, shifting logical 0 in. the DIRECTION parameter
determines if the barrel shifter performs a left or right shift. Setting the DIRECTION
9. 9
parameter to 0 would result in a left shift and setting it to 2 would result in a right
shift.
Logarithmic shift
The shift or rotate operation is done in stages where each stage performs a shift or
rotate operation of a different size. For example, a 5 bits shift operation would result
in a shift of 4 and a shift of 1 where the stage that performs the shift of 2 would not do
any shift. The select vector binary encoding is actually to enable the different stages of
the barrel shifter.
10. 10
Shift direction
The direction of the rotate and shift operation is implemented by reversing the input and
output vector. Using this method allows for the shift or rotate logic to be kept simple,
performing only right shift. For a left shift, the input vector is reversed at the input, goes
through the shift logic which performs a right shift according to the select input and at the
output stage, it is reversed again, resulting in a left shift of the vector.
15. 15
10.CONCLUSION
The reason behind undertaking this project simply lies with the fact that there
are so many circuits that have more power consumption and delay, so to minimize the area
and delay we are using shifting or rotation. Here we are doing shift right logical, shift right
arithmetic, rotate right, shift left logical, shift left arithmetic, and rotate left. Four different
barrel shifter designs are presented and compared in terms of area and delay for a variety of
operand sizes. This is also examining techniques for detecting results that overflow and
results of zero in parallel with the shift or rotate operation. To resolve this purpose we have
made this very project, so that if such a kind of system is used then at least it may be able to
sense the shifting or rotation and accordingly necessary conditions can be undertaken.
11.FUTURE EXPECTS
The future expects of barrel shifter is that it minimizes the area and power
delay of the circuit. Area and delay estimates, based on synthesis of structural level VHDL,
indicate that data‐reversal barrel shifters have less area than two's complement or one's
complement barrel shifters and that mask‐based data‐reversal barrel shifters have less delay
than the other designs. As the operand size increases, the delay of the shifters increases as
O(log(n)) and their area increases as O (n log(n)). In to the future expectation we attach a
overflow detection logic, so the data should not be waste.
12.REFERENCES
1.www.quora.com
2.www.wikipedia.com
3.Electroincs Engineer's Reference Books by FF Mazda
4.Switching Theory by William Howard
5.Computer Organization and Architecture by William Stallings